INSTRUCTION SET

ARCHITECTURE
Rashid Mehmood
Basic Microcomputer Design
DESIGN OF INSTRUCTIONS SET
Designing an Instruction Set Architecture (ISA) for a small-level processor involves
several key steps. Here’s a structured approach:

1. Define Processor Goals and Constraints

Performance Goals: Determine the desired speed, efficiency, and application domain.
Resource Constraints: Consider the limitations in hardware resources such as memory,
processing power, and energy consumption.
2. Determine Instruction Types
Arithmetic and Logic: Define operations for addition, subtraction, multiplication, division, and
logical operations (AND, OR, NOT).
Data Transfer: Specify instructions for moving data between registers, memory, and
I/O devices.
Control Flow: Include instructions for branching (conditional and unconditional) and
loops.

Input / Output Operations: Define how the processor will handle I/O operations.
DESIGN OF INSTRUCTIONS SET

3. Design the Instruction Formats:

Opcode: Define the operation code that specifies the instruction type.
Operands: Specify how many operands are needed, their types (registers, immediate values),
and how they are represented.
Fields: Determine the number of bits for each field (opcode, operands, addressing
modes).

4. Choose Addressing Modes:

Immediate: Operand is a constant value included in the instruction.
Register: Operand is in a register.
Direct: Address of the operand is specified in the instruction.
Indirect: Address of the operand is specified by a register.
Indexed: Address is computed by adding a constant value to the content of a register.
DESIGN OF INSTRUCTIONS SET

5. Define Registers:
General-Purpose Registers: Decide on the number and size.
Special-Purpose Registers: Include program counter (PC), stack pointer (SP),
and status registers
6. Design the Execution Model:
Pipeline Stages: Define if and how pipelining will be implemented
Instruction Execution: Specify how instructions will be decoded and executed.

7. Specify Memory Organization:

Memory Addressing: Define how memory addresses are calculated and
accessed
Memory Access: Decide on access methods (byte-addressable, word-
addressable).
DESIGN OF INSTRUCTIONS SET
8. Create an Instruction Set Manual:
Instruction Descriptions: Provide detailed descriptions of each instruction, including
syntax, semantics, and usage examples
Instruction Timing: Detail the execution time for each instruction if relevant.:

9. Simulation and Testing:

Model the ISA: Use simulation tools to test the ISA design
Benchmarking: Run tests and benchmarks to evaluate performance and identify
bottlenecks

10. Iterate and Refine:

Gather Feedback: Get feedback from users and developers.
Optimize: Refine the ISA based on practical considerations and performance data.
8086 INSTRUCTION SET
The Intel 8086 is a 16-bit microprocessor that was introduced in 1978

8086(Machine Language Instruction Formats)

• A machine language instruction format has one or more number of fields associated with it.

• The first field is called as operation code field or op-code field, which indicates the type of operation to be
performed by the CPU

• The instruction format also contains other fields known as operand fields

• The CPU executes the instruction using the information which reside in these fields

• There are six general formats of instructions in 8086 instruction set.

• The length of an instruction may vary from 1 byte to 6 bytes. The instruction formats are described as
follows
For multiple-byte words stored in Main Memory there are two different conventions:

– Little Endian

• Little Endian byte order puts the byte whose address is "x...x00" at the least
significant position in the word (the little end)

• In Little Endian, the address of a datum is the address of the least significant byte (LSB

– Big Endian

• Big Endian byte order puts the byte whose address is "x...x00" at the most significant
position in the is "x...x00" at the most significant position in the word (the big end)

• In Big Endian addressing, the address of a datum is the address of the most significant byte
(MSB)
X86 - ISA-16
• generally refers to the 16-bit instruction set architecture
used in early x86 processors

• particularly the Intel 8086/8088

• This architecture laid the foundation for the x86 family

of processors.
Key Features of x86 ISA-16:
16-Bit Data Bus: Supports 16-bit data operations, allowing for the processing of larger
integers compared to 8-bit architectures.

Segmented Memory: Utilizes a segmented memory model, dividing memory into segments
(code, data, stack) to extend the addressable space beyond 64KB (the limit for a 16-bit
address).

Registers: Includes several general-purpose registers (AX, BX, CX, DX), segment registers
(CS, DS, SS, ES), and pointer/index registers (SP, BP, SI, DI).

Instruction Set: Supports a variety of instructions for arithmetic, logic, control, and data
movement. Notable instructions include ADD, SUB, MOV, and JMP.

Operating Modes: Primarily runs in real mode, allowing direct access to hardware and
memory but with limited protection.

Compatibility: The ISA-16 is compatible with subsequent x86 architectures, allowing 16-
bit applications to run on later 32-bit and 64-bit processors.
Types of ISA-16 Instructions:

The x86 ISA-16 includes around 100 to 200 instructions, depending on

how you count variations and addressing modes. Here’s a breakdown of the
main categories of instructions:

1. Data Transfer Instructions: MOV, PUSH, POP, etc.

2. Arithmetic Instructions: ADD, SUB, MUL, DIV, etc.
3. Logic Instructions: AND, OR, XOR, NOT, etc.
4. Control Flow Instructions: JMP, CALL, RET, etc.
5. String Instructions: MOVSB, MOVSW, CMPSB, etc.
6. Bit Manipulation Instructions: SHL, SHR, ROL, ROR, etc.

Each of these categories can have multiple variants based on operand

types and addressing modes
 Variants of MOV Instruction:
1. Register to Register
MOV r1, r2 :Move data from one register to another (e.g., MOV AX, BX).

2. Immediate to Register
MOV r1, immediate : Load an immediate value into a register (e.g., MOV AX, 5).

3. Memory to Register
MOV r1, [address] : Move data from memory into a register (e.g., MOV AX, [1234h]).

4. Register to Memory
MOV [address], r1 : Move data from a register to a memory location (e.g., MOV [1234h], AX).

5. Immediate to Memory
MOV [address], immediate : Load an immediate value into a memory location (e.g., MOV [1234h], 5).

6. Segment Register Variants

MOV segment register, r1 : Move data from a general-purpose register to a segment register (e.g., MOV DS, AX).
MOV r1, segment register: Move data from a segment register to a general-purpose
register.
Key Features of x86 ISA-32:
32-Bit Data Bus: The ISA supports 32-bit data operations, allowing for more extensive data handling compared
to 16-bit architectures.

Flat Memory Model: Unlike the segmented model in ISA-16, ISA-32 introduces a flat memory model,
simplifying addressing and allowing direct access to up to 4GB of memory.

Extended Register Set: Introduces additional general-purpose registers (EAX, EBX, ECX, EDX) that are 32 bits
wide, along with the extended versions of existing registers (e.g., ESI, EDI, EBP, ESP).

Enhanced Instruction Set: ISA-32 includes a broader range of instructions and improved support for complex
data types and operations.

Protected Mode: Introduces protected mode, allowing for better memory management, multitasking, and access
control, which is critical for modern operating systems.

Support for Virtual Memory: Enhances the architecture's ability to manage virtual memory, enabling more
efficient use of RAM.

Instruction Extensions: Includes additional instruction sets such as MMX, SSE, and later extensions that
enhance multimedia processing and floating-point operations.
Instruction Categories
ISA-32 instructions similar to ISA-16 categorized into:

1. Data Transfer Instructions: MOV, PUSH, POP, XCHG

2. Arithmetic Instructions: ADD, SUB, MUL, DIV, INC, DEC

3. Logical Instructions: AND, OR, XOR, NOT

4. Control Flow Instructions: JMP, CALL, RET, LOOP, INT

5. String Manipulation Instructions: MOVSB, MOVSW, CMPSB, SCASB

6. Bit Manipulation Instructions: SHL, SHR, ROL, ROR

How many instructions are there in ISA-32 ?

The x86 ISA-32 instruction set includes several hundred instructions, typically estimated to be
around 200 to 300 core instructions, depending on how variations and different addressing modes
are counted
 MMX (MultiMedia Extensions)

MMX (MultiMedia Extensions) is an instruction set extension to the x86 architecture, introduced by Intel in
1996 with the Pentium MMX processor. It was designed to accelerate multimedia and signal processing
applications by allowing parallel processing of multiple data points.

Key Features of MMX

Packed Data Types: MMX allows operations on packed integers, enabling the simultaneous processing of
multiple data elements. For instance, it can handle multiple 8-bit or 16-bit integers in a single instruction.

Registers: MMX introduces a set of eight 64-bit registers (MM0 to MM7) that are used specifically for
MMX operations. These registers can hold packed data types.

Integer Operations: MMX primarily focuses on integer arithmetic and logical operations rather than
floating-point calculations.

Backward Compatibility: MMX instructions are designed to be backward compatible with existing x86
code, allowing applications to run without modification.
 MMX (MultiMedia Extensions)

Instruction Count MMX includes approximately 57 instructions, covering a range of operations like:

Arithmetic Operations: ADD, SUB, etc.

Logical Operations: AND, OR, XOR, NOT.
Shift Operations: SHL, SHR, etc.
Data Movement: MOV, PUNPCK (for unpacking data).
Comparison: PCMPEQ (compare for equality), etc.

MMX was a significant step towards enhancing multimedia processing capabilities in processors and
set the stage for later SIMD (Single Instruction, Multiple Data) extensions like SSE (Streaming SIMD
Extensions), which further expanded the range and type of operations that could be performed in
parallel
 SSE (Streaming SIMD Extensions)
SSE (Streaming SIMD Extensions) is a set of instructions introduced by Intel starting with the Pentium III processor in
1999. It enhances the x86 instruction set for performing SIMD (Single Instruction, Multiple Data) operations, primarily
aimed at improving the performance of multimedia applications, 3D graphics, and scientific computations.

Key Features of SSE

Packed Data Types: SSE supports operations on packed data types, allowing for parallel processing of multiple data
elements in a single instruction.

128-Bit Registers: SSE introduces a new set of 128-bit registers (XMM0 to XMM7) for holding packed data, allowing
for more efficient processing of data.

Data Types Supported: SSE works with various data types, including:
Packed single-precision floating-point (32 bits)
Packed double-precision floating-point (64 bits)
Packed integers (various sizes)

Floating-Point Operations: SSE enhances floating-point computation capabilities, making it suitable for a range of
applications like graphics and scientific calculations.
Instruction Categories
Arithmetic Operations ADDPS: Add packed single-precision floating-point values.
SUBPS: Subtract packed single-precision floating-point values.
MULPS: Multiply packed single-precision floating-point values.

Logical Operations: ANDPS: Bitwise AND on packed single-precision floating-point values.

ORPS: Bitwise OR on packed single-precision floating-point values.

Comparison Operations: CMPPS: Compare packed single-precision floating-point values.

CMPEQPS: Compare for equality.

Data Movement: MOVAPS: Move aligned packed single-precision floating-point values.

MOVUPS: Move unaligned packed single-precision floating-point values.

Conversion Operations: CVTSI2SS: Convert integer to scalar single-precision floating-point.

CVTSS2SI: Convert scalar single-precision floating-point to integer.

Horizontal Operations: HADDPS: Horizontal add of packed single-precision floating-point values.

HSUBPS: Horizontal subtract of packed single-precision floating-point values.
Instruction Count
SSE has about 70 instructions in its initial specification.

Subsequent extensions, such as

 SSE2

 SSE3

 SSE4

 AVX

 AVX2

 AVX 512