Blocking and Non-

Blocking
Contexts
• Blocking Statements and Non-Blocking statements
• Examples
• Verilog Regions
• System Verilog Regions
• System tasks
 Blocking and Non-Blocking
Assignment
Example of blocking assigments
Example of Non-blocking
Assignment
Example
Verilog Regions
• Active region Continuous assignments
Procedural assignments
Active region
• Inactive region $display and $write
Evaluate the RHS of Non-blocking
• NBA region
(Non-blocking Assignments) Inactive region #0 blocking assignment

• $monitor region
Updation LHS value of non-
NBA blocking Assign

Postponed $monitor and $strobe

System Verilog Regions
Preponed Assertion will trigger

Module Active

Inactive

NBA

Observed Assertion evaluate the expression

Reactive Assertion pass or fail

Program block
Re-inactive

Re-NBA

Postponed
System tasks
$display:-executed in the 0 simulation time
$monitor:-executes every time whenever the value changes
$strobe:-executes at the end of the simulation
$write:- To display strings, variables, and expressions without
appending the newline at the end of the message
$finish:- terminate the current simulation
$stop:- The $stop task suspends the simulation at the point where it is called
Example of $display and $write
Example of $display and $strobe
Example of $monitor
Events
Introduction
• Events are used to synchronize the execution of the process in
conjunction with wait statements to control the stimulus time.
Wait Order
• Wait for events to be triggered in the given order and issue an error if
any event executes out of order.
 Merge Events
• When one events variable is assigned
to another, all processes waiting for the
first event to trigger will wait until the
second variable if triggered.
Threads
Types of fork join
Fork join
Fork-join :- In fork-join, all processes start simultaneously,
and join will wait for all processes to be completed.
Fork_join any
• In fork-join_any, all processes start simultaneously and
join_any will wait for any one process to be completed
Fork_join none
• In fork-join_none, all processes start simultaneously and join_none will not wait for any
process to be completed.
• So, we can say that fork-join and fork-join_any is blocked due to process execution time,
whereas fork-join_none is not blocked due to any process.
Disable fork join
Wait fork
Randomization
 Introduction
• Random variables
• Randomization methods
• Scope randomization
• Disable randomization
• Advantages
Random variables
• Variables are declared random using the rand or randc keyword.
• randc is random-cyclic. For the variables declared with the randc
keyword, on randomization variable values don’t repeat a random
value until every possible value has been assigned.
• Example:
Randomization methods
• Pre randomization: Function is defines within the same class whose
object will be randomization before.
• Post randomization: Function is also defines within the same class
whose object will be randomization after.
Scope randomization
• The scope randomize function, std::randomize(), enables users to
randomize data in the current scope without the need to define a
class or instantiate a class object.
Disable randomization
• Randomization of variable in a class can be disable by using
rand_mode method call.
Advantages

• It has the capability of finding hidden bugs with some random

combination.
• Constraint-based randomization provides possible random values
instead of a complete random range.
• It provides flexibility to have random values based on user-defined
probability.
• SystemVerilog randomization provides flexibility to disable
randomization for a particular variable in a class as well as disable
particular constraints based on the requirement.
• It saves time and effort in verification instead of writing a test for every
possible scenario.
 Constraint Randomization
Verification
Types of Constraints
• Inside constraint
• Inline Constraint
• Soft constraint LRM 12
• Distribution constraint/weighted constraint
• Implication constraint
• Bi-directional constraint
• Unique constraint
• Foreach loop constraint
• Solve before Constraint
• Disable modes
Inside Constraint

• The inside keyword is helpful when randomized values have to be

in the provided range.

Syntax:-
Constraint <Constraint_name> {<variable> inside {….};}
Inline Constraint

• A class already has well-written constraints and there is a need to randomize

the class variable with a set of different constraints decided by the user.
• By using with construct, users can declare in-line constraints at the point
where the randomize() method is called.

Syntax:-
Class_handle.randomize( ) with {….;};
Soft constraint

• It is possible to change constraints during randomization and inline constraints

should not conflict with constraints written in the class to avoid randomization
failure.
• But sometimes there is a requirement to change constraints in such a way that it
may conflict with constraints inside the class.

Syntax:-
Constraint <Constraint_name> {soft <variable> inside {….};}
Distribution constraint/weighted constraint

• The dist keyword is helpful whenever to have weighed distribution

during randomization.
• The probability random value occurrence can be controlled using
the dist keyword

Syntax:-
constraint constraint_name {<variable> dist {[1:5]:=10 }; }
constraint constraint_name {<variable> dist {[1:5]:/10}; }
Implication constraint

• Implication operator (->) declares the relation between two variables.

• For an implication operator in constraint, it declares the relation between expression
and constraint.
• If the LHS expression of -> holds true, the RHS constraint is considered

Syntax:-
Constraint constraint_name {<expression> -> <constraint>;}
constraint scale_c { (scale == LOW) -> value <50; }
Bi-directional constraint

• SystemVerilog solves constraints parallelly for all random variables and

makes sure no constraint fails.
• While solving the constraint, the value of a variable can be impacted because
of another variable.

Syntax:-
Constraint constraint_name1 {variable_1 > value, variable_2< value;
Constraint constraint_name2 {variable_1 < variable_2;}
Unique constraint & randc

• A unique constraint is useful to generate unique values for

variables and elements in an array (Fixed array, associative array,
dynamic array, and queue).

Syntax:-
constraint <constraint name> {unique {array or variable};}
Foreach loop constraint

Same as foreach loop, array constraints can also be implemented using

foreach loop to iterate over array elements.

Syntax:-
constraint <constraint_name> { foreach(variable[i]) variable[i] <condition>}
Solve before Constraint

• Solve before is the constraint property. solve before is used inside the
constraint block to specify the order of constraint solving.
• If the variables are dependent, due to the bidirectional nature of constraints
value of one variable will influence the value of another variable.

Syntax:-
Constraint constraint_name {solve <variable> before {range};}
Disable modes

Methods of using rand_mode

Complete class randomization can be disabled

<object_handle>.rand_mode(0);

Enable the randomization

<object_handle>.rand_mode(1);

Particular variable randomization can be disabled

<object_handle>.<variable>.rand_mode(0);

To disable constraint, constraint_mode(0) is used.

Coverage
Type of coverage
There are two types of coverage supported
1.Code coverage
2.Functional coverage
 Code Coverage
Code coverage deals with covering design code metrics.
It tells how many lines of code have been exercised w.r.t. block, expression, FSM,
signal toggling.
• The code coverage is further divided as
1.Block coverage – To check how many lines of code have been covered.
2.Expression coverage – To check whether all combinations of inputs have been
driven to cover expression completely.
3.FSM coverage – To check whether all state transitions are covered.
4.Toggle coverage – To check whether all bits in variables have changed their states
Functional Coverage

• Functional coverage deals with covering design functionality or feature

metrics. It is a user-defined metric that tells about how much design
specification or functionality has been exercised.

The functional coverage can be classified into two types

1.Data intended coverage :- checks combinations of data values have
occurred. We can get Data-oriented coverage by writing Coverage groups,
coverage points and also by cross coverage
2.Control intended coverage – Checks whether sequences of behaviors have
occurred. We can get assertion coverage by writing SystemVerilog Assertions
Cont….
• Covergroup
• Coverpoint
• Cross-Coverage
• Bins
• Sampling methods
Types of Bins
• Implicit bins or automatic bins
• Explicit bins
• Illegal bins
• Ignore bins
• Cross bins
• Option. atleast bins
• Auto_bin_max bins (user-defined type)
• Wild card bins
Covergroup
• A covergroup is defined between keywords covergroup & endgroup
• A covergroup instance can be created using the new() operator

Syntax :-
Covergroup covergroup_name;
Coverpoint_name: cover point variable_name
Endgroup
Cg Cg_inst=new();
Cross coverage
• The cross-coverage allows having a cross-product between two or more variables or
coverage points within the same covergroup.
• In simple words, cross-coverage is nothing but a set of cross-products of variables or
coverage points.

Syntax:-
<cross_coverage_label> : cross <coverpoint_1>, <coverpoint_2>,..., <coverpoint_n>
Cross coverage Example
class parent;
rand bit [3:0] a,b;
bit [7:0] c;
bit wr_rd;
endclass
module crosscoverage;
parent p1=new();
covergroup cov;
option.per_instance = 1;
l1: coverpoint p1.a;
l2: coverpoint p1.b;
l1xl2: cross l1,l2; //Cross Coverage
endgroup
cov c1=new();
initial begin
repeat(500) begin
assert(p1.randomize());
c1.sample();
end
end
endmodule
Implicit /automatic bins

module eg();

bit [2:0] data; // 2^3 = 8 i.e 0 to 7

bit [1:0] addr; // 2^2 = 4 i.e 0 to 3

covergroup cg;

option.per_instance = 1;

Y : coverpoint addr;

X : coverpoint data {
option.auto_bin_max = 8;
}
endgroup: cg

initial begin: B1

cg c = new();

repeat(50) begin: B2

{data,addr} = $urandom();

c.sample();
end: B2

end: B1

initial begin: B3
#100;
$stop();
end: B3

endmodule: eg
Explicit bins
module eg();

bit [2:0] data;

bit [1:0] addr;

covergroup cg;

option.per_instance = 1;

Y : coverpoint addr;

X : coverpoint data {bins b1= {10,[13:15]}; }

endgroup: cg

initial begin: B1

cg c = new();

repeat(50) begin: B2

{data,addr} = $urandom();

c.sample();
end: B2

end: B1

initial begin: B3
#100;
$stop();
end: B3

endmodule: eg
Illegal bins:- Illegal bins are used to capture values that are not expected, such as those that should
never occur in a particular scenario.

program main;
bit [0:2] y;
bit [0:2] values[$]= '{1,6,3,7,3,4,3,5};
covergroup cg;
option.per_instance = 1;
cover_point_y : coverpoint y {
illegal_bins ib = {7};
}
endgroup
cg cg_inst = new();
initial
foreach(values[i]) begin
y = values[i];
cg_inst.sample();
end
endprogram
Ignore bins:- Ignore bins are used to exclude certain values from the coverage model, meaning the
coverage model will not track those excluded values
program main;
bit [0:2] y;
bit [0:2] values[$]= '{1,6,3,7,3,4,3,5};

covergroup cg;
cover_point_y : coverpoint y {
ignore_bins ig = {1,2,3,4,5};
}

endgroup

cg cg_inst = new();

initial
foreach(values[i])
begin
y = values[i];
cg_inst.sample();
end

endprogram
Wildcard bins:- The wildcard bins definition causes all X, Z, or ? to be treated as wildcards for 0 or 1
(similar to the ==? operator).
program main;
reg [0:3] y;
reg [0:3] values[$]= '{ 4'b1100,4'b1101,4'b1110,4'b1111};

covergroup cg;
option.per_instance = 1;
cover_point_y : coverpoint y {
wildcard bins g12_15 = { 4'b11?? } ;
}
endgroup

cg cg_inst = new();
initial
foreach(values[i])
begin
y = values[i];
cg_inst.sample();
end
endprogram
Sampling methods
They are 2 sampling methods

1. Calling sample method

• Covergroup_handle.sample();

2. Clock method
• covergroup cg @(posedge clk);
 Modports and
clocking blocks
Modports
• Within an interface to declare port directions for signals modport
is used.
• The modport also put some restrictions on interface access.

Syntax:-
Modport <name> (input <port_list>, output <port_list>) ;
Clocking block
• To specify the synchronization scheme and timing requirements for an
interface, a clocking block is used.
• The testbench can have multiple clocking blocks but only one clocking block
per clock.
• The clocking block can be declared in the program, module, or interface.
Syntax:-
clocking <clocking_name> (<clocking event>);
Default input <delay> output <delay>;
<signals>
endclocking
 SEMAPHORE
Semaphores are typically used for mutual exclusion, access control to
shared resources, and basic synchronization.

Syntax : Semaphore semaphore_name;

Semaphore methods

• new(); Create a semaphore with a specified number of keys

• get(); Obtain one or more keys from the bucket
• put(); Return one or more keys into the bucket
• try_get(); Try to obtain one or more keys without blocking

Semaphore_name.new()/get()/put()/try_get();
Semaphore Example:
MAILEBOX
A SystemVerilog mailbox is a way of communication between different
processes to exchange data. One process can put data into a mailbox
that stores data internally and can be retrieved by another process.
Mailbox behaves as first-in, first-out (FIFO).

Based on the sizes mailboxes are categorized :

•bounded mailbox: size is specified and number of entries are limited

•unbounded mailbox : Size is not specified and number of entries are unlimited
Generic mailbox
The generic mailbox can be put or get data of any data_type like int, bit, byte, string, etc. By default,
the mailbox is a typeless or generic mailbox.

Syntax:
mailbox <mailbox_name>

Parameterized mailbox
The parameterized mailbox can be put or get data of particular data_type. The parameterized mailbox is
useful when data_type needs to be fixed.For differences in data_type, a compilation error is expected.

Syntax:
mailbox #(<type>) <mailbox_name>

Example: mailbox #(int) mb;

 Mailbox Methods
SystemVerilog Mailbox is a built-in class that provides the following methods. these are applicable for both
Generic and Parameterized mailboxes

new(); - Create a mailbox

put(); - Place a message in a mailbox
try_put(); - Try to place a message in a mailbox without blocking
get(); or peek();- Retrieve a message from a mailbox
num(); - Returns the number of messages in the mailbox
try_get(); or try_peek(); - Try to retrieve a message from a mailbox without blocking

Example: https://www.edaplayground.com/x/2PQL
SV Assertions
ASSERTIONS :-
Assertions are used to check the property of a signal.
• It improves the debugging time.
• It improves error detection.

There are 2 types of Assertions. They are:

1. Immediate Assertions 2. Concurrent Assertions

IMMEDIATE ASSERTIONS:
Immediate assertions checks for a condition at the current simulation time.
• In Immediate assertions all the signals will be evaluated at a time.
Syntax : assert (expression)
These Immediate assertions we will use in Combinational Circuits.
EXAMPLE:
Sequence: Property:
sequence <sequence_name>; property <property_name>;
Boolean Expression; test expression or
endsequence sequence_name;
endproperty

Example :
sequence seq;
@(posedge clk) a ##2 b;
endsequence

property p;
seq;
endproperty

assert property(p);
sequence seq_1; property p;
@(posedge clk) a==1; seq_1;
endsequence endproperty

assert property(p);
Reason for once clock cycle delay.
Sequences with timing relationship:

Clock cycle delays are represented by a “##” sign.

For example, ##2 means 2 clock cycles.
property p;
sequence seq;
seq;
@(posedge clk) a ##2 b;
endproperty
endsequence
assert property(p);
Clock usage in SVA :
Clock defined in the sequence definition :

sequence seq;
@(@(posedge clk) <expression>;a ##2 b;
endsequence

property p;
seq;
endproperty
a_1 : assert property(p););
Clock defined in the property definition :
sequence seq;
a ##2 b;
endsequence

property p;
@(posedge clk) seq;
endproperty

a_1 : assert property(p););

Implication Operator:

• If we want the sequence to be checked only after “a” is high, this can be achieved by
using the implication operator.
• The left-hand side of the implication is called the “antecedent” and the right-hand side
is called as “consequent.”
• If the antecedent succeeds, then the consequent is evaluated.
• If antecedent fails we will call it as a vacious success.
Antecedent --> Consequent.
• The implication construct can be used only in property definitions. It cannot be used in
sequences.

• There are 2 types of implication:

1.Overlapped implication 2.Non-overlapped implication
Overlapping implication:

• The overlapping implication is denoted by the symbol |->.

• If there is a match on the antecedent, then the consequent expression is
evaluated in the same clock cycle
• Below property checks that, if signal “a” is high on a given positive clock edge,
then signal “b” should also be high on the same clock edge.
property p;
@(posedge clk) a |-> b;
endproperty
a: assert property(p);
Overlapping implication:
Non-overlapping:

• The non-overlapped implication is denoted by the symbol |=>.

• If there is a match on the antecedent, then the consequent expression is

evaluated in the next clock cycle.

• Below property checks that, if signal “a” is high on a given positive clock edge,
then signal “b” should be high on the next clock edge. And the output will be
given on the next posedge clk due to sv event Schedulers.

property p;
@(posedge clk) a |=> b;
Endproperty

a: assert property(p);
The implication with a fixed delay on the consequent:

• Below property checks that, if signal “a” is high on a given positive clock edge, then
signal “b” should be high after 2 clock cycles.

property p;
@(posedge clk) a |-> ##2 b;
endproperty
a: assert property(p);
Using two sequences to write conditions:

Below property checks that, if the sequence seq_1 is true on a given positive edge of
the clock, then start checking the seq_2 (“d” should be low, 2 clock cycles after
seq_1 is true).
sequence seq_1;
(a && b);
endsequence
sequence seq_2;
##2 !c;
endsequence

property p;
@(posedge clk) seq_1 |-> seq_2;
endpeoperty
a: assert property(p);
EXAMPLE:

Below property checks that, if signal “a” is high on a given positive clock edge, then
within 1 to 4 clock cycles, the signal “b” should be high.
property p;
@(posedge clk) a |-> ##[1:4] b;
endproperty
a: assert property(p);

EXAMPLE:

Below property checks that, if signal “a” is high on a given positive clock edge, then
signal “b” should be high in the same clock cycle or within 4 clock cycles.
property p;
@(posedge clk) a |-> ##[0:4] b;
endproperty
a: assert property(p);
Indefinite timing window:

• The upper limit of the timing window specified in the right-hand side can be defined
with a “$” sign which implies that there is no upper bound for timing.
• The checker will keep checking for a match until the end of the simulation.
• Below property checks that, if signal “a” is high on a given positive clock edge,
then signal “b” will be high eventually starting from the next clock cycle.

property p;
@(posedge clk) a |-> ##[1:$] b;
endproperty
a: assert property(p);
Repetition Operators:
property p;
@(posedge clk) a |-> ##1 b ##1 b ##1 b;
endproperty
a: assert property(p);

• The above property checks that, if the signal “a” is high on given posedge of the clock,
the signal “b” should be high for 3 consecutive clock cycles.

• The Consecutive repetition operator is used to specify that a signal or a sequence will
match continuously for the number of clocks specified.
• Syntax
signal [*n] or sequence [*n]

"n" is the number of repetitions.

• with repetition operator above sequence can be re-written as,

• property p;
• @(posedge clk) a |-> ##1 b[*3];
• endproperty
• a: assert property(p);
SVA Methods:

$rose : returns true if the signal changed from 0 to 1. Otherwise, it returns false.
Syntax : $rose(boolean expression or signal name)
sequence seq_rose;
@(posedge clk) $rose(a);
endsequence
Sequence seq_rose checks that the signal “a” transitions to a value of 1 on every
positive edge of the clock. If the transition does not occur, the assertion will fail.
$fell: returns true if the signal changes from 1 to 0. Otherwise, it returns
false.

Syntax : $fell(boolean expression or signal name)

sequence seq_fell;
@(posedge clk) $fell(a);
endsequence
Sequence seq_fell checks that the signal “a” transitions to a value of 0 on every
positive edge of the clock. If the transition does not occur, the assertion will fail.
STABLE:
Returns true if the value of the expression did not change. Otherwise, it
returns false.
Syntax : $stable(boolean expression or signal name)
sequence seq_stable;
@(posedge clk) $stable(a);
endsequence
Sequence seq_stable checks that the signal “a” is stable on every positive edge of
the clock.
If there is any transition occurs, the assertion will fail.
PAST:
provides the value of the signal from the previous clock cycle.
Syntax : $past(signal_name, number of clock cycles)
• Below Property checks that, in the given positive clock edge, if the “b” is high, then
2 cycles before that, a was high.
property p;
@(posedge clk) b |-> ($past(a,2) == 1);
endproperty
a: assert property(p);
• $onehot(expression)
checks that only one bit of the expression can be high on any given clock edge.
• $isunknown(expression)
checks if any bit of the expression is X or Z. If any x or z it will return 1 else 0.
• $countones(expression)
counts the number of bits that are high in a vector.
SV Loops
• - if-else Statement
- case Statement
- repeat loop
- for loop
- while loop
- do-while
- foreach
- Loop Control
If statement:
• EXAMPLE : if
• program main ;
• integer i;
• initial begin
• i = 20;
• if( i == 20)
• $display(" I is equal to %d ",i);
• else
• $display(" I is not equal to %d ",i);
• end
• Endprogram

• RESULTS

• I is equal to 20
Case and repeat:
• EXAMPLE : case and repeat
• program main ;
• integer i;
• initial begin
• repeat(10)begin
• i = $random();
• case(1) begin
• (i<0) :$display(" i is less than zero i==%d\n",i);
• (i>0) :$display(" i is grater than zero i=%d\n",i);
• (i == 0):$display(" i is equal to zero i=%d\n",i);
• end
• end
• end
• endprogram
• RESULTS

• i is grater than zero i=69120

• i is grater than zero i=475628600
• i is grater than zero i=1129920902
• i is grater than zero i=773000284
• i is grater than zero i=1730349006
• i is grater than zero i=1674352583
• i is grater than zero i=1662201030
• i is grater than zero i=2044158707
• i is grater than zero i=1641506755
• i is grater than zero i=797919327
For-loop
• EXAMPLE : forloop
• program for_loop;
• integer count, i;
• initial begin
• for(count = 0, i=0; i*count<50; i++, count++)
• $display("Value i = %0d\n", i);
• end
• endprogram
• RESULTS

• Value i = 0
• Value i = 1
• Value i = 2
• Value i = 3
• Value i = 4
• Value i = 5
• Value i = 6
• Value i = 7
While-loop
• EXAMPLE : whileloop
• program while_loop;
• integer operator=0;
• initial begin
• while (operator<5)begin
• operator += 1;
• $display("Operator is %0d\n", operator);
• end
• end
• endprogram
• RESULTS

• Operator is 1
• Operator is 2
• Operator is 3
• Operator is 4
• Operator is 5
Do-while
• EXAMPLE : dowhile
• program test;
• integer i = 0;
• initial begin
• do
• begin
• $display("i = %0d \n", i);
• i++;
• end
• while (i < 10);
• end
• endprogram
• RESULTS

• i=0
• i=1
• i=2
• i=3
• i=4
• i=5
• i=6
• i=7
• i=8
• i=9
For-each
• The foreach construct specifies iteration over the elements of an array. Its argument is an identifier that
designates any type of array (fixed-size, dynamic, or associative) followed by a list of loop variables enclosed in
square brackets. Each loop variable corresponds to one of the dimensions of the array. The foreach construct is
similar to a repeat loop that uses the array bounds to specify the repeat count instead of an expression.

• The mapping of loop variables to array indexes is determined by the dimension cardinality, as described in
multidimentional topic.
• The foreach arranges for higher cardinality indexes to change more rapidly.

• // 1 2 3 3 4 1 2 -> Dimension numbers

• int A [2][3][4]; bit [3:0][2:1] B [5:1][4];
• foreach( A [ i, j, k ] ) ...
• foreach( B [ q, r, , s ] ) ...
• he first foreach causes i to iterate from 0 to 1, j from 0 to 2, and k from 0 to 3. The second foreach
causes q to iterate from 5 to 1, r from 0 to 3, and s from 2 to 1 (iteration over the third index is skipped).

• EXAMPLE : foeach
• program example;
• string names[$]={"Hello", "SV"};
• int fxd_arr[2][3] = '{'{1,2,3},'{4,5,6}};
• initial begin
• foreach (names[i])
• $display("Value at index %0d is %0s\n", i, names[i]);
• foreach(fxd_arr[,j])
• $display(fxd_arr[1][j]);
• end
• endprogram
• RESULTS

• Value at index 0 is Hello

• Value at index 1 is SV

•4
•5
•6