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Digital VLSI
ECC503

Subject Incharge
Snehal Lopes
Assistant Professor
Room No. 628
email:
[email protected]
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Lopes
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Module I

Lecture 1

Introduction to Digital VLSI

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Course Objective: To teach students

1. To introduce process flow of VLSI Design.
2. To understand MOSFET operation from VLSI design perspective.
3. To learn VLSI design performance metric and various tradeoffs.
4. To design, implement and verify combinational and sequential logic circuits
using various MOS design styles.
5. To provides an exposure to RTL design and programming

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Course Outcomes: Course should enable the students to:

1. Know various tools and processes used in VLSI Design.

2. Explain working of various CMOS combinational and sequential circuits

used in VLSI Design.
3. Derive expressions for performance parameters of basic building
blocks like CMOS inverter.
4. Relate performance parameters with design parameters of VLSI circuits.
5. Select suitable circuit and design style for given application.
6. Design and realize various combinational and sequential circuits for given
specification.

St. Francis Institute of technology DVLSI Design 6

Department of Electronics & Telecommunication Ms. Snehal
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Introduction of Subject

Module 1: Review of MOSFET operation and Fabrication : (8h)

Topics:

1. Overview of VLSI Design Flow, Review of MOSFET operation, MOSFET

Capacitances, MOSFET scaling, Short channel effects

(03)

2. Fabrication process flow of NMOS and CMOS, Lambda based design rules
(03)

3. Novel MOSFET Architectures FinFET, GAA-FET, CNTFET

(02)
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Introduction of Subject

Module 2: Combinational CMOS Logic Circuits (6h)

Topics:

2.1 CMOS inverter operation, Voltage Transfer characteristics (VTC), Noise

Margins, Propagation Delay, Power Dissipation, Design of CMOS

(03)
Inverter, Layout of CMOS Inverter

2.2 Realization of CMOS NAND gate, NOR gate, Complex CMOS Logic
(03)
Circuits, Layout of CMOS NAND, NOR and complex CMOS circuits

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Introduction of Subject

Module 3: MOS Design Logic Styles (9h)

Topics:

1. Static CMOS, Pass Transistor Logic, Transmission Gate, Pseudo NMOS,

Dynamic Logic, Domino Logic, NORA, Zipper, C2MOS

(04)

2. Setup time, Hold time, clocked CMOS SR Latch, CMOS JK Latch, MS–JK

Flip Flop, Edge triggered D-Flip Flop and realization using design styles

(03)
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3. Realization of Shift Register, MUX, Decoder using above design styles ,1-bit Lopes
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Introduction of Subject

Module 4: Semiconductor Memories (6 h)

Topics:

4.1 ROM array, 6T-SRAM (operation, design strategy, leakage

currents, sense amplifier),layout of SRAM (03)

4.2 Operation of 1T and 3T DRAM Cell, NAND and NOR (03)

flash memory

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Introduction of Subject

Module 5: Data path and system design issues ( 6 h)

Topics:

1. Ripple carry adder, CLA adder, carry save adder, carry select

adder, carry skip adder, Array Multiplier

(04)

2. On chip clock generation and distribution, Interconnect delay

model, interconnect scaling and crosstalk

(02)
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Introduction of Subject

Module 6: RTL Design (4

h)

Topics:

6.1 High Level state machines, RTL design process (02)

6.2 RTL design of Soda dispenser machine, FIR

(02)
Filter

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Recommended Books:

Textbooks:

1. Sung-Mo Kang and Yusuf Leblebici, “CMOS Digital Integrated Circuits

Analysis and Design”, Tata McGraw Hill, 3rd Edition, 2012.

2. Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic,

“Digital Integrated Circuits: A Design Perspective”, Pearson Education,

2nd Edition.

3. Frank Vahid, “Digital Design with RTL design, VHDL and VERILOG”,

John Wiley and Sons Publisher 2011.

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Reference Books:
1. Neil H. E. Weste, David Harris and Ayan Banerjee, ―CMOS VLSI

Design: A Circuits and Systems Perspectiveǁ, Pearson Education, 3rd

Edition.

2. John P. Uyemura, “Introduction to VLSI Circuits and Systems”, Wiley,

Student Edition, 2013.

3. R. Jacob Baker, “CMOS Circuit Design, Layout and

Simulation”, Wiley, 2nd Edition, 2013

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What is VLSI Design

• “Very Large Scale Integration”, it is used to create IC

(Integrated Circuits) by combining millions
of metal oxide silicon (MOS) transistors to form a single chip.

• VLSI came into existence in the 1970s.

• VLSI design has been widely used in various devices such

as memory cards, cell phones, and set-top boxes.

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IC Fabrication in India

• IC fabrication in India is only done by ISRO Laboratory(semi-conductor

laboratory, mohali) previously known as semiconductor complex limited.

• works in 180 nm CMOS technology for manufacturing analog, digital devices.

• Dedicated bays for Wafer Fabrication Processes viz. Diffusion, Lithography,

Etching (Dry & Wet) are there.

• The wafer size used by SCL is 8″

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IC fabrication Labs In India

• Government has planned to setup fabrication labs in India.
One ongoing project is at Gujarat/ Maharashtra, which is setup by NRIs,
the name of the company is HSMC( Hindustan semiconductor
manufacturing company).

• Mini fab labs are present at IIT Bombay and IISc Bengaluru. Those are

under the centre for microelectronics.

• But as far as commercial factors are concerned SCL, Mohali is the only

one.

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Will IC fabrication start in India in the near future?

• Business of IC fabrication means bigger investments in the range of billions

without any return for initial few years. And few years may be 6–7 at least,
and no industrialists have guts to take that much risk.
• Space to set up a big plant - seeing the current govt. stance we can get the
land inside SEZ to construct such plant easily in comparison to old times.
• Starting a fabrication plant means we need tooling experts, production

managers and quite other specialists too.

• We need uninterrupted supply of electricity, and a lot of water is required

for the process.

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Will IC fabrication start in India in the near future?

• Even after your plant is ready, you need a constant R&D for chips to work

properly and developing new possible technology nodes.

• And even after everything is perfect till here. We need to sell those home

made chips to related customers, now here people will rely on someone who
is into this business for 40 years rather than a new comer, hence business
will take a lot of time to establish.
• Semiconductor fabrication plants can be opened here, if some foreign

company is ready to invest. Because our private firms expect quick money
rather than doing bigger investment for long time.

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on March 13, Prime Minister Narendra Modi virtually
initiated ground-breaking ceremonies for three
semiconductor projects worth about Rs 1.25 lakh crore.
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The roadmap for a successful VLSI designer.

The
hierarchy
shown
below,
taken
from Digital
Integrated
Circuits by
Jan Rabaey

St. Francis Institute of Tec hnology

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VLSI Design 28
Department of & Telecommunication Ms. 0
Ms.SSnehal
nehal
Electronics LopesLopes
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Module 1

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Why to Design VLSI

Circuit?

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HISTORICAL OVERVIEW: ERA of ICs

• 1954, 1st Silicon Transistor, cost $2.50.

• 1961, 1st IC( FF circuit), cost $50.

• 1961-1966 : SSI era, 90-150 Tr/C, FF, Gates.

• 1967-1971 : MSI, 100-1000 Tr/C, Adders, counters and 1K RAM chip by

Intel.

• 1972-1978 :LSI, 1K-20K Tr/C, 4-8bit µps, ROM.

• 1978-1988 : VLSI, 20K-500K Tr/C, 16-32bit µps, sophisticated peripherals.

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• In 1965, Gordon Moore

noted that the number
of
transistors on a
doubled every
chip 18 to 24
months.
• He made a prediction
semiconductor
that technology Gordon Moore
Intel Co-Founder and Chairmain
will double its effectiveness Emeritus

every 18 months

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Why MOSFET’s?

• CMOS circuits dissipate power only when switching (they do

use power when not switching, but it is much less than
other circuits).

• This allows for more circuits to be placed on one die.

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Why CMOS dominates the semiconductor /IC industry ?

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Why CMOS dominates the semiconductor /IC industry ?

• Silicon is cheaper preferred over other materials

• physics of CMOS is easier to understand
• CMOS is easier to implement/fabricate
• CMOS provides lower power-delay product
• CMOS is lowest power dissipation
• density: can get more CMOS transistors/functions in same chip area
• BUT! CMOS is not the fastest technology!

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Symbols of MOSFET
54

DVLSI Design Ms. Snehal Lopes 12/02/2024

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Structure and Operation of MOS Transistor (MOSFET)

The distance between the drain and

source diffusion regions is the
channel length L, and the lateral
extent of the channel (perpendicular
to the length dimension) is the
channel width W. The thickness of
the oxide layer covering the channel
region, tox, is also an important
parameter.

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 Operation Principle of E-MOSFET

• The current conduction between the source and the drain,

can be controlled using the electric field generated by the
gate voltage as a control variable.
• The current flow in the channel is also controlled by the
drain-to-source voltage and by the substrate voltage, the
current can be considered a function of these external
terminal voltages.

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Two terminal MOS structure

• The thickness of the silicon dioxide layer is usually between 10nm and 50
nm.
• The MOS structure forms a capacitor

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For a p-type semiconductor, the Fermi potential can be

approximated by

whereas for an n-type semiconductor (doped with a

donor concentration ND), the Fermi potential is given by

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 QuizTime

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What are the three terminals of a MOSFET
called?

a) Emitter, Base, Collector

b) Anode, Cathode, Gate
c) Source, Drain, Gate (Correct)
d) Positive, Negative, Neutral

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The MOS System under External Bias

The hole density near the surface increases as a result of the negative
gate bias, the electron (minority carrier) concentration decreases as the
negatively charged electrons are pushed deeper into the substrate.

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• The thickness xd of this depletion region on the surface is a

function of the surface potential ᶲs.
• the mobile hole charge in a thin horizontal layer parallel to the
surface is

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 Threshold voltage (VT0): It is defined as the
voltage at which an MOS device begins to
conduct (“turn on”) 7
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Threshold Voltage for MOSFET Transistor

threshold voltage based on four physical components

1)the work function difference between the gate and the channel ΦGC,
it reflects the built-in potential of the MOS system,

2)the gate voltage component to change the surface potential,

surface potential is - 2ϕF

3) the gate voltage component to offset the depletion region

charge, Depletion region charge density

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The threshold voltage, same expression can be used both for

n- channel and p-channel MOS transistors.

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MOSFET Operation: A Qualitative View

VGS = 0V VGS << VT0

ID = 0 ID = 0
□ The source and drain
have free electrons
□ The body has free
so almost zero current flows
holes but no free
electrons
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□ The junction
Ms. Snehal
between the body Lopes
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• When VGS > VT0. At VDS = 0, thermal equilibrium exists in the inverted channel region,

and the drain current ID is equal to zero

• If a small drain to source voltage VDS < (VGS - VT0) is applied, a drain current proportional to
VDS will flow from the drain to source to through the conducting channel.
• This operation mode is called the linear region or non-saturated, or
unsaturated region
• This channel region acts as a voltage-controlled resistor. The electron velocity in the channel
is much lower.
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• As VDS = (VGS - VT0) becomes sufficiently large then VGD ≤ VT0, the channel is no longer
inverted near the drain (inversion charge at the drain is reduced to zero) and becomes
pinched off.
• However, conduction is still brought about by the drift of electrons under the influence of the
positive drain voltage.
• As electrons reach the end of the channel, they are injected into the depletion region near the
drain and accelerated toward the drain.

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• This operation mode of the

MOSFET is called the
saturation region;

•As VDS > (VGS - VT0) a depleted surface region forms adjacent to the drain, and
this depletion region grows toward the source with increasing drain voltages.

• the pinched-off section absorbs most of the excess voltage drop (VDS - VDSAT) and a high-
field region forms between the channel-end and the drain boundary, so electrons are
injected into the depletion region and then flows to drain.

• the effective channel length is reduced as the inversion layer near the drain vanishes, while
the channel-end voltage remains essentially constant and equal to VDSAT= (VGS - VT0)

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Channel Length Modulation

The inversion layer charge at the source end is

The inversion layer charge at the drain end is

At the edge of saturation V = (V - V ) =V

DS GS T0
DSAT
If the drain-to-source voltage VDS is increased even further beyond the
saturation edge, the channel becomes pinched off.
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Short channel effects

• Short-channel effects occur when the effective channel length is approximately equal to the
depletion region thicknesses of the source and drain junctions.
• Channel length is reduced to increase both the operation speed and the number
of components per chip, it appear some unwanted effects are called short- channel effects.

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Short channel effects

The short-channel effects are attributed to two physical phenomena:

□ the limitation imposed on electron drift characteristics in the channel,
□ the modification of the threshold voltage due to the shortening channel
length.

In particular five different short-channel effects can be distinguished:

1. Drain-induced barrier lowering and punch through
2. Surface scattering
3. Velocity saturation
4. Impact ionization
5. Hot electrons
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1. Drain-induced barrier lowering and punch through

• In short channel MOSFETs, the potential barrier is by both
controlled the

gate-to-source voltage VGS and the drain-to-source voltage VDS.

• If the drain voltage is increased, the potential barrier in the channel decreases,

leading to drain-induced barrier lowering (DIBL).

• Under DIBL condition electrons can flow between the source and drain even if VGS

< VT. The channel current that flows in this case is called subthreshold current

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1. Drain-induced barrier lowering and punch through

• When the depletion regions surrounding the drain extends to the source, so that the two

depletion layer merge (i.e., when xdS + xdD = L), punch through occurs.

• Punch through can be minimized with thinner oxides, larger substrate doping,

shallower junctions, and with longer channels.

• In general current flow in the channel depends on creating and sustaining an inversion

layer on the surface.

• If the gate bias voltage is not sufficient to invert the surface (VGS<VT0), the

electrons in the channel face a potential barrier that blocks the flow.

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2. Surface scattering
• For small-geometry MOSFETs, the electrons mobility in the channel depends on a
two-dimensional electric field (Ex, Ey).
• As the channel becomes smaller the electric field component Ey increases.

• The surface scattering occurs when electrons are accelerated toward the surface by
the vertical component of the electric field Ex. This collision of the electrons causes
a reduction in the mobility.
• The average surface mobility is about half as much as that of the bulk mobility.

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3. Velocity saturation
• As channel is reduced, the electric field increases (if voltage is constant)

• At low Ey, the electron drift velocity Vde in the channel varies linearly with the
electric field intensity.
• However, as Ey increases the drift velocity tends to increase more slowly, and
approaches a saturation value.
• The drain current is limited by velocity saturation instead of pinch off. This occurs in
short channel devices when the dimensions are scaled without lowering the bias
voltages.
• The velocity saturation reduces the transconductance of short-channel devices in
the saturation condition

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4. Impact ionization
• Due to the high velocity of electrons in presence of high longitudinal fields, there
may ionizing of silicon atoms by impacting electron-hole pairs.

• Normally most of the electrons are attracted by the drain, so it is possible a higher
concentration of holes near the source.

• If the holes concentration on the source is able to creates a voltage drop on the source-
substrate n-p junction of about 0.6V then

❖ electrons may be injected from source to substrate

❖ electrons travel toward the drain, increasing their energy and

create new electrons-holes pairs

❖ electrons may escape the drain fields and affecting other devices on a chip

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5. Hot electrons
• Due to high electric fields, this high energy electrons can enter the oxide and
reduces the total current flow from drain to source.
• It increases the oxide charging that can be accumulate with time and degrade the device
performance by decreasing VT
• Electrons arriving at the Si-SiO2 interface with enough kinetic energy to cross the
surface potential barrier and be injected into the oxide.

• In small-geometry transistor, the depletion charge near n+ regions is induced by p-n

junctions, so, the bulk depletion region which is induced by the gate voltage is smaller than
expected.

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Narrow Channel effects

• MOS having channel widths approximately equals to depletion region

thickness is known as narrow channel effect .
• Overlapping of gate electrode and field oxide, shallow depletion region
forms underneath this overlap area as well.
• Gate voltage must also support this additional depletion charge in order to establish
the conducting channel.

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MOSFET Capacitances

• The on-chip capacitances found in MOS circuits are in general complicated functions
of the layout geometries.
• Most of these capacitances are not lumped, but distributed,
symmetry of the MOSFET
structure.

channel length is

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parasitic capacitances associated with this typical MOSFET structure

as lumped equivalent capacitances

parasitic device capacitances can be classified into two major

groups: oxide-related capacitances and junction
capacitances

Oxide-related Capacitances
1. Overlap capacitance

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these overlap capacitances do not depend on the bias conditions (voltage )

2. Gate –Channel capacitance

• the gate-to-channel capacitance is distributed capacitances and voltage-dependent.
• the gate-to-source capacitance Cgs is actually the gate-to-channel capacitance
seen between the gate and the source terminals;
• the gate-to-drain capacitance Cgd is actually the gate-to-channel capacitance seen
between the gate and the drain terminals.

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The variation of the distributed parasitic oxide capacitances as functions of the gate-
to-source voltage VGS is

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Junction Capacitances

• voltage-dependent source:-substrate and drain-substrate

junction capacitances, Csb and Cdb , respectively.
• these capacitances are due to the depletion charge (reverse bias) surrounding
the respective source or drain diffusion regions.
• this capacitances are non-linear and decreases as reverse-bias is increased.
• The calculation of this associated junction capacitances is complicated

the n+ diffusion region forms a number of

planar pn-junctions with the surrounding p-
type substrate,

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Complementary CMOS (static CMOS)

• Complementary: have complementary pullup (p-type) and pulldown (n-
type) networks.
• Static: do not rely on stored charge.
• Simple, effective, reliable; hence very popular.

pMOS
pull-up
MOSFET as a Switch, passing the data
network
between the diffusions when it’s on, and
inputs
output blocking the data when it’s off:
• An nMOS is on when it’s gate is high:
nMOS
pull-down • A pMOS is on when it’s gate is low:
network

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Pull up network

PMOS passes a strong 1 but a weak 0

CMOS inverter

Pull down network

NMOS passes a strong 0 but a weak 1

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 14
2

Fabrication Process Flow

DVLSI Design Ms. Snehal Lopes 12/02/2024

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 Processing is carried out on a thin wafer cut
from a single crystal of silicon of high purity
into which the required p-impurities are
introduced as the crystal is grown. Such wafers
are typically 75 to 150 mm in diameter and 0.4
mm thick and are doped with, say, boron to
impurity concentrations of 1015/cm3 to
1016/cm3 , giving resistivity in the approximate
range 25 ohm cm to 2 ohm cm.

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Fabrication Process Flow: Basic Steps

• The process used to transfer a pattern to a layer(silicon, polysilicon, silicon dioxide, metal
etc.) on the chip is called lithography. Since each layer has its own distinct patterning
requirements, the lithographic sequence must be repeated for every layer, using a different
mask.
• fabrication steps involved in patterning silicon dioxide through optical lithography,

a) Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity
into which the required p-impurities (Boron) are introduced.

b) A SiO2 (silicon dioxide) layer typically 1 micrometer thick, is grown all above the surface of the
wafer to protect the surface, act as a barrier to the dopant through processing, and provide a
generally insulating substrate on to which other layers may be deposited and patterned.

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c) The entire oxide surface is then covered with a layer of photoresist, which is
essentially a light-sensitive and spun to an even distribution of the necessary
thickness, initially insoluble in the developing solution

d) The photoresist material is then exposed to ultraviolet (UV) light through a mask
which defines those regions into which complete nMOS transistor is to take
place. the exposed areas become soluble so that they are no longer resistant
to etching solvents. To selectively expose the photoresist, we have to cover
some of the areas on the surface with a mask during exposure.

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• positive photoresist: it is initially insoluble and becomes soluble after exposure

to UV light.
• Negative photoresist: it is initially soluble and becomes insoluble (hardened)
after exposure to UV light.
• Negative photoresists are more sensitive to light, but their photolithographic
resolution is not as high as that of the positive photoresists. Therefore, negative
photoresists are rarely used in the manufacturing of high-density integrated
circuits.

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e) The unexposed portions of the photoresist can be removed by a solvent. The silicon dioxide
regions which are not covered by hardened photoresist can be etched away either by using a
chemical solvent (HF acid) or by using a dry etch (plasma etch) process.

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f) The remaining photoresist can now be stripped from the silicon dioxide surface by using
another solvent.

Steps a to f are required to transfer single pattern onto the silicon dioxide surface.
The fabrication of semiconductor devices requires several such pattern

Fabrication process of the nMOS transistor

Mask-1: The field oxide (thick silicon dioxide)is selectively etched to expose the silicon
surface on which the MOS transistor (source, drain, channel) will be created.

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Mask-2: The surface is covered with a thin, high-quality oxide layer, which will eventually form the
gate oxide of the MOS transistor. On top of the thin oxide layer, a layer of polysilicon is deposited by
using CVD technique. Un-doped polysilicon has relatively high resistivity. The-resistivity of polysilicon
can be reduced, however, by doping it with impurity atoms.
• the polysilicon layer is patterned and etched to the MOS transistor gate.
• The thin gate oxide not covered by polysilicon is also etched away,

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• The entire silicon surface is then doped with a high concentration of impurities, either through
diffusion or ion implantation process. Diffusion is achieved by heating the wafer to a high
temperature and passing a gas containing the n-type impurity over the surface.
• The doping penetrates the exposed areas on the silicon surface, ultimately creating two n-type
regions (source and drain junctions) in the p-type substrate.
• The impurity doping also penetrates the polysilicon on the surface, reducing
its resistivity.
• Polysilicon with underlying thin oxide and thick oxide act as a mask during diffusion
process is called self –aligning.

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Mask-3: The entire surface is again covered with an insulating layer of silicon
dioxide. The insulating oxide layer is then patterned in order to provide
contact windows for the drain and source junctions.

Mask-4: Aluminum metal layer is deposited over its surface to a thickness typically of 1μm
which will form the interconnects. Finally, the metal layer is patterned and etched, completing
the interconnection of the MOS transistors on the surface.
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Fabrication process of CMOS

Fabrication of CMOS in IC can be done by using three different methods
1. N-well process
2. P-well process
3. Twin tub process

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N-Well CMOS Process

In N-well process an n-type well is diffused on a p-type substrate to fabricate pMOS
transistor.
Mask 1: N-well Diffusion

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Mask 2: Define Active Regions

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Mask 3: Polysilicon Gate

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Mask 4: n+ Diffusion

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Mask 5: p+ Diffusion

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Mask 6: Contact Holes

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Mask 7: Metalization

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Cross section of a CMOS Inverter

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 CMOS Fabrication Steps

The CMOS fabrication process flow is conducted using twenty basic fabrication steps
while manufactured using N- well/P-well technology.

Making of CMOS using N well

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Latch up problem

• T1 and T2 form a thyristor circuit.

• If Rw and/or Rs are not 0, and for some reason (power-up, current spike etc), T1 or T2 are
forced to conduct, Vdd will be shorted to Gnd through the small resistances and the
transistors.
• Once the circuit is 'fired', both transistors will remain conducting due to the voltage drop
across Rw and Rs. The only way to get out of this mode is to turn the power off.
• This condition is known as latch-up.
• To avoid latch-up, substrate-taps (tied to Gnd) and well-taps (tied to Vdd) are inserted as frequently
as possible. This has the effect of shorting out Rw and Rs.

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 What is latchup in CMOS?

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• Latchup refers to short circuit/low impedance path formed between
power and ground rails in an IC leading to high current and damage to the
IC.
• It occurs due to interaction between parasitic pnp and npn transistors.
• The structure formed by these resembles a Silicon Controlled rectifier
(SCR).
• These form a positive feedback loop, by short circuiting the power rail
and ground rail, which eventually causes excessive current, and can even
permanently damage the device.

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Latchup formation:

• Figure above is a CMOS transistor consisting of an NMOS and a PMOS device.

• Q1 and Q2 are parasitic transistor elements residing inside it.
• Q1 is double emitter pnp transistor whose base is formed by n well substrate
of PMOS, two emitters are formed by source and drain terminal of PMOS and
collector is formed by substrate(p type) of NMOS.
• The reverse is true for Q2.
• The two parasitic transistors form a positive feedback loop and is equivalent to
an SCR (as stated earlier).

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Analysis of latchup formation:
• Unless SCR is triggered by an external disturbance, the collector
current of both transistors consists of reverse leakage current.
• But if collector current of one of BJT is temporarily increased by
disturbance, resulting positive feedback loop causes current
perturbation to be multiplied by β1β2 as explained below.
• The disturbance may be a spike of input voltage on an input or
output pin, leading to junction breakdown, or ionizing
radiations.

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• Because collector current of one transistor Q1 is fed as input
base current to another transistor Q2, collector current of
Q2, Ic2 = β2 * Ib2 and this collector current Ic2 is fed as input
base current Ib1 to another transistor Q1.
• In this way both transistors feedback each other and the
collector current of each goes on multiplying.
• Net gain of SCR device = β1 *β2
• Total current in one loop = current perturbation * Gain

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 • If, β1 *β2 >=1, both transistors will conduct a high
saturation current even after the triggering perturbation is
no longer available.
• This current will eventually becomes so large that it may
damage the device.

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 Latch-up prevention techniques:

1) Putting a high resistance in the path so as to limit the current

through supply and make β1 *β2 < 1.
2) Surrounding PMOS and NMOS transistors with an insulating
oxide layer (trench). This breaks parasitic SCR structure.
3) Latchup Protection Technology circuitry which shuts off the
device when latchup is detected.

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Twin-Tub CMOS Process

□ This process provides the separate optimization of the nMOS and pMOS transistors.
□ Optimization of threshold voltage, body effect and the channel transconductance of both types of
transistors can be tuned independently.
□ Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top.
□ This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed.
□ Since two independent doping steps are performed for the creation of the well regions, the
dopant concentrations can be carefully optimized to produce the desired device characteristics.

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□ In the conventional p & n-well CMOS process, the doping density of the well region is
typically higher than the substrate, results in unbalanced drain parasitics. The twin-tub process
avoids this problem.
□ Balanced performance nMOS and pMOS can be obtained.

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Layout Design Rules

□ The physical mask layout of any circuit to be manufactured using a particular

process must conform to a set of geometric constraints or rules, which are
generally called layout design rules.
□ Design Rules are constraints poses by processing line in the form of
minimum allowable width, minimum allowable separation, extension
and overlap.
□ If a layer width is made too small then it is possible for the line to break
during the fabrication process or afterwards, resulting in an open circuit.
□ If two lines are placed too close to each other in the layout, they may
form an unwanted short circuit by merging during or after the
fabrication process.
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Lambda based design rules

A. N-well

A1 Minimum size = 10 λ
A2 Minimum spacing = 6 λ (Same potential)
A3 Minimum spacing = 8 λ (Different potentials)

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B. Active (Diffusion)

B1 Minimum size = 3λ
B2 Minimum spacing = 3 λ
B3 N-well overlap of p+ = 5 λ
B4 N-well overlap of n+ = 3
λ B5 N-well space to n+ = 5
λ B6 N-well space to p+ = 3
λ

C. Polysilicon

C1 Minimum size = 2 λ
C2 Minimum spacing = 2 λ
C3 Spacing to Active = 1 λ
C4 Gate extension = 2 λ

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E. Contact rules

E1 Minimum size = 2 λ
E2 Minimum spacing (Poly) = 2 λ
E3 Minimum spacing (Active) = 2 λ
E4 Minimum overlap Active) = 2 λ
E5 Minimum overlap of Poly = 1 λ
E6 Minimum overlap of Metal = 1 λ
E7 Minimum spacing to Gate = 2 λ

F. Metal-1 rules
F1 Minimum size = 3 λ
F2 Minimum spacing = 3 λ

G. Via rules
G1 Minimum size = 3 λ
G2 Minimum spacing =3 λ
G3 Minimum Metal-1 overlap = 1 λ
G4 Minimum Metal-2 overlap = 1
λ

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H. Metal-2 rules

H1 Minimum size = 3 λ
H2 Minimum spacing = 4 λ

Layout of pMOS

Layout of nMOS

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Design Rules

N- Well

1.1 Minimum width 10λ

1.2 Between wells 6λ

1.1 1.2

N-
Well

196
R2.1 Minimum N+ and P+ diffusion width 3λ

r 2.1 P+ Diff

N-
Well

r 2.1 N+
Diff
197
R2.2 Between two P+ and N+ diffusions 3λ

r 2.2
P+ Diff

N-
Well

r 2.2
N+
Diff
198
R2.3 Extra N-well after P+ diffusion 5λ

r 2.3
P+ Diff

r 2.3

N-
Well

N+
Diff
199
R2.3 Between N+ diffusion and n-well 5λ

P+ Diff

N-
Well

r 2.3

N+
Diff
200
R3.1 Polysilicon Width 2λ

Polysilico
n
r 3.1

P+ Diff

N-
Well
Polysilico
n
r 3.1

N+
Diff
201
R3.2 Between two Polysilicon boxes 3λ

Polysilico
n

r 3.2
P+ Diff

N-
Well
Polysilico
n

r 3.2
N+
Diff
202
R3.3 Extra Polysilicon surrounding Diffusion 3λ

Polysilico
n
r 3.3

P+ Diff
r 3.3

N-
Well
Polysilico
n
r 3.3

N+
Diff
203 r 3.3
R3.4 Diffusion after Polysilicon 3λ

Polysilico
n

r 3.4 r 3.4

P+ Diff

N-
Well
Polysilico
n

r 3.4 r 3.4

N+
Diff
204
R5.1 Contact width 2λ

Contact
r 5.1

Polysilicon
Contact

Metal/Polysilicon
Contact

205
 The material in this presentation belongs to St. Francis Institute of Technology and is solely for educational purposes. Distribution and modifications of the content is prohibited.

Layout of CMOS Inverter

12/02/2024 DVLSI Design 15

Ms. Snehal 2
Lopes
 The material in this presentation belongs to St. Francis Institute of Technology and is solely for educational purposes. Distribution and modifications of the content is prohibited.

VDD

Vin Vout

GND

12/02/2024 DVLSI Design 15

Ms. Snehal 3
Lopes
 The material in this presentation belongs to St. Francis Institute of Technology and is solely for educational purposes. Distribution and modifications of the content is prohibited.

12/02/2024
1/26/2021 DVLSI Design 152
Ms. Snehal 40
9
Lopes