Digital 2nd Half Portion
Digital 2nd Half Portion
Making CLR=1 and PR=0 results in Q=0 and Q’=1- Thus clearing Flip flop.
Making CLR=0and PR=1 results in Q=1 and Q’=0- Thus Presetting Flip flop.
These are asynchronous inputs and does not need a clock pulse.
JK Flip flop
JK Flip flop
D Flip flop
D Flip flop
T Flip flop
T Flip flop
D Flip flop & T Flip flop Symbols
JK Master Slave Flip flop
JK Master Slave Flip flop
JK Master Slave Flip flop Truth Table
J K Q S R Qnext
0 0 0 0 0 No Change
0 0 1 0 0 No Change
0 1 0 0 0 0 ( Reset)
0 1 1 0 1 0 (Reset)
1 0 0 1 0 1 (Set)
1 0 1 0 1 1 (Set)
1 1 0 1 0 1 (Set)
1 1 1 0 1 0 (Reset)
Shift Register
• A register that is designed to allow the bits of
its contents to be moved to left or right.
Serial In Parallel out Register
Binary Counter
• Counter is a sequential circuit that counts
number of input pulses.
• If it counts in terms of binary then its called
BINARY COUNTER
• The counter output of n bit binary counter has
2n states and it can count from 0 to (2n -1)
• The number of states of counter is referred to
as its modulus. For n bit counter m< 2n
• Depend upon manner in which Flip flop are
triggered to count we divide in to 2 types,
– Asynchronous counter
– Synchronous counter
• Asynchronous Counter
– Flip flops are clocked sequentially
• Synchronous Counter
– Flip flops are clocked Simultaneously