FET and SCR

Silicon Controlled Rectifier (SCR)

• SCR is 4 layer,3 terminal, 3 junction device which
along with its associated ckt has very wide range of
applications such as
– Rectifiers
– Regulated power supplies
– DC to AC Conversions
– Relay control
– Time delay ckts and many more
– SCR can control the power as high as 10MW and
frequency extended upto 50Khz.
 Basic Operation & Symbols of SCR
• Silicon is used in construction of SCR to handle high
temperature requirements
• Has 4 layers arranged in PNPN as shown in fig,

• Symbolic representation is as shown,

 Basic Operation contd..
• 3 terminals are Anode, Cathode and Gate

• The end P-region is the anode, the end N-region is the cathode
and the inner P-region is the gate.
• The anode to cathode is connected in series with the load
circuit. Essentially the device is a switch.
• Ideally it remains off (voltage blocking state), or appears to
have an infinite impedance until both the anode and gate
terminals have suitable positive voltages with respect to the
cathode terminal.
• The thyristor then switches on and current flows and continues
to conduct without further gate signals.
 Basic Operation contd..
• Ideally the thyristor has zero impedance in conduction state.
• For switching off or reverting to the blocking state, there
must be no gate signal and the anode current must be
reduced to zero. Current can flow only in one direction.
• However because of Regenerative action , removing the gate
current does not cause the device to turn off.
• The forward resistance offered by the SCR is as low as 0.01Ω
to 0.1Ω
• The dynamic reverse resistance of SCR is as high as 100KΩ or
more.
Two Transistor Model
 Working
• The SCR consist of two devices can be recognized as two
transistors. The upper left one is P-N-P transistor and the
lower right N-P-N type.
• Further it can be recognized that the base of the P-N-P
transistor is joined to the collector of the N-P-N transistor
while the collector of P-N-P is joined to the base of N-P-N
transistor, as illustrated in fig.
• The gate terminal is brought out from the base of the N-
P-N material. This construction has been conceived
merely to explain the working of SCR, otherwise in
physical shape the SCR has four solid layers of P-N-P-N
type only.
• The 2 transistors are connected in such way that the base
and collector of each other is linked.
 Working
• When the gate current is zero or the gate terminal is
open, the only current in circulation is the leakage
current, which is very small in case of silicon device
specially and the total current is a little higher than sum
of individual leakage currents. Under these conditions P-
N-P-N device is said to be in its forward blocking or high
impedance ‘off state.
• As soon as a small amount of gate current is given to the
base of transistor Q2 by applying forward bias to its base-
emitter junction, it generates the collector current as
β2 times the base current.
 Working
• This collector current of Q2 is fed as input base current to
Q: which is further multiplied by β1 times as ICl which
forms input base current of Q2 and undergoes
further amplification.
• In this way both transistors feedback each other and the
collector current of each goes on multiplying. This
process is very quick and soon both the transistors drive
each other to saturation. Now the device is said to be in
ON-state. The current through the on-state SCR is
controlled by external impedance only.

Note :- Each transistors are named as Q1 and Q2 for better understanding.

 Switching Action
• Turn On- Make Gate pulse Positive
• Turn Off- Make Gate Pulse Ground- Negative-
Reduce anode current to ZERO.
• Eloberation wrt diagram

• Turn off mechanism is called Commutation.

• 2 types of commutations-
– Natural commutation
– Forced commutation
 Natural commutation
• If the source feeding ANODE terminal
naturally passes through ZERO , then SCR
automatically turned OFF. The case is when
SCR is fed from AC source.
 Forced commutation
• In this method the current through the SCR is
forced to become zero by passing current
through in it in opposite direction from an
independent ckt.
 Working
• Dc source is in series with SCR. When SCR is
conducting the IB=0 and transistor is OFF.
• To turn OFF SCR IB is made positive of pulse large
enough to drive transistor base. Thus transistor
almost acts as short circuit.
• This causes flow of very large Ioff through SCR in
opposite direction to its conduction current. The
total SCR current reduces to zero in a very short time
causing it to Turn off.
• The transistor has to withstand a large current but for
a very short time.
• Turn off time of an SCR is typically 5-30µs.
• Forward Characteristics
• When anode is positive w.r.t. cathode, the curve between V
and I is called the forward characteristics.
• Following key terms has to be mentioned in SCR
Characteristics
– Forward Breakover voltage- It is the minimum forward
voltage, gate being open, at which SCR starts conducting
heavily i.e. turned on.
– Holding current- It is the maximum anode current, gate
being open, at which SCR is turned OFF from ON
condition.
– Reverse Breakdown Voltage (Peak reverse voltage)- It is
the maximum reverse voltage (cathode positive w.r.t.
anode) that can be applied to an SCR without
conducting in the reverse direction.
– Forward and Reverse blocking regions
• These are the regions in which the SCR is open
circuited and no current flows from anode to
cathode.
 THE JFET
• The JFET ( junction field-effect transistor) is a type of
FET that operates with a reverse-biased pn junction
to control current in a channel.

• Depending on their structure, JFETs fall into either of

two categories, n channel or p channel.
Internal Diagram ( Structure of FET)
 Basic Operation
• To illustrate the operation of a JFET, Figure shows dc bias voltages
applied to an n-channel device. VDD provides a drain-to-source
voltage and supplies current from drain to source. VGG sets the
reverse-bias voltage between the gate and the source, as shown,
• The JFET is always operated with the gate-source pn
junction reverse-biased. Reverse biasing of the gate-
source junction with a negative gate voltage produces a
depletion region along the pn junction, which extends
into the n channel and thus increases its resistance by
restricting the channel width.
• The channel width and thus the channel resistance can
be controlled by varying the gate voltage, thereby
controlling the amount of drain current, ID. ( Can be seen
in Characteristics curve in later part).
• The white areas represent the depletion region created
by the reverse bias. It is wider toward the drain end of
the channel because the reverse-bias voltage between
the gate and the drain is greater than that between the
gate and the source.
JFET schematic symbols
 JFET CHARACTERISTICS AND PARAMETERS
• The JFET operates as a voltage-controlled, constant-
current device.
• Drain Characteristic Curve
• Pinch-Off Voltage- For VGS 0 V, the value of VDS at which ID
becomes essentially constant (point B on the curve in Figure is the
pinch-off voltage, VP.
• Breakdown- breakdown occurs at point C when ID begins to
increase very rapidly with any further increase in VDS
• Cutoff Voltage
The value of VGS that makes ID approximately zero is the cutoff
voltage, VGS(off),
• VGS Controls ID - Let’s connect a bias voltage, VGG, from gate
to source as shown in Figure. As VGS is set to increasingly
more negative values by adjusting VGG, a family of drain
characteristic curves is produced, as shown in Figure.

• Notice that ID decreases as the magnitude of VGS is

increased to larger negative values because of the narrowing
of the channel.
 JFET Universal Transfer Characteristic
• We have learned that a range of VGS values from zero to
VGS(off) controls the amount of drain current. For an n-
channel JFET, VGS(off) is negative, and for a p-channel
JFET, VGS(off) is positive.
• Because VGS does control ID, the relationship between
these two quantities is very important.
• Figure shown next is a general transfer characteristic
curve that illustrates graphically the relationship
between VGS and ID.
• This curve is also known as a transconductance curve.
 JFET Universal Transfer Characteristic

Notice that the bottom end of the curve is at a point on the VGS axis
equal to VGS(off ), and the top end of the curve is at a point on the
ID axis equal to IDSS. This curve shows that
ID = 0 when VGS = VGS(off)
D I =I / 4 when V = 0.5V
DSS GS GS(off)

ID = IDSS when VGS = 0

 JFET Forward Transconductance
• The forward transconductance (transfer conductance),
gm, is the change in drain current (ΔID)for a given
change in gate-to-source voltage (ΔVGS) with the drain-
to-source voltage constant.
• It is expressed as a ratio and has the unit of siemens (S).
• gm = ΔID/ ΔVGS
Input Resistance and Capacitance
• RIN = Magnitude of VGS/ IGSS
• AC Drain-to-Source Resistance
The ratio of these changes is the ac drain-to
source resistance of the device,
r’ds= ΔVDS/ Δ ID
 THE MOSFET
• The MOSFET (metal oxide semiconductor field-effect
transistor) is another category of field-effect transistor.
• The MOSFET, different from the JFET, has no PN junction
structure; instead, the gate of the MOSFET is insulated
from the channel by a silicon dioxide (SiO2) layer.
• The two basic types of MOSFETs are enhancement (E)
and depletion(D).
• Of the two types, the enhancement MOSFET is more
widely used.
• Because polycrystalline silicon is now used for the gate
material instead of metal, these devices are sometimes
called IGFETs (insulated-gate FETs).
Enhancement MOSFET (E-MOSFET)
• The E-MOSFET operates only in the enhancement mode.
• Notice in Figure (a) that the substrate extends completely
to the SiO2 layer.
• For an n-channel device, a positive gate voltage above a
threshold value induces a channel by creating a thin layer
of negative charges in the substrate region adjacent to
the SiO2 layer, as shown in Figure (b).
• The conductivity of the channel is enhanced by
increasing the gate-to-source voltage and thus pulling
more electrons into the channel area.
• For any gate voltage below the threshold value, there is
no channel.
Fig.a Fig.b
Schematic Symbols
 Depletion MOSFET (D-MOSFET)
• The drain and source are diffused into the substrate
material and then connected by a narrow channel
adjacent to the insulated gate. Both n-channel and p-
channel devices are shown in the figure.
• The D-MOSFET can be operated in either of two modes
– the depletion mode
– the enhancement mode
– (sometimes called a depletion/enhancement MOSFET)

• Since the gate is insulated from the channel, either a

positive or a negative gate voltage can be applied.

• The n-channel MOSFET operates in the depletion mode

when a negative gate-to-source voltage is applied.

• In the enhancement mode when a positive gate-to-

source voltage is applied. These devices are generally
operated in the depletion mode.
 Depletion Mode of D MOSFET
• Visualize the gate as one plate of a parallel-plate
capacitor and the channel as the other plate. The silicon
dioxide insulating layer is the dielectric.
• With a negative gate voltage, the negative charges on the
gate repel conduction electrons from the channel,
leaving positive ions in their place. Thereby, the n
channel is depleted of some of its electrons, thus
decreasing the channel conductivity.
• The greater the negative voltage on the gate, the greater
the depletion of n-channel electrons. At a sufficiently
negative gate-to-source voltage, VGS(off ), the channel is
totally depleted and the drain current is zero.
Depletion Mode of D MOSFET
 Enhancement Mode of D MOSFET
• Visualize the gate as one plate of a parallel-plate
capacitor and the channel as the other plate. The silicon
dioxide insulating layer is the dielectric.
• With a positive gate voltage, more conduction electrons
are attracted into the channel, thus increasing
(enhancing) the channel conductivity,
Enhancement Mode of D MOSFET
D MOSFET Schematic Symbols
 Laterally Diffused MOSFET(LDMOSFET)

• The LDMOSFET has a lateral channel structure and is a

type of enhancement MOSFET designed for power
applications.
• This device has a shorter channel between drain and
source than does the conventional
• E-MOSFET. The shorter channel results in lower resistance,
which allows higher current and voltage.
• When the gate is positive, a very short n channel is
induced in the p layer between the lightly doped source
and the n region.
• There is current between the drain and source through the
n regions and the induced channel as indicated.
Laterally Diffused MOSFET(LDMOSFET)
 V-groove MOSFET
• The V-groove MOSFET is to achieve higher power
capability by creating a shorter and wider channel with
less resistance between the drain and source using a
vertical channel structure.
• The VMOSFET has two source connections, a gate
connection on top, and a drain connection on the
bottom, as shown in Figure.
• The channel is induced vertically along both sides of the
V-shaped groove between the drain (n+ substrate where
n+ means a higher doping level than ) and the source
connections.
• The channel length is set by the thickness of the layers,
which is controlled by doping densities and diffusion
time rather than by mask dimensions.
V-groove MOSFET
 TMOSFET
• The vertical channel structure of the TMOSFET is
illustrated in Figure.
• The gate structure is embedded in a silicon dioxide
layer, and the source contact is continuous over the
entire surface area.
• The drain is on the bottom. TMOSFET achieves
greater packing density than VMOSFET, while
retaining the short vertical channel advantage.
TMOSFET
 Dual-Gate MOSFETs
• The dual-gate MOSFET can be either a depletion or an
enhancement type. The only difference is that it has two
gates, as shown in Figure
• By using a dual-gate device, the input capacitance is
reduced, thus making the device useful in high-frequency
RF amplifier applications. Another advantage of the dual-
gate arrangement is that it allows for an automatic gain
control (AGC) input in RF amplifiers.
• Another application is demonstrated in the Application
Activity where the bias on the second gate is used to
adjust the transconductance curve.
Dual-Gate MOSFETs
 CMOS
• CMOS is Complimentary MOS wherein 2 enhancement
MOSFET’s, one N type and other P type are connected as
Complimentary pair.
• The pairs are connected such that they form proper input and
output configuration as shown in figure
• The CMOS offers following 2 advantages,
– The drain current is low and flows mainly during transition
from one state to the other ( On/Off)
– The power drawn in steady state is extremely small.
 Digital Circuit Applications

NMOS
NMOS is built on a p-type substrate with n-type source and drain diffused on it.
In NMOS, the majority carriers are electrons. When a high voltage is applied to
the gate, the NMOS will conduct. Similarly, when a low voltage is applied to the
gate, NMOS will not conduct. NMOS are considered to be faster than PMOS,
since the carriers in NMOS, which are electrons, travel twice as fast as the holes.
PMOS
P- channel MOSFET consists P-type Source and Drain diffused on an N-type
substrate. Majority carriers are holes. When a high voltage is applied to the gate,
the PMOS will not conduct. When a low voltage is applied to the gate, the PMOS
will conduct. The PMOS devices are more immune to noise than NMOS devices.
CMOS INVERTER