Scribd
Upload
24 views

Features of RISC

Uploaded by

abansal10be22
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
24 views

Features of RISC

Uploaded by

abansal10be22
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 9

Features of RISC

• Features of RISC
• The following are some of the features of RISC
• Feature 1
• RISC processors have a fixed instruction size. In
a CISC microcontroller such as the 8051,
instructions can be 1, 2, or even 3 bytes.
• In a RISC architecture, the size of all instructions
is fixed. Therefore, the CPU can decode the
instructions quickly.
• Feature 2
• One of the major characteristics of RISC architecture
is a large number of registers. All RISC architectures
have at least 32 registers. Of these 32 registers, only
a few are assigned to a dedicated function.
• One advantage of a large number of registers is that
it avoids the need for a large stack to store
parameters. Although a stack can be implemented
on a RISC processor, it is not as essential as in CISC
because so many registers are available.
• Feature 3
• RISC processors have a small instruction set. RISC processors have
only the basic instructions such as ADD, SUB, MUL, LOAD, STORE,
AND, OR, EXOR,CALL,JUMP,and so on.
• The limited number of instructions is one of the criticisms leveled at
the RISC processor because it makes the job of Assembly language
programmers much more tedious and difficult compared to CISC
Assembly language programming. This is one reason that RISC is
used more commonly in high-level language environments such as
the C programming language rather than Assembly language
environments. The limited number of instructions in RISC leads to
programs that are large. Although these programs can use more
memory, this is not a problem because memoryischeap.
• Feature 4
• The most important characteristic of the RISC
processor is that more than 95% of
instructions are executed with only one clock
cycle,in contrast to CISC instructions. Even
some of the 5% of the RISC instructions that
are executed with two clock cycles can be
executed with one clock cycle by juggling
instructions around (code scheduling).
• Feature 5
• RISC processors have separate buses for data and code. In all the x86
processors, like all the CISC computers, there is one set of buses for the
address (e.g.,A0—A24 in the 80286) and another set of buses for data
(e.g.,D0—D15inthe 80286) carrying opcodes and operands in and out of
the CPU. To access any section of memory, regardless of whether it
contains code or data operands, the same address bus and data bus are
used. In RlSC processors, there are four sets of buses:
• (1)a set of data buses for carrying data (operands) in and out of the CPU
• (2)a set of address buses for accessing the data
• (3)a set of buses to carry the opcodes
• (4)A set of address buses to access the opcodes.
• Feature 6
• Because CISC has such a large number of
instructions, each with so many different
addressing modes, and the execution of
instructions inside the CPU takes more than 40
—60% of transistors in many CISC processors.
• In the case of RlSC, however, due to the small
set of instructions, they are implemented
using the hardwire method. Hardwiring of
RISC instructions takes no more than 10% of
the transistors.
• Feature 7
• RISC uses load/store architecture. In CISC microprocessors, data
can be manipulated while it is still in memory. For example, in
instructions such as “ADD Reg, Memory”, the microprocessor
must bring the contents of the external memory location into the
CPU, add it to the contents of the register, then move the result
back to the external memory location. The problem is there might
be a delay in accessing the data from external memory.
• In RISC, instructions can only load from external memory into
registers or store registers into external memory locations. There
is no direct way of doing arithmetic and logic operations between
a register and the contents of external memory locations.

You might also like