Instruction and Instruction

Sequencing
“Must-Perform” Operations
 Data transfers between the memory and the processor
registers
 Arithmetic and logic operations on data
 Program sequencing and control
 I/O transfers
Register Transfer Notation
 Identify
a location by a symbolic name standing for its
hardware binary address (LOC, R0,…)
 Contents of a location are denoted by placing square

brackets around the name of the location (R1←[LOC], R3

←[R1]+[R2])
 Register Transfer Notation (RTN)
Assembly Language Notation
 Represent machine instructions and programs.
 Move LOC, R1 = R1←[LOC]
 Add R1, R2, R3 = R3 ←[R1]+[R2]
CPU Organization
 Single Accumulator
 Result usually goes to the Accumulator
 Accumulator has to be saved to memory quite
often
 General Register
 Registers hold operands thus reduce memory
traffic
 Register bookkeeping
 Stack
 Operands and result are always in the stack
 Instruction Formats
 Three-Address Instructions
 ADD A,B,C C←[ A] +[ B]
 Operation source1, source2,destination
 Two-Address Instructions
 ADD A, B B ← [A] +[B]
 Operation source, destination
 One-Address Instructions
 ADD A AC ← AC + [A]
 LOAD A AC←[A]
 STORE A [A]←AC
Zero-Address Instructions
 INC AC ← AC+1

Opcode Operand(s) or Address(es)

 C←[ A] +[ B]
Three-Address Instructions
 ADD A,B,C

Two-Address Instructions
• ADD A,B
• MOVE B,C

One-Address Instructions
• LOAD A
• ADD B
• STORE C
Using Registers
 Registers are faster
 Shorter instructions
 The number of registers is smaller (e.g. 32 registers need 5 bits)
 Minimize the frequency with which data is moved back and
forth between the memory and processor registers.
 Let Ri represents a general purpose register,
 LOAD A,Ri
 STORE Ri,A
 ADD A,Ri
 Only one memory address is specified in instruction, still may

not fit into one word

Instuctions may have only registers
 ADD Ri,Rj
 ADD Ri, Rj, Rk

Since only registers in instruction , it fits into one word

 MOVE A,Ri is same as LOAD A,Ri
 MOVE Ri,A is same as STORE Ri,A

EX:C=A+B ,if arithmetic operations are allowed on registers

MOVE A,Ri
MOVE B,Rj
ADD Ri,Rj
Move Rj,C
Instruction Formats
Example: Evaluate X= (A+B)  (C+D)
 Three-Address

1. ADD A, B,E ; E ← [A] +

[B]
2. ADD C, D,F ; F ← [C] +
[D]
3. MUL E, F,X ; X ← [E]*[F]
Instruction Formats
Example: Evaluate X= (A+B)  (C+D)
 Two-Address

1. ADD A,B ; B←[A] + [B]

2. ADD C, D ; D ← [C] +
[D]
3. MUL B,D ; D ← [B] 
[D]
4. MOV D,X ; X ← [D]
Instruction Formats
Example: Evaluate X=(A+B)  (C+D)
 One-Address

1. LOAD A ; AC ← [A]
2. ADD B ; AC ← AC +
[B]
3. STORE T ; [T] ← AC
4. LOAD C ; AC ← [C]
5. ADD D ; AC ← AC +
[D]
6. MUL T ; AC ← AC 
[T]
7. STORE X ; [X] ← AC
Instruction Execution and Straight-Line
Sequencing
Address Contents

i
Assumptions:
Begin execution here Move A,R0
i+4
3-instruction
program
- One memory operand
Add B,R0
segment per instruction
i+8 Move R0,C
- 32-bit word length
- Memory is byte
addressable
A - Full memory address
can be directly specified
in a single-word instruction
B Data for
the program
Two-phase procedure
-Instruction fetch
-Instruction execute
C
Page 43

Figure 2.8. A program for C ¬ [A] + [B].

 i Move NUM1,R0
i+4 Add NUM2,R0

Branching i+8 Add NUM3,R0

•
•
•
i + 4n - 4 Add NUMn,R0
i + 4n Move R0,SUM

•
•
•
SUM
NUM1
NUM2

•
•
•
NUMn

Figure 2.9. A straight-line program for adding n numbers.

 Move N,R1
Clear R0

Branching LOOP
Determine address of
"Next" number and add
Program "Next" number to R0
loop
Decrement R1
Branch>0 LOOP
Branch target
Move R0,SUM

Conditional branch

•
•
•
SUM
N n
NUM1

Figure 2.10. Using a loop to add n numbers. NUM2

•
•
•
NUMn
Condition Codes
 Condition code flags
 Condition code register / status register
 N (negative)
 Z (zero)
 V (overflow)
 C (carry)
 Different instructions affect different flags
Conditional Branch Instructions
 Example: A: 11110000
 A: 1 1 1 1 0 0 0 0 +(−B): 1 1 1 0 1 1 0 0
 B: 0 0 0 1 0 1 0 0 11011100

C=1 Z=0
S=1
V=0
Status Bits

Cn-1
A B

Cn ALU
F
V Z S C
Fn-1

Zero Check