8085 Microprocessor

8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor

designed by Intel in 1977 using NMOS technology.

It has the following configuration −

8-bit data bus

16-bit address bus, which can address upto 64KB
A 16-bit program counter
A 16-bit stack pointer
Six 8-bit registers arranged in pairs: B-C, D-E, H-L
Requires +5V supply to operate at 3.2 MHZ clock
 8085 Microprocessor
8085 consists of the following functional units −

Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It is
connected to internal data bus & ALU.

Arithmetic and logic unit

As the name suggests, it performs arithmetic and logical operations like Addition,
Subtraction, AND, OR, etc. on 8-bit data.

General purpose register

There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register
can hold 8-bit data.

These registers can work in pair to hold 16-bit data and their pairing combination is like B-C,
D-E & H-L.
Pins diagram of 8085
HOLD − This signal indicates that another master is requesting the use of the address and
data buses. HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD
request and it will relinquish the bus in the next clock cycle.

READY − This signal indicates that the device is ready to send or receive data. If READY is
low, then the CPU has to wait for READY to go high.

RESET_IN* pin which is an active low input pin. We RESET 8085 by placing a logic 0 on this
pin at least for 0.5μs, after that the power is supplied to Vcc pin of 8085

RESET OUT − This signal is used to reset all the connected devices when the
microprocessor is reset
8085 architecture and its block diagram
 Signal descriptions and pins of 8085
Control is provided by a variety of lines which support memory and I/O interfacing,
requiring only a 5 volt supply.

The 8085 comes in two models, the 8085A and the 8085A-2. The 8085A expects clock
frequency of 3 MHz, while the 8085A-2 expects clock frequency of 5 MHz. This clock is
generated by a crystal externally.

The 8085 make use of multiplexing of the lower 8 bits of the address with the data bits on
the same 8 pins. This requires that the external circuitry be able to catch and hold the A0-
A7 lines for later use.

The upper 8 bits of the address have their own pins, however.

The General Purpose Register Array contains the B, C, D, E, H, and L registers, each 8
bits wide. The B and C, D and E, and H and L registers may be grouped into 16-bit
register pairs. The H & L register pair may be used to store indirect addresses.

An address generation system consisting of the Program Counter, Stack Pointer, address
latches, and incremented / decremented.

The array also contains the Program Counter (PC) and Stack Pointer (SP). These 16-bit
registers contain the address of the next instruction part to be fetched, and the address of
the top of the stack, respectively.
 STATUS FLAG REGISTER
The Status Flags of the 8085 indicate the logical conditions that existed as a result of the
execution of the instruction just completed.

S Z x A C x P x C
ZERO FLAG: This flag is set to a 1 by the instruction just ending if the A Register
contains a result of all 0’s.Otherwise 0.

SIGN FLAG: This flag is set to a 1 by the instruction just ending if the leftmost, bit of
the A Register is set to a 1. Otherwise 0.

PARITY FLAG: This flag is set to a 1 by the instruction if the A Register is left with an
even number of bits set on, i.e., in even parity. Otherwise 0.

CARRY FLAG: This flag is set to a 1 by the instruction just ending if a carry out of the
leftmost bit occurred during the execution of the instruction. Otherwise 0.

AUXILIARY CARRY FLAG: This flag is set to a 1 by the instruction just ending if a
carry occurred from bit 3 to bit 4 of the A Register. Otherwise 0.
 Timing and control unit
Timing Diagram is a graphical representation. It
represents the execution time taken by each
instruction in a graphical format. The execution
time is represented in T-states.

One byte, two byte and three byte instruction

Instruction Cycle: The time required to execute an

instruction. (Fetch cycle + Execution cycle)
Machine Cycle: The time required to access the
memory or input/output devices .

T-State: Subdivision of operation performed in one

clock cycle. The machine cycle and instruction cycle
takes multiple clock cycles.

One time period of frequency of microprocessor is

called t-state.
 Timing and control unit

The 8085 microprocessor has following machine cycles.:

1. Op-code Fetch cycle(4T or 6T).
2. Memory read cycle (3T)
3. Memory write cycle(3T)
4. I/O read cycle(3T)
5. I/O write cycle(3T)
6. Interrupt Acknowledge cycle(6T or 12T)
Timing and control unit
Instruction set of 8085: -

DATA TRANSFER: -

1. MOV r1, r2
Move contents of register (A, B, C, D, E, H, L) r2 to r1.
Eg. MOV A, B Move the contents of B to A

2. MVI r, data Move the data to the specify register

Eg. MVI C, F0H Move the data F0 to the reg C

3. LDA 2000H
Load the contents of memory location 2000 to Accu. A
4. LXIH 2000H
Load the 20 to H Load the 00 to L
5. MOV A, M
Load the value of data from mem location 2000 to A.
DATA TRANSFER: -
6. MOV M, A
Load the value of A to the memory pointed by HL pair.
7. MVI M, F0H
Load F0 to the memory pointed by HL pair.
8. STA 2000H
Store the data of Accu. A to the memory 2000H
9. LHLD 2000H
Data of 2000 to L, Data of 2001 to H
10. SHLD 2000H
Store the value of L to 2000 & H to 2001
11. LDAX D
If DE=2000H, then load the value of 2000 to Accu. A
12. STAX D
if DE=3000H, Store the value of A to the 3000H
13. XCHG Exchange the value of DE with HL pair.
ARITHMETIC: -

1.ADD C A+C=A
2.ADD M A+[H-L]=A
3.ADI F0H A+F0=A
4.ADC C A+C+[CF]=A
5.ADC M A+[H-L]+[CF]=A
6.ACI F0H A+F0+[CF]=A
7.DAD D H-L+D-E=H-L
8. SUB B A-B=A
9. SUB M A-[H-L]=A
10.SUI F0H A-F0=A
11.SBB B A-B-[CF]=A
12.SBB M A-[H-L]-[CF]=A
13.SBI F0H A-[F0]-[CF]=A
14.INR D Increment the content of D by one
15 INX D Increment the content of DE pair by one
16.DCR L Decrement the content of L by one.
17.DCR H Decrement the content of HL pair by one.
LOGICAL GROUP: -
1. ANA D Logical AND Between the contents of A and D
2. AND M
Logical AND Between the contents of A and [H-L]
3. ANI F0 H
Logical AND Between the contents of A and F0 H
4. ORA C
Logical OR Between the contents of A and C
5. ORA M
Logical OR Between the contents of A and [H-L]
6. ORI F0 H
Logical OR Between the contents of A and F0 H
7. XRA C Logical XOR Between the contents of A and C
8. XRA M Logical XOR Between the contents of A and [H-L]
9. XRI 0F H
Logical XOR Between the contents of A and 0F H
 10. CMA Complement the contents of
A only.

11. CMC Complement the carry

status.

12. STC Set the carry flag.

13. CMP M Compare the contents of A
and [H-L].
i.e. A-[HL]. But the contents of A
and [HL] are not changed.
15. CPI F0 H
BRANCH GROUP: -
Unconditional
1. JMP 2000 Jump to the location 2000
2. CALL 2000 Jump to the location 2000

Conditional
1. JZ 2000
Jump to the location 2000 if there is zero in result i.e. in Accu.
2. JNZ 2000
Jump to the location 2000 if there is non zero in result i.e. in Accu.
3. JC 2000
Jump to the location 2000 if there is carry in result
4. JNC 2000
Jump to the location 2000 if there is no carry in result i.e. in Accu.
Conditional
5. JP 2000
Jump to the location 2000 if result is positive in Accu.
6. JM 2000
Jump to the location 2000 if result is negative in Accu.
7. JPE 2000
Jump to the location 2000 if result contain even parity in Accu.
8. JPO 2000
Jump to the location 2000 if result contain odd parity in Accu.
9. RET Return from the subroutine.
10. PUSH C Push the contents of C reg. into stack.
11. POP D Retrieve the contents of stack top into reg C.
12. HLT End of the program.
13. NOP No operation.
OPCODE FORMAT
Registered code Register pair code
B 000 BC 00
C 001 DE 01
D 010 HL 10
E 011
H 100
L 101
M 110
A 111
 ADDRESSING MODES

Immediate Addressing Mode:-

The data to be used is given in the instruction
itself. Immediate addressing mode instruction are
either 2 byte or 3 byte long.
EX. MVI A, 20H ADI 30H LXI H, C200H

Register addressing mode

This mode of addressing specify the register or
register pair that contain the data.
EX. MOV A, B ADD B
Direct addressing mode
In this mode the operand is given by a direct address where
the data is present. The direct addressing mode instruction is
a 3 byte inst.
EX. LDA 2000H STA 2000H

Indirect Addressing Mode

Here Inst. Does Not Have Address Of The Data. But The
Instruction Point Where The Address Is Stored
EX. MOV A, M MOV M, A

Implied or inherent addressing mode

This mode does not required any operand. The data is
specified within the opcode itself.
EX. RAL RAR
 INSTRUCTION TYPE

The first part of the instruction is called opcode and the

second part is called operand. The operand may be either 8
bit data or memory location. Depending upon the number of
bytes required to specify an operation the instruction are of 3
bytes.

ONE BYTE INSTRUCTION:-

A 1 byte instruction include the opcode and the operand in
the 8 bits only i.e. One byte

MOV A, B
MOV A, C
ADD B
TWO BYTE INSTRUCTION:-
The 2 byte instruction uses first byte to specify the operation
and second byte to specify the operand.

MVI A, 20
MVI B, 30

THREE BYTE INSTRUCTION:-

The 3 byte instruction uses first byte to specify the operation,
second and third bytes are used to specify the operand.
Generally those instruction are used to specify memory
address.

LDA 2000H
LXIH 2101H
 INSTRUCTION TYPE
The first part of the instruction is called opcode and the second part is called operand. The operand
may be either 8 bit data or memory location. Depending upon the number of bytes required to specify
an operation the instruction are of 3 bytes.

ONE BYTE INSTRUCTION:-

A 1 byte instruction include the opcode and the operand in the 8 bits only i.e. One byte

MOV A, B 01 111 000 = 78H

MOV A, C 01 111 001 = 79H
ADD B 1000 0 000 = 80H

TWO BYTE INSTRUCTION:-

The 2 byte instruction uses first byte to specify the operation and second byte to specify the operand.

MVI A, 20 0011 1110 0010 0000

MVI B, 30 0000 0110 0011 0000

THREE BYTE INSTRUCTION:-

The 3 byte instruction uses first byte to specify the operation, second and third bytes are used to
specify the operand. Generally those instruction are used to specify memory address.

LDA ADDRESS
To find the addition of
two eight bit numbers
sum is 8 bits.

LXIH 2501 H ADDITION OF TWO 8-BIT NUMBER, SUM

MOV A,M 16 BITS
INX H
ADD M LXI H,2501H
STA 2503 H MVI C,00
HLT MOV A,M
INX H
ADD M
To find the subtraction of JNC
two eight bit numbers
INR C
STA 2503H
LXIH 2501 H
MOV A,M MOV A,C
INX H STA 2504H
SUB M HLT
INX H
MOV M,A
HLT
Disclaimer:
Proposed notes in the PPT are for your reference and for more detail description kindly
refer the text books and reference books of the syllabus.

As per the new guidelines MTE/ETE question paper may be from the external agency.
Therefore, it is requested to prepare yourself through the suggested reading materials
in the syllabus also.