Scribd
Upload
20 views

Memory Organization in ARM7: Von Neumann Architecture Harvard Architecture

Uploaded by

itssam4577
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
20 views

Memory Organization in ARM7: Von Neumann Architecture Harvard Architecture

Uploaded by

itssam4577
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 8

Memory Organization in ARM7

• The ARM7 processor uses a 32-bit address bus, which allows access to a 4GB addressable memory space.
• Memory regions within this address space can be allocated for different types of storage (RAM, ROM, Flash)
or peripherals.
• ARM7 supports both von Neumann architecture and Harvard architecture.

• Memory Types in ARM7:

Normal Memory: Used for program code and data.


Device Memory: Used for peripherals like I/O devices.
Strongly Ordered Memory: Memory where the order of reads and writes is strictly enforced, typically used for
critical system control.

Support Big Endian and Little Endian


memory configurations. This feature
allows flexibility in how the processor
handles multi-byte data formats.
Instruction set
• MOV R0, R1 – Copies the value from R1 to R0.
• MOV R0, # <imm> - Move the value <imm> into register R0
• MVN R0, R1 – Stores the bitwise negation of R1 into R0.
• PUSH {R0} – Stores the value of R0 onto the stack.
• POP {R0} – Retrieves the top value from the stack and stores it
into R0.
Example
PUSH {r0,r4-r7} //This instruction pushes the values of r0 and r4 to r7 onto the
stack.
PUSH {r2,lr} // pushes the value of r2 and the Link Register (lr) onto the
stack.
POP {r0,r10,pc} // This instruction pops the values from the stack into the
registers r0, r10, and pc.
• ADD R0, R1, R2 - Adds contents of R1 and R2 and stores the result into R0
// r0 and r10 will get the first two values popped from the
(Rd)
stack.
• ADD R0, R1, #2 - Adds contents of R1 and the value 2 and stores the result
//pc (Program Counter) will be loaded with the next value
into
• from R0
LSL the (Rd)
Rd, stack
Rn, #<imm> - LSL shifts the bits of Rn to the left by <imm> positions. It fills the
Tryright
for side
subtract
with zeros
• LSL Rd, Rn, Rs - shifts the value in Rn left by a number of bits specified in the register Rs.
Try for right
• ROR Rd, Rn, #<imm> - rotates the bits in Rn to the right by #<imm> positions and stores the
result in Rd.
Try for left
MUL <Rd>, <Rn>, <Rm> : Multiply two registers and store the result in a
destination register.
MLA R10, R2, R1, R5 : Multiply with accumulate, R10 = (R2 × R1) + R5
MLS R4, R5, R6, R7 : Multiply with subtract, R4 = R7 - (R5 × R6)

SDIV R0, R2, R4 : Signed divide, R0 = R2/R4


UDIV R8, R8, R1 : Unsigned divide, R8 = R8/R1

CMP <Rn>, <operand2> : (Rn - operand2) and sets the flags based on the
result

CLZ <Rd>, <Rn> : Count Leading Zeros


Logical instruction

AND R0, R1, R2 @ R0 = R1 & R2 (bitwise AND)


ORN R0, R1, R2 @ R0 = R1 | ~(R2) (bitwise OR
with NOT R2)

*****Try other instructions


1. ARM supports three primary types of data transfer instructions:
Single Data Transfer (LDR/STR)
• These instructions are used to transfer a single word, byte, or halfword between a register
and memory.
• Instructions:
 LDR (Load Register): Loads data from memory to a register.
 STR (Store Register): Stores data from a register to memory.
2. Block Data Transfer (LDM/STM)
• These instructions allow for transferring multiple registers to or from memory in a single
operation. Useful for saving or restoring register contents.
• Instructions:
 LDM (Load Multiple): Loads multiple registers from memory.
 STM (Store Multiple): Stores multiple registers to memory.
3. Swap Data Transfer (SWP)
• This instruction is used for swapping a value between a register and a memory location.
• Instructions:
 SWP (Swap): Exchanges the values between a register and a memory location.

LDR R0, [R1] ; Load the value from the memory address stored in R1
into R0
STR R2, [R3] ; Stores the value found in R2 to the memory address
found in R3.
Register Indirect with Offset addressing mode in ARM is an extension of register indirect
addressing. In this mode, the effective memory address is calculated by adding or subtracting an
immediate value (offset) or the value of another register to/from the base register.

LDR R0, [R1, #4] ; Load the value from the memory address (R1 + 4) into R0
STR R2, [R3, #-8] ; Store the value in R2 into the memory address (R3 - 8)

Auto-indexing in ARM refers to an addressing mode where the address used for loading or
storing data is automatically updated after the operation, without requiring extra instructions

Pre-indexing:
LDR R1, [R2, #4]! : Here, R2 is first incremented by 4, then the value from the memory address
is loaded into R1.

Post-indexing:
LDR R1, [R2], #4 Here, the value at the memory address pointed to by R2 is first loaded into R1,
and then R2 is incremented by 4 after the operation.
****Try for STR also
DR instruction can load data in different sizes: word, half-word, or byte.
(Word): This loads a 32-bit word (4 bytes).
LDR R1, [R2, #4]!: Loads a full 32-bit word from the memory address [R2 + 4] into R1.

H (Half-Word): This loads a 16-bit half-word (2 bytes).


LDRH R1, [R2, #4]!: Loads a 16-bit half-word from the memory address [R2 + 4] into R1.

B (Byte): This loads an 8-bit byte.


LDRB R1, [R2, #4]!: Loads an 8-bit byte from the memory address [R2 + 4] into R1.

SB (Signed Byte): This loads a signed 8-bit and extends it to 32 bits.


LDRSB R1, [R2, #4]!: Loads a signed 8-bit from [R2 + 4] and sign-extends it to 32 bits in R1.

SH (Signed Half-Word): This loads a signed 16-bit half-word and extends it to 32 bits.
LDRSH R1, [R2, #4]!: Loads a signed 16-bit half-word from [R2 + 4] and sign-extends it to 32 bits in R1

Try for STR


Multiple register load and store
IA R0, {R1, R2, R3} : Stands for Load Multiple Increment After.
LDM means to load multiple registers.
IA (Increment After) means that the base register (R0) will be incremented after each memory access.
R0: This is the base register that holds the starting memory address.
{R1, R2, R3}: This is the list of registers that will be loaded with data.
R1 from the memory address in R0,
R2 from the memory address in R0 + 4,
R3 from the memory address in R0 + 8.
R0 remains unchanged in this instruction ***Read Decrement before and after

LDMIB R0, {R1, R2, R3}: Stands for Load Multiple Increment
Before.
• R0 is incremented by 4 before each load.
• The value at the memory address R0 + 4 is loaded into R1.
• The value at the memory address R0 + 8 is loaded into R2.
• The value at the memory address R0 + 12 is loaded into
LDMIB
R3. R0!, {R1, R2, R3}
• The ! after R0 means that the updated value of R0 will be written back to the
register after the instruction finishes.
• After the instruction is executed, R0 will hold the address R0 + 12
Control flow instructions

Control flow instructions in ARM assembly are used to change the flow of execution in a
program, typically by branching or jumping to different parts of the code based on certain
conditions.
Instructions:
B (Branch): Unconditional branch to a target address or label.
BL (Branch with Link): Branches to a subroutine, saving the return address in the LR
(Link Register).
Conditional branches:

BEQ (Branch if Equal): Branches if the Zero flag is set


BNE (Branch if Not Equal): Branches if the Zero flag is not set.
BGT (Branch if Greater Than): Branches if the signed result is greater than.
BLT (Branch if Less Than): Branches if the signed result is less than.

You might also like