Computer Organization &

Architectures
Topic: Input Output Organization
Unit-IV
 INPUT-OUTPUT ORGANIZATION
UNIT-IV

• Peripheral Devices . Memory hierarchy

• Input-Output Interface . Main Memory
• Asynchronous Data Transfer . Auxiliary Memory
• Modes of Transfer . Associative Memory
• Priority Interrupt . Cache Memory
• Direct Memory Access

• Input-Output Processor

• Serial Communication

G.SWARNALATHA,Asst.Professor, GNITC
 Peripheral Devices

UNIT-IV PERIPHERAL DEVICES

Input Devices Output Devices

• Keyboard • Card Puncher, Paper Tape Puncher
• Optical input devices • CRT
- Card Reader • Printer (Impact, Ink Jet,
- Paper Tape Reader Laser, Dot Matrix)
- Bar code reader • Plotter
- Digitizer • Analog
- Optical Mark Reader • Voice
• Magnetic Input Devices
- Magnetic Stripe Reader
• Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
• Analog Input Devices

G.SWARNALATHA,Asst.Professor, GNITC
UNIT-IV

G.SWARNALATHA,Asst.Professor, GNITC
UNIT-IV

G.SWARNALATHA,Asst.Professor, GNITC
 Input/Output Interfaces
UNIT-IV INPUT/OUTPUT INTERFACE
• Provides a method for transferring information between internal storage
(such as memory and CPU registers) and external I/O devices

• Resolves the differences between the computer and peripheral

devices(External I/O devices)

G.SWARNALATHA,Asst.Professor, GNITC
 Input/Output Interfaces
UNIT-IV I/O BUS AND INTERFACE MODULES
I/O bus
Data
Processor Address
Control

Interface Interface Interface Interface

Keyboard
and Printer Magnetic Magnetic
display disk tape
terminal

Each peripheral has an interface module associated with it Interface

- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory
Typical I/O instruction
Op. code Device address Function code
(Command)

G.SWARNALATHA,Asst.Professor, GNITC
 Input/Output Interfaces
UNIT-IV CONNECTION OF I/O BUS
Connection of I/O Bus to CPU
Op. Device Function Accumulator Computer
code address code register I/O
control
CPU
Sense lines
Data lines
Function code lines
I/O
bus
Device address lines

Connection of I/O Bus to One Interface

Data lines
Peripheral
register

Device Buffer register

Output
address peripheral
I/O AD = 1101 Interface
device
and
bus Logic controller

Function code Command

decoder

Sense lines Status

register

G.SWARNALATHA,Asst.Professor, GNITC
 Input/Output Interfaces
UNIT-IV I/O BUS AND MEMORY BUS
Functions of Buses
* MEMORY BUS is for information transfers between CPU and the MM
* I/O BUS is for information transfers between CPU
and I/O devices through their I/O interface
Physical Organizations
* Many computers use a common single bus system
for both memory and I/O interface units
- Use one common bus but separate control lines for each funct
- Use one common bus with common control lines for both functions
* Some computer systems use two separate buses,
one to communicate with memory and the other with I/O interfaces
I/O Bus
- Communication between CPU and all interface units is via a common
I/O Bus
- An interface connected to a peripheral device may have a number of
data registers , a control register, and a status register
- A command is passed to the peripheral by sending
to the appropriate interface register
- Function code and sense lines are not needed (Transfer of data, control,
and status information is always via the common I/O Bus)

G.SWARNALATHA,Asst.Professor, GNITC
 Input/Output Interfaces

UNIT-IV ISOLATED vs MEMORY MAPPED I/O

Isolated I/O
- Separate I/O read/write control lines in addition to memory read/write
control lines
- Separate (isolated) memory and I/O address spaces
- Distinct input and output instructions

Memory-mapped I/O
- A single set of read/write control lines
(no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space
-> reduces memory address range available
- No specific input or output instruction
-> The same memory reference instructions can
be used for I/O transfers
- Considerable flexibility in handling I/O operations

G.SWARNALATHA,Asst.Professor, GNITC
 Input/Output Interfaces

UNIT-IV I/O INTERFACE

Port A I/O data
register
Bidirectional Bus
data bus buffers
Port B I/O data
register

Internal bus
CPU Chip select CS
I/O
Register select RS1 Control Control Device
Timing register
Register select RS0 and
I/O read Control
RD Status Status
I/O write WR register

CS RS1 RS0 Register selected

0 x x None - data bus in high-impedence
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register

G.SWARNALATHA,Asst.Professor, GNITC
UNIT-IV
Input/Output Interfaces

Programmable Interface
 Information in each port can be assigned a meaning depending on the
mode of operation of the I/O device
→ Port A = Data; Port B = Command; Port C = Status
 CPU initializes(loads) each port by transferring a byte to the Control
Register
→ Allows CPU can define the mode of operation of each port
→ Programmable Port: By changing the bits in the control register, it is
possible to change the interface characteristics

G.SWARNALATHA,Asst.Professor, GNITC
 Asynchronous Data Transfer

UNIT-IV ASYNCHRONOUS DATA TRANSFER

Synchronous and Asynchronous Operations

Synchronous - All devices derive the timing

information from common clock line
Asynchronous - No common clock
Asynchronous Data Transfer
Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to
indicate the time at which data is being transmitted
Two Asynchronous Data Transfer Methods
Strobe pulse
- A strobe pulse is supplied by one unit to indicate
the other unit when the transfer has to occur
Handshaking
- A control signal is accompanied with each data
being transmitted to indicate the presence of data
- The receiving unit responds with another control
signal to acknowledge receipt of the data
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 Asynchronous Data Transfer

UNIT-IV STROBE CONTROL

* Employs a single control line to time each transfer

* The strobe may be activated by either the source or
the destination unit

Source-Initiated Strobe Destination-Initiated Strobe

for Data Transfer for Data Transfer

Block Diagram Block Diagram

Data bus Data bus
Source Destination Source Destination
unit Strobe unit unit Strobe unit

Timing Diagram Timing Diagram

Valid data Valid data
Data Data

Strobe Strobe

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 Asynchronous Data Transfer

UNIT-IV HANDSHAKING

Strobe Methods
 Source-Initiated

The source unit that initiates the transfer has

no way of knowing whether the destination unit
has actually received data

 Destination-Initiated

The destination unit that initiates the transfer

no way of knowing whether the source has
actually placed the data on the bus
To solve this problem, the HANDSHAKE method
introduces a second control signal to provide a Reply
to the unit that initiates the transfer

G.SWARNALATHA,Asst.Professor, GNITC
 Asynchronous Data Transfer
UNIT-IV SOURCE-INITIATED TRANSFER USING HANDSHAKE
Data bus
Source Data valid Destination
Block Diagram unit Data accepted unit

Valid data
Data bus
Timing Diagram

Data valid

Data accepted

Sequence of Events Source unit Destination unit

Place data on bus.
Enable data valid.
Accept data from bus.
Enable data accepted
Disable data valid.
Invalidate data on bus.
Disable data accepted.
Ready to accept data
(initial state).
* Allows arbitrary delays from one state to the next
* Permits each unit to respond at its own data transfer rate
* The rate of transfer is determined by the slower unit
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UNIT-IV
Asynchronous Data Transfer

DESTINATION-INITIATED TRANSFER USING HANDSHAKE

Data bus
Block Diagram Source Data valid Destination
unit Ready for data unit

Timing Diagram Ready for data

Data valid

Valid data
Data bus

Sequence of Events Source unit Destination unit

Ready to accept data.
Place data on bus. Enable ready for data.
Enable data valid.

Accept data from bus.

Disable data valid. Disable ready for data.
Invalidate data on bus
(initial state).

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 Asynchronous Data Transfer

UNIT-IV
DESTINATION-INITIATED TRANSFER USING HANDSHAKE

 Handshaking provides a high degree of flexibility and reliability because the

successful completion of a data transfer relies on active participation by both

units

 If one unit is faulty, data transfer will not be completed

 Can be detected by means of a timeout mechanism

G.SWARNALATHA,Asst.Professor, GNITC
 Asynchronous Data Transfer

UNIT-IV ASYNCHRONOUS SERIAL TRANSFER

Asynchronous serial transfer
Four Different Types of Transfer Synchronous serial transfer
Asynchronous parallel transfer
Synchronous parallel transfer
Asynchronous Serial Transfer
- Employs special bits which are inserted at both
ends of the character code
- Each character consists of three parts; Start bit; Data bits; Stop bits.

1 1 0 0 0 1 0 1
Start Character bits Stop
bit bits
(1 bit) (at least 1 bit)

A character can be detected by the receiver from the knowledge of 4 rules;

1. When data are not being sent, the line is kept in the 1-state (idle state)
2. The initiation of a character transmission is detected by a Start Bit
which is always a 0
3. The character bits always follow the Start Bit
4. After the last character , a Stop Bit ,which is always 1 is detected and
the line returns to the 1-state for at least 1 bit time The receiver knows in
advance the transfer rate of the bits and the number of information bits to expect

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UNIT-IV
Asynchronous Data Transfer
UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER
- UART -
A typical asynchronous communication interface available as an IC
Transmit
Bidirectional Transmitter Shift data
data bus Bus register register
buffers

Control Transmitter Transmitter

clock
register control

Internal Bus
and clock
Chip select
CS
Register select Status Receiver Receiver CS RS Oper. Register selected
RS Timing clock
register control 0 x x None
I/O read and and clock 1 0 WR Transmitter register
RD Control 1 1 WR Control register
I/O write Receive 1 0 RD Receiver register
WR Receiver Shift data
1 1 RD Status register
register register

G.SWARNALATHA,Asst.Professor, GNITC
 Asynchronous Data Transfer

UNIT-IV
UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER
- UART -
Transmitter Register
 Accepts a data byte(from CPU) through the data bus
 Transferred to a shift register for serial transmission
Receiver
 Receives serial information into another shift register
 Complete data byte is sent to the receiver register
Status Register Bits
 Used for I/O flags and for recording errors
Control Register Bits
 Define baud rate, no. of bits in each character, whether
to generate and check parity, and no. of stop bits

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UNIT-IV
Asynchronous Data Transfer

FIRST-IN-FIRST-OUT(FIFO) BUFFER
* Input data and output data at two different rates
* Output data are always in the same order in which the data entered the buffer.
* Useful in some applications when data is transferred asynchronously
4 x 4 FIFO Buffer (4 4-bit registers Ri),
4 Control Registers(flip-flops Fi, associated with each Ri)

R1 R2 R3 R4

Data 4-bit 4-bit 4-bit 4-bit Data

input register register register register output

Clock Clock Clock Clock

Insert

S F1 S F2 S F3 S F4
Output
F'4 ready
R F'1 R F'
F2 R F'3 R

Input ready Delete

Master clear
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UNIT-IVMODES OF TRANSFER - PROGRAM-CONTROLLED I/O
Modes of Transfer

3 different Data Transfer Modes between the central

computer(CPU or Memory) and peripherals; Program-Controlled I/O
Interrupt-Initiated I/O
Program-Controlled I/O(Input Dev to CPU) Direct Memory Access (DMA)

Data bus Interface I/O bus

Address bus Data register
Data valid I/O
CPU I/O read device
I/O write Status Data accepted
register F

Read status register

Check flag bit

=0 Polling or Status Checking

flag
=1 • Continuous CPU involvement
• CPU slowed down to I/O speed
Read data register
Transfer data to memory • Simple
• Least hardware
no Operation
complete?
yes
Continue with
program
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UNIT-IVMODES OF TRANSFER - INTERRUPT INITIATED I/O & DMA
Modes of Transfer

Interrupt Initiated I/O

- Polling takes valuable CPU time
- Open communication only when some data has
to be passed -> Interrupt.
- I/O interface, instead of the CPU, monitors the I/O device
- When the interface determines that the I/O device is
ready for data transfer, it generates an Interrupt Request to the CPU
- Upon detecting an interrupt, CPU stops momentarily
the task it is doing, branches to the service routine
to process the data transfer, and then returns to the
task it was performing
DMA (Direct Memory Access)
- Large blocks of data transferred at a high speed to
or from high speed devices, magnetic drums, disks, tapes, etc.
- DMA controller
Interface that provides I/O transfer of data directly
to and from the memory and the I/O device
- CPU initializes the DMA controller by sending a
memory address and the number of words to be transferred
- Actual transfer of data is done directly between
the device and memory through DMA controller
-> Freeing CPU for other tasks
G.SWARNALATHA,Asst.Professor, GNITC
 Priority Interrupt

UNIT-IV PRIORITY INTERRUPT

Priority
- Determines which interrupt is to be served first
when two or more requests are made simultaneously
- Also determines which interrupts are permitted to
interrupt the computer while another is being serviced
- Higher priority interrupts can make requests while
servicing a lower priority interrupt

Priority Interrupt by Software(Polling)

- Priority is established by the order of polling the devices(interrupt sources)
- Flexible since it is established by software
- Low cost since it needs a very little hardware
- Disadvantage: If there are many interrupts ,the time required to poll them is
exceed the time available to service the I/O device.
- Very slow

G.SWARNALATHA,Asst.Professor, GNITC
 Priority Interrupt

UNIT-IV
PRIORITY INTERRUPT

Priority Interrupt by Hardware

 Require a priority interrupt manager which accepts
all the interrupt requests to determine the highest priority request
 Fast since identification of the highest priority
interrupt request is identified by the hardware
 Fast since each interrupt source has its own interrupt vector to access
directly to its own service routine

G.SWARNALATHA,Asst.Professor, GNITC
 Priority Interrupt

UNIT-IV
HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -
Interrupt Request from any device(>=1)
-> CPU responds by INTACK <- 1
-> Any device receives signal(INTACK) 1 at PI puts the VAD on the bus
Among interrupt requesting devices the only device which is physically closest
to CPU gets INTACK=1, and it blocks INTACK to propagate to the next device
One stage of the daisy chain priority arrangement
VAD
Priority in Enable
PI
Vector address

Interrupt RF Priority out

request PO PI RF PO Enable
S Q
from device 0 0 0 0
0 1 0 0
R 1 0 1 0
1 1 1 1
Delay

Interrupt request to CPU

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 Priority Interrupt

UNIT-IV PARALLEL PRIORITY INTERRUPT

Interrupt register Bus
Buffer
Disk 0 I0 y
Printer 1 I1 x
Priority 0
Reader 2 I 2 encoder
0 VAD
Keyboard 3 0 to CPU
I3
0
0
0 IEN IST
0
Mask
register 1 Enable

2
Interrupt
to CPU
3
INTACK
from CPU

IEN: Set or Clear by instructions ION or IOF

IST: Represents an unmasked interrupt has occurred. INTACK enables
tristate Bus Buffer to load VAD generated by the Priority Logic

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 Priority Interrupt

UNIT-IV
PARALLEL PRIORITY INTERRUPT
Interrupt Register:
 Each bit is associated with an Interrupt Request from different
Interrupt Source - different priority level
 Each bit can be cleared by a program instruction

Mask Register:
 Mask Register is associated with Interrupt Register
 Each bit can be set or cleared by an Instruction

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 Priority Interrupt

UNIT-IV
INTERRUPT PRIORITY ENCODER
Determines the highest priority interrupt whenmore than one
interrupts take place

Priority Encoder Truth table

Inputs Outputs
I0 I1 I2 I3 x y IST Boolean functions
1 d d d 0 0 1
0 1 d d 0 1 1
0 0 1 d 1 0 1 x = I 0' I 1'
0 0 0 1 1 1 1 y = I 0' I 1 + I 0’ I 2’
0 0 0 0 d d 0 (IST) = I0 + I1 + I2 + I3

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 Priority Interrupt

UNIT-IV INTERRUPT CYCLE

 At the end of each Instruction cycle

- CPU checks IEN and IST
- If IEN  IST = 1, CPU -> Interrupt Cycle

 SP SP - 1 Decrement stack pointer

 M[SP]  PC Push PC into stack
 INTACK  1 Enable interrupt acknowledge
 PC  VAD Transfer vector address to PC
 IEN  0 Disable further interrupts
 Go To Fetch to execute the first instruction
in the interrupt service routine

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 Priority Interrupt
UNIT-IV INTERRUPT SERVICE ROUTINE
address Memory I/O service programs
7
0 JMP DISK DISK Program to service
1 JMP PTR magnetic disk
VAD=00000011 3
2 JMP RDR PTR Program to service
3 JMP KBD line printer
8
1 Main program RDR
KBD Program to service
749 current instr.
interrupt 750 character reader
4
KBD Program to service
Stack
11 keyboard
5
2 255
256 Disk 256
750 interrupt
6 9 10

Initial and Final Operations:-

 Each interrupt service routine must have an initial and final set of
operations for controlling the registers in the hardware interrupt
system

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 Priority Interrupt
UNIT-IV
INTERRUPT SERVICE ROUTINE
Initial Sequence:-
[1] Clear lower level Mask reg. bits
[2] IST <- 0
[3] Save contents of CPU registers
[4] IEN <- 1
[5] Go to Interrupt Service Routine

Final Sequence
[1] IEN <- 0
[2] Restore CPU registers
[3] Clear the bit in the Interrupt Reg
[4] Set lower level Mask reg. bits
[5] Restore return address, IEN <- 1

G.SWARNALATHA,Asst.Professor, GNITC
 Direct Memory Access
UNIT-IV DIRECT MEMORY ACCESS
* Block of data transfer from high speed devices, Drum, Disk, Tape
* DMA controller - Interface which allows I/O transfer directly between
Memory and Device, freeing CPU for other tasks
* CPU initializes DMA Controller by sending memory
address and the block size(number of words)
CPU bus signals for DMA transfer


ABUS Address bus High-impedence
Bus request BR DBUS Data bus (disabled)
CPU when BG is
Bus granted BG RD Read
WR Write enabled

Block diagram of DMA controller

Address bus

Data bus Data bus Address bus

buffers buffers
Internal Bus

DMA select DS Address register

Register select RS
Read RD Word count register
Write WR Control
logic
Bus request BR Control register

Bus grant BG
Interrupt Interrupt DMA request
DMA acknowledge to I/O device

G.SWARNALATHA,Asst.Professor, GNITC
 Direct Memory Access
UNIT-IV DMA I/O OPERATION

Starting an I/O
- CPU executes instruction to
Load Memory Address Register
Load Word Counter
Load Function(Read or Write) to be performed
Issue a GO command

Upon receiving a GO Command DMA performs I/O

operation as follows independently from CPU

Input
[1] Input Device <- R (Read control signal)
[2] Buffer(DMA Controller) <- Input Byte; and
assembles the byte into a word until word is full
[4] M <- memory address, W(Write control signal)
[5] Address Reg <- Address Reg +1; WC(Word Counter) <- WC - 1
[6] If WC = 0, then Interrupt to acknowledge done, else go to [1]

G.SWARNALATHA,Asst.Professor, GNITC
 Direct Memory Access

UNIT-IV
DMA I/O OPERATION

Output
[1] M <- M Address, R M Address R <- M Address R + 1,
WC <- WC - 1
[2] Disassemble the word
[3] Buffer <- One byte; Output Device <- W, for all
disassembled bytes
[4] If WC = 0, then Interrupt to acknowledge done, else go to [1]

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 Direct Memory Access
UNIT-IV CYCLE STEALING

While DMA I/O takes place, CPU is also executing instructions

DMA Controller and CPU both access Memory -> Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access

- Priority System

Memory accesses by CPU and DMA Controller are interwoven,

with the top priority given to DMA Controller
-> Cycle Stealing

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UNIT-IV
Direct Memory Access

CYCLE STEALING

Cycle Steal:-

- CPU is usually much faster than I/O(DMA), thus

CPU uses the most of the memory cycles
- DMA Controller steals the memory cycles from CPU
- For those stolen cycles, CPU remains idle
- For those slow CPU, DMA Controller may steal most of the
memory cycles which may cause CPU remain idle long time

G.SWARNALATHA,Asst.Professor, GNITC
UNIT-IV
Direct Memory Access

DMA TRANSFER

Interrupt
Random-access
BG
CPU memory unit (RAM)
BR
RD WR Addr Data RD WR Addr Data
Read control
Write control
Data bus
Address bus

Address
select

RD WR Addr Data
DS DMA ack.

RS DMA I/O
Controller Peripheral
BR device
BG DMA request
Interrupt

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 Input/Output Processor

INPUT/OUTPUT PROCESSOR - CHANNEL -

Channel

- Processor with direct memory access capability

that communicates with I/O devices
- Channel accesses memory by cycle stealing
- Channel can execute a Channel Program
- Stored in the main memory
- Consists of Channel Command Word(CCW)
- Each CCW specifies the parameters needed
by the channel to control the I/O devices and
perform data transfer operations
- CPU initiates the channel by executing an
channel I/O class instruction and once initiated,
channel operates independently of the CPU
Central
processing
unit (CPU)
Memory Bus

Peripheral devices
Memory
unit PD PD PD PD

Input-output
processor
(IOP) I/O bus
 Input/Output Processor

UNIT-IV CHANNEL / CPU COMMUNICATION

CPU operations IOP operations
Send instruction
to test IOP.path
Transfer status word
to memory
If status OK, then send
start I/O instruction
to IOP. Access memory
for IOP program

CPU continues with

another program Conduct I/O transfers
using DMA;
Prepare status report.

I/O transfer completed;

Interrupt CPU
Request IOP status

Transfer status word

Check status word to memory location
for correct transfer.

Continue

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UNIT-IV
MEMORY HIERARCHY

MEMORY HIERARCHY

The memory hierarchy in computer architecture refers to the arrangement of

different types of memory in a system, organized in a hierarchy based on
their speed, capacity, and proximity to the CPU. The main goal of the memory
hierarchy is to bridge the gap between the fast but small and expensive CPU
registers and the slower but larger and cheaper main memory (RAM) and
secondary storage (like hard drives or SSDs).
Here's a typical memory hierarchy, from fastest and smallest to slowest and
largest

1.CPU Registers: These are the fastest storage locations within the CPU itself.
Registers hold data that the CPU is currently processing. They have the
smallest capacity and are the most expensive in terms of hardware.
2.Cache Memory: Cache memory sits between the CPU registers and the main
memory. It's faster than main memory but slower than registers. Cache
memory is typically divided into several levels (L1, L2, L3) based on proximity
to the CPU and size. The caches store frequently accessed data and
instructions to reduce the time needed to access them

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 MEMORY HIERARCHY

UNIT-IV MEMORY HIERARCHY

3.Main Memory (RAM): This is the primary memory of a computer system where
data and instructions are stored temporarily for processing by the CPU. It is
slower than cache memory but larger in size. RAM is volatile, meaning it loses
its contents when the power is turned off.
4.Secondary Storage: This includes hard disk drives (HDDs), solid-state drives
(SSDs), and other forms of non-volatile storage. Secondary storage devices
have much larger capacities compared to RAM but are slower in terms of
access time. They are used for long-term storage of data and programs even
when the power is turned off.
The memory hierarchy is designed to exploit the principle of locality, which
states that programs tend to access a relatively small portion of their address
space at any given time. By placing frequently accessed data and instructions
in faster, smaller storage closer to the CPU, the memory hierarchy helps
improve overall system performance. Cache management techniques, such as
caching algorithms and prefetching, play a crucial role in optimizing the
performance of the memory hierarchy.

G.SWARNALATHA,Asst.Professor, GNITC
 MEMORY HIERARCHY

UNIT-IV MEMORY HIERARCHY

This hierarchical arrangement optimizes memory access by placing frequently

accessed data and instructions in faster, smaller memory units closer to the
CPU, while less frequently accessed data resides in larger but slower memory
units

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 MAIN MEMORY

UNIT-IV MAIN MEMORY

RAM and ROM Chips
Typical RAM chip

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 Main Memory

UNIT-IV MAIN MEMORY

MEMORY ADDRESS MAP

Address space assignment to each memory chip

Example: 512 bytes RAM and 512 bytes ROM

Hexa Address bus
Component address 10 9 8 7 6 5 4 3 2 1
RAM 1 0000 - 007F 0 0 0 x x x x x x x
RAM 2 0080 - 00FF 0 0 1 x x x x x x x
RAM 3 0100 - 017F 0 1 0 x x x x x x x
RAM 4 0180 - 01FF 0 1 1 x x x x x x x
ROM 0200 - 03FF 1 x x x x x x x x x

G.SWARNALATHA,Asst.Professor, GNITC
 Main Memory

UNIT-IV MEMORY ADDRESS MAP

Memory Connection to CPU

- RAM and ROM chips are connected to a CPU
through the data and address buses

- The low-order lines in the address bus select

the byte within the chips and other lines in the
address bus select a particular chip through
its chip select inputs

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 Main Memory

UNIT-IV CONNECTION OF MEMORY TO CPU

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 Auxiliary Memory

UNIT-IV AUXILIARY MEMORY

Information Organization on Magnetic Tapes

file i
block 1 block 2
block 3 EOF
R1
R2 R3 R4
R5
R6
block 3 IRG
R1
EOF R3 R2
R5 R4 block 1
block 2

Organization of Disk Hardware

Moving Head Disk Fixed Head Disk

Track

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 Associative Memory

UNIT-IV ASSOCIATIVE MEMORY

- Accessed by the content of the data rather than by an address
- Also called Content Addressable Memory (CAM)
Hardware Organization

- Compare each word in CAM in parallel with the content of A(Argument Register)
- If CAM Word[i] = A, M(i) = 1
- Read sequentially accessing CAM for CAM Word(i) for M(i) = 1
- K(Key Register) provides a mask for choosing a
particular field or key in the argument in A
(only those bits in the argument that have 1’s in
their corresponding position of K are compared)

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 Associative Memory

UNIT-IV ORGANIZATION OF CAM

Internal organization of a typical cell Cij

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 Associative Memory

UNIT-IV MATCH LOGIC

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 Cache Memory

UNIT-IV CACHE MEMORY

Locality of Reference
- The references to memory at any given time interval tend to be
confined within a localized areas
- This area contains a set of information and the membership changes
gradually as time goes by
- Temporal Locality
The information which will be used in near future is likely to be in
use already( e.g. Reuse of information in loops)
- Spatial Locality
If a word is accessed, adjacent(near) words are likely accessed soon
(e.g. Related data items (arrays) are usually stored together;
instructions are executed sequentially)
Cache
- The property of Locality of Reference makes the Cache memory
systems work
- Cache is a fast small capacity memory that should hold those
information which are most likely to be accessed

G.SWARNALATHA,Asst.Professor, GNITC
 Cache Memory

UNIT-IV CACHE MEMORY

Main memory CPU

Cache memory

PERFORMANCE OF CACHE
Memory Access
All the memory accesses are directed first to Cache
If the word is in Cache; Access cache to provide it to CPU
If the word is not in Cache; Bring a block (or a line)
including
that word to replace a block now in Cache

- How can we know if the word that is required

is there ?
- If a new block is to replace one of the old blocks,
which one should we choose ?
G.SWARNALATHA,Asst.Professor, GNITC
 Cache Memory

UNIT-IV
PERFORMANCE OF CACHE

Performance of Cache Memory System

Hit Ratio - % of memory accesses satisfied by Cache memory system

Te: Effective memory access time in Cache memory system
Tc: Cache access time
Tm: Main memory access time

Te = Tc + (1 - h) Tm

Example: Tc = 0.4 s, Tm = 1.2s, h = 0.85%

Te = 0.4 + (1 - 0.85) * 1.2 = 0.58s

G.SWARNALATHA,Asst.Professor, GNITC
 Cache Memory

UNIT-IV MEMORY AND CACHE MAPPING - ASSOCIATIVE MAPPLING -

Mapping Function Specification of correspondence between main memory
blocks and cache blocks
 Associative mapping
 Direct mapping
 Set-associative mapping
Associative Mapping
- Any block location in Cache can store any block in memory
-> Most flexible
- Mapping Table is implemented in an associative memory
-> Fast, very Expensive
- Mapping Table
Stores both address and the content of the memory word

G.SWARNALATHA,Asst.Professor, GNITC
 Cache Memory

UNIT-IV MEMORY AND CACHE MAPPING - DIRECT MAPPING -

- Each memory block has only one place to load in Cache
- Mapping Table is made of RAM instead of CAM
- n-bit memory address consists of 2 parts; k bits of Index field and n-k bits of
Tag field
- n-bit addresses are used to access main memory and k-bit Index is used to
access the Cache
Addressing Relationships

G.SWARNALATHA,Asst.Professor, GNITC
 Cache Memory

UNIT-IV MEMORY AND CACHE MAPPING - DIRECT MAPPING -

Direct Mapping Cache Organization

G.SWARNALATHA,Asst.Professor, GNITC
 Cache Memory

UNIT-IV DIRECT MAPPING

Operation

- CPU generates a memory request with (TAG;INDEX)

- Access Cache using INDEX ; (tag; data)
Compare TAG and tag
- If matches -> Hit
Provide Cache[INDEX](data) to CPU
- If not match -> Miss
M[tag;INDEX] <- Cache[INDEX](data)
Cache[INDEX] <- (TAG;M[TAG; INDEX])
CPU <- Cache[INDEX](data)
Direct Mapping with block size of 8 words

G.SWARNALATHA,Asst.Professor, GNITC
 Cache Memory

UNIT-IV
MEMORY AND CACHE MAPPING - SET ASSOCIATIVE MAPPING -
- Each memory block has a set of locations in the Cache to load
Set Associative Mapping Cache with set size of two

Operation
- CPU generates a memory address(TAG; INDEX)
- Access Cache with INDEX, (Cache word = (tag 0, data 0); (tag 1,
data 1))
- Compare TAG and tag 0 and then tag 1
- If tag i = TAG -> Hit, CPU <- data i
- If tag i  TAG -> Miss,
Replace either (tag 0, data 0) or (tag 1, data 1),
Assume (tag 0, data 0) is selected for replacement,
(Why (tag 0, data 0) instead of (tag 1, data 1) ?)
M[tag 0, INDEX] <- Cache[INDEX](data 0)
Cache[INDEX](tag 0, data 0) <- (TAG, M[TAG,INDEX]),
CPU <- Cache[INDEX](data 0)
G.SWARNALATHA,Asst.Professor, GNITC
 Cache Memory

UNIT-IV BLOCK REPLACEMENT POLICY

Many different block replacement policies are available

LRU(Least Recently Used) is most easy to implement
Cache word = (tag 0, data 0, U0);(tag 1, data 1, U1), Ui = 0 or 1(binary)
Implementation of LRU in the Set Associative Mapping with set size = 2
Modifications
Initially all U0 = U1 = 1
When Hit to (tag 0, data 0, U0), U1 <- 1(least recently used)
(When Hit to (tag 1, data 1, U1), U0 <- 1(least recently used))
When Miss, find the least recently used one(Ui=1)
If U0 = 1, and U1 = 0, then replace (tag 0, data 0)
M[tag 0, INDEX] <- Cache[INDEX](data 0)
Cache[INDEX](tag 0, data 0, U0) <- (TAG,M[TAG,INDEX], 0); U1 <- 1
If U0 = 0, and U1 = 1, then replace (tag 1, data 1)
Similar to above; U0 <- 1
If U0 = U1 = 0, this condition does not exist
If U0 = U1 = 1, Both of them are candidates,
Take arbitrary selection

G.SWARNALATHA,Asst.Professor, GNITC
 Cache Memory

UNIT-IV CACHE WRITE

Write Through
When writing into memory
If Hit, both Cache and memory is written in parallel
If Miss, Memory is written
For a read miss, missing block may be
overloaded onto a cache block
Memory is always updated
-> Important when CPU and DMA I/O are both executing
Slow, due to the memory access time
Write-Back (Copy-Back)
When writing into memory
If Hit, only Cache is written
If Miss, missing block is brought to Cache and write into Cache
For a read miss, candidate block must be
written back to the memory
Memory is not up-to-date, i.e., the same item in
Cache and memory may have different value

G.SWARNALATHA,Asst.Professor, GNITC