Computer Organization and

Architecture
UNIT - II
List of Topics :
• Instruction Codes
• Computer Registers
• Computer Instructions
• Timing and Control
• Instruction Cycle
• Memory Reference Instructions
• Input-Output and Interrupt
• Complete Computer Description
• Design of Basic Computer
• Design of Accumulator Logic G.Swarnalatha, Asst.Professor, GNITC
 II INTRODUCTION
• Every different processor type has its own design (different registers, buses,
microoperations, machine instructions, etc)
• Modern processor is a very complex device
• It contains
• Many registers
• Multiple arithmetic units, for both integer and floating point calculations
• The ability to pipeline several consecutive instructions to speed execution Etc.
• However, to understand how processors work, we will start with a simplified processor
model
• This is similar to what real processors were like ~25 years ago
• M. Morris Mano introduces a simple processor model he calls the Basic Computer
• We will use this to introduce processor organization and the relationship of the RTL model
to the higher level computer processor

G.Swarnalatha, Asst.Professor, GNITC

II THE BASIC COMPUTER

G.Swarnalatha, Asst.Professor, GNITC

II INSTRUCTIONS

• Program
• A sequence of (machine) instructions

• (Machine) Instruction
• A group of bits that tell the computer to perform a specific operation (a sequence of micro-
operation)

• The instructions of a program, along with any needed data are stored in
memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the instruction into the
sequence of microoperations necessary to implement it
G.Swarnalatha, Asst.Professor, GNITC
II INSTRUCTION FORMAT

• A computer instruction is often divided into two parts

• An opcode (Operation Code) that specifies the operation for that instruction
• An address that specifies the registers and/or locations in memory to use for that
operation
• In the Basic Computer, since the memory contains 4096 (= 212)
words, we needs 12 bit to specify which memory address this
instruction will use
• In the Basic Computer, bit 15 of the instruction specifies the
addressing mode (0: direct addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits
long, that leaves 3 bits for the instruction’s opcode
G.Swarnalatha, Asst.Professor, GNITC
 II ADDRESSING MODES

• The address field of an instruction can represent either

• Direct address: the address in memory of the data to use (the address of the operand), or
• Indirect address: the address in memory of the address in memory of the data to use

• Effective Address (EA)

• The address, that can be directly used without modification to access an operand for a computation-
type instruction, or as the target address for a branch-type instruction
G.Swarnalatha, Asst.Professor, GNITC
II PROCESSOR REGISTERS

• A processor has many registers to hold instructions, addresses, data, etc

• The processor has a register, the Program Counter (PC) that holds the memory address of
the next instruction to get
• Since the memory in the Basic Computer only has 4096 locations, the PC only needs 12 bits

• In a direct or indirect addressing, the processor needs to keep track of what locations in
memory it is addressing: The Address Register (AR) is used for this
• The AR is a 12 bit register in the Basic Computer

• When an operand is found, using either direct or indirect addressing, it is placed in the
Data Register (DR). The processor then uses this value as data for its operation
• The Basic Computer has a single general purpose register – the Accumulator (AC)

G.Swarnalatha, Asst.Professor, GNITC

II PROCESSOR REGISTERS
• The significance of a general purpose register is that it can be referred to in instructions
• e.g. load AC with the contents of a specific memory location; store the contents of
AC into a specified memory location
• Often a processor will need a scratch register to store intermediate results or other
temporary data; in the Basic Computer this is the Temporary Register (TR)
• The Basic Computer uses a very simple model of input/output (I/O) operations
• Input devices are considered to send 8 bits of character data to the
processor
• The processor can send 8 bits of character data to output devices
• The Input Register (INPR) holds an 8 bit character gotten from an input device
• The Output Register (OUTR) holds an 8 bit character to be send to an output device

G.Swarnalatha, Asst.Professor, GNITC

II BASIC COMPUTER REGISTERS

G.Swarnalatha, Asst.Professor, GNITC

II COMMON BUS SYSTEM

• The registers in the Basic Computer are connected using a bus

• This gives a savings in circuitry over complete connections
between registers

G.Swarnalatha, Asst.Professor, GNITC

II COMMON BUS SYSTEM

G.Swarnalatha, Asst.Professor, GNITC

II COMMON BUS SYSTEM

Rea INPR
Memory d
Write
4096 x E ALU
16 Address

AC

L I C
L I C L
DR IR
L I C L I C
PC TR

AR OUTR LD
L I C
7 1 2 3 4 5 6
16-bit Common Bus

G.Swarnalatha, Asst.Professor, GNITC

II COMMON BUS SYSTEM

• Three control lines, S2, S1, and S0 control which register the bus selects as its input

• Either one of the registers will have its load signal activated, or the memory will have its read signal
activated
• Will determine where the data from the bus gets loaded
• The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the high order 4 bit positions
• When the 8-bit register OUTR is loaded from the bus, the data comes from the low order 8 bits on the
bus

G.Swarnalatha, Asst.Professor, GNITC

II BASIC COMPUTER INSTRUCTIONS

G.Swarnalatha, Asst.Professor, GNITC

II BASIC COMPUTER INSTRUCTIONS

G.Swarnalatha, Asst.Professor, GNITC

II INSTRUCTION SET COMPLETENESS

G.Swarnalatha, Asst.Professor, GNITC

II CONTROL UNIT

• Control unit (CU) of a processor translates from machine instructions to

the control signals for the microoperations that implement them

• Control units are implemented in one of two ways

• Hardwired Control
• CU is made up of sequential and combinational circuits to generate the control signals
• Microprogrammed Control
• A control memory on the processor contains microprograms that activate the necessary control
signals

• We will consider a hardwired implementation of the control unit for the

Basic Computer
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II TIMING AND CONTROL

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II TIMING SIGNALS

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II INSTRUCTION CYCLE

• In Basic Computer, a machine instruction is executed in the following

cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an indirect address
4. Execute the instruction

• After an instruction is executed, the cycle starts again at step 1, for the
next instruction

• Note: Every different processor has its own (different) instruction cycle

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II FETCH and DECODE

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II DETERMINE THE TYPE OF INSTRUCTION

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II REGISTER REFERENCE INSTRUCTIONS

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II MEMORY REFERENCE INSTRUCTIONS

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II MEMORY REFERENCE INSTRUCTIONS

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II MEMORY REFERENCE INSTRUCTIONS

BSA:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

G.Swarnalatha, Asst.Professor, GNITC

II FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS

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II INPUT-OUTPUT AND INTERRUPT

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II PROGRAM CONTROLLED DATA TRANSFER

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II INPUT-OUTPUT INSTRUCTIONS

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II PROGRAM-CONTROLLED INPUT/OUTPUT

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II INTERRUPT INITIATED INPUT/OUTPUT

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II FLOWCHART FOR INTERRUPT CYCLE

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II REGISTER TRANSFER OPERATIONS IN INTERRUPT CYCLE

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II FURTHER QUESTIONS ON INTERRUPT
• How can the CPU recognize the device
• requesting an interrupt ?

• Since different devices are likely to require

• different interrupt service routines, how can
• the CPU obtain the starting address of the
• appropriate routine in each case ?

• Should any device be allowed to interrupt the

• CPU while another interrupt is being serviced ?

• How can the situation be handled when two or

• more interrupt requests occur simultaneously ?

G.Swarnalatha, Asst.Professor, GNITC

 COMPLETE COMPUTER DESCRIPTION
II Flowchart of Operations

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II COMPLETE COMPUTER DESCRIPTION
Microoperations

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II COMPLETE COMPUTER DESCRIPTION
Microoperations

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II DESIGN OF BASIC COMPUTER(BC)

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II CONTROL OF REGISTERS AND MEMORY

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II CONTROL OF FLAGS

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II CONTROL OF COMMON BUS

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II DESIGN OF ACCUMULATOR LOGIC

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II CONTROL OF AC REGISTER

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II ALU (ADDER AND LOGIC CIRCUIT)

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