UNIT 3

MOSFET SCALING
MOSFET SCALING
• MOSFET scaling refers to the process of reducing the size of MOSFET
(Metal-Oxide-Semiconductor Field-Effect Transistor) devices to
increase their density on integrated circuits (ICs).
• This scaling, which has driven advancements in semiconductor
technology for decades, enables
1.improved performance,
2.lower power consumption, and
3.reduced manufacturing costs
Device scaling: Simplified design goals/guidelines
for shrinkingdevice dimensions to achieve density
and performance gains, and power reduction in VLSI
Types of Scaling:

• Constant-Field Scaling: This is the ideal form of scaling where all device
dimensions, including voltage, are reduced proportionally. This keeps the
electric field constant, ensuring device reliability while improving speed
and reducing power.
• Constant-Voltage Scaling: In some cases, it’s difficult to reduce supply
voltage due to threshold voltage requirements. Here, only device
dimensions are reduced, leading to an increase in electric field. This
approach can lead to increased leakage currents and device degradation.
• Generalized Scaling: A compromise where some parameters are scaled
differently, balancing performance, power, and reliability.
1.Constant-Field Scaling
• The principle of constant-field scaling lies in scaling the device voltages and the device dimensions
(both horizontal and vertical) by the same factor, κ(>1), such that the electric field remains unchanged.
• Both horizontal (channel length) and vertical dimensions (e.g., gate oxide thickness, junction depth)
are scaled down by a constant factor K(>1).

• Applied voltages (supply and threshold voltage) are scaled down by 𝐾 to maintain the same electric
Voltage and Doping Adjustments:

field.
• Substrate doping concentration is increased to reduce depletion width, which helps in controlling
short-channel effects (SCEs).
Purpose and Benefits
• Short-Channel Control: Improved SCE suppression by keeping the electric field constant.
• Device Reliability: Avoids increased stress on materials, preserving lifespan.
• Performance & Power: Enables lower power consumption and faster operation due to reduced
capacitance and voltage.
Limitation
• Difficult to sustain as MOSFETs reach submicron scales, leading to alternative scaling methods.
scaling of depletion width
Rules for Constant-Field Scaling
1.Voltage Scaling:
• The voltage applied (V app =−V dd ) scales directly with the scaling factor κ, implying V dd becomes V dd /κ.
• This assumes V dd (the power supply voltage) is much greater than the built-in potential (ϕ bi ).
2.Capacitance Scaling:
• All capacitances, including wiring and gate capacitances, are proportional to the area and inversely
proportional to thickness. If the dimensions are scaled by 1/κ, the capacitances scale by 1/κ.
3.Charge Scaling:
• The total charge per device (C×V) scales as 1/κ 2 , since both the capacitance C) and voltage (V) scale by
1/κ.However, the inversion-layer charge density Qi (per unit gate area) remains unchanged because it depends
on the vertical electric field, which does not change with scaling.
4.Electric Field and Mobility:
• The electric field at any given point is unchanged after scaling. This implies the carrier velocity (v=μ ⋅E),
where μ is the carrier mobility and E is the electric field, remains the same.
• Since the mobility μ depends on the vertical electric field, which is constant, mobility and carrier velocity
remain unchanged.
5.Velocity Saturation Effects:
• Since the electric field and carrier velocity are unchanged, velocity saturation effects will also be similar
between the original and scaled devices.
Diffusion Current:
• The diffusion current arises due to the carrier concentration gradient, governed by Fick's law.
• It is proportional to the diffusion coefficient (D) and the gradient of the inversion charge
density( dQ i /dx).

Scaling Behavior:
• The diffusion current per unit width, given by

scales down by 1/𝜅.

• scales differently. Specifically dQ i /dx is inversely proportional to the channel length (L), which

• Therefore, dQ i /dx scales up by κ, leading to an overall increase in diffusion current by κ.

Implication:
• Unlike drift current, the diffusion current does not scale down with device miniaturization. This
disparity becomes critical in subthreshold regions, where the diffusion current dominates.
• As a result, subthreshold leakage currents do not scale down proportionally, posing a challenge in
low-power, highly scaled devices.
Rules of Constant Field Scaling
MOSFET Device and Circuit Multiplicative Factor (κ> 1)
Parameters
Scaling assumptions Device dimensions (tox,L, 1/κ
W,xj)Doping concentration κ
(Na,Nd) 1/κ
Voltage (V)

Derived scaling Electric field (E) 1

behavior of device Carrier velocity (v) 1
parameters Depletion layer width (Wd) 1/κ
Capacitance (C = εA/t) 1/κ
Inversion layer charge density (Qi 1
Current, drift (I) 1/κ
Channel resistance (Rch) 1

Derived scaling Circuit delay time (τ∼CV/I) 1/κ

behavior of circuit Power dissipation per circuit 1/κ2
parameters (P∼VI) 1/κ3
Power-delay product per circuit κ2
(P×τ) 1
Circuit density (∝1/A)
Power density (P/A)
Effect of Scaling on Circuit
Parameters
Active Channel Resistance:
• The active channel resistance (R) remains unchanged after scaling because both the voltage (V)
and the current (I) scale down by the same factor1/κ:R= IV​.
• The assumption here is that parasitic resistances (e.g., source and drain resistances) are either
negligible or do not scale with the device.
Circuit Delay:
• The circuit delay (τ), which is proportional to RC or CV/I, scales down by 1/κ because:
• Capacitance (C) scales as 1/κ,
• Current (I) and voltage (V) scale as 1/κ.
Conclusion:
• The circuit operates faster by the same scaling factor κ.
Power Dissipation:
• Power dissipation per circuit (P∝VI) scales down by
• 1/κ because both V and 𝐼scale by 1/κ.
Conclusion: Each circuit consumes less power as scaling progresses.
Power Density:
• Circuit density increases by κ 2 , as the area of each circuit decreases by 1/κ 2
• However, the power per circuit decreases by 1/κ, leaving the power density (power per

• Power Density∝Power per circuit×Circuit density∝1/𝜅×𝜅2 = 𝜅.

unit area) unchanged:

Technological Implication:
• Since power density is constant, scaled CMOS devices do not require additional heat-
sinking, in contrast to bipolar devices, which often require elaborate thermal
management.
Power-Delay Product:
• The power-delay product (P×τ), a key measure of energy efficiency, improves

• Power-Delay Product∝𝑃×𝜏∝1/ 𝜅×1/𝜅=1/𝜅2.

dramatically:

• This reflects a significant improvement in energy efficiency, making scaled CMOS circuits
much more power-efficient.
 Threshold Voltage
Threshold Voltage and Scaling:
• The threshold voltage (V t​) is assumed to scale proportionally to the scaling factor (𝜅) and the power-supply
voltage. However, material parameters like the energy gap and work function remain constant, meaning
• V t does not inherently scale unless adjusted.
• Threshold Voltage Equation:

• The substrate bias voltage (V bs ) significantly impacts scaling.

• In n-channel MOSFETs, the first two terms (V fb +2ψ B ) can be approximately -0.15 V, which is negligible.
Scaling Adjustments:
• By adjusting V bs​, the term 2ψ B −V bs can scale down with κ, enabling V t to scale accordingly.
• In early technologies, V bs​ was often reduced to zero for logic applications. Forward biasing V bs​ (to further
scale 2ψ B −V bs ) is rare and mostly experimental.
Nonuniform Doping:
• Nonuniform doping profiles are used in practice to adjust V t​ for scaled devices, improving compatibility
with scaling requirements.
P-Channel MOSFET Challenges:
• P-channel MOSFETs with p +-polysilicon gates scale similarly to n-channel devices.
• However, in buried-channel devices (e.g., with n +-polysilicon gates),
 2.Generalized Scaling
Limitations of Constant-Field Scaling:
• Constant-field scaling requires both device dimensions and supply voltage to scale by the same
factor, but this approach is often impractical.
• Due to subthreshold nonscaling and the preference to maintain standardized voltage levels,
supply voltage (V DD ) is rarely scaled in proportion to the channel length.
• Historical Trends:
• Data in Table shows that the oxide field has increased across CMOS VLSI generations, deviating
from constant-field scaling principles.
Generalized Scaling: Generalized
Scaling
• Introduced by Baccarani et al. (1984), generalized scaling allows both vertical and lateral electric fields to scale by the same
multiplication factor.
• This approach preserves the electric field pattern, minimizing 2D effects like short-channel effects during scaling.
Challenges of Higher Electric Fields:
• Increased electric fields improve performance but pose reliability concerns, such as hot carrier degradation and dielectric
breakdown
Sub-0.1 µm Design Constraints:
• Below 0.1 µm feature sizes, power limitations dominate the design space, with significant trade-offs between performance
and power efficiency.
• This generalized scaling approach allows flexibility in designing smaller, more efficient CMOS devices while addressing real-
world constraints.
Rules for Generalized Scaling

• Generalized scaling allows higher electric fields to improve performance but at the cost of increased power
density and thermal management challenges. It requires precise control of doping and field patterns to
minimize short-channel effects while balancing power and delay trade-offs.
3.Constant-Voltage Scaling
Nonscaling Effects
• constant-field scaling provides a basic framework for shrinking CMOS
devices to gain higher density and speed without degrading reliability
and power, there are several factors that scale neither with the
physical dimensions nor with the operating voltage.
•
 Primary Nonscaling Factors
• The primary reason for the nonscaling effects is that neither the thermal
voltage kT/q nor the silicon bandgap Eg changes with scaling.
1.subthreshold nonscaling
( i.e., the thresholdvoltage cannot be scaled down like other parameters)
the voltage level cannot be scaled down as much asthe linear
dimensions, and the electric field has increased as a result.
2.built-in potential,
3.depletion-layer width, and
4.short-channel effect
• To compensate for these effects, the doping concentration must increase
more than that suggested by constant-field scaling or generalized scaling
• Threshold Voltage Scaling and Off Current:
The exponential relationship between threshold voltage (V t) and subthreshold current (I off​) limits
how much V t can be reduced.

are scaled by 𝜅
• Even if V t is held constant, the off current increases by a factor of κ when physical dimensions

• This limitation becomes critical for dynamic circuits and RAM, as lower V t​ leads to higher power
consumption.
Impact on Power-Supply Voltage:
• The threshold voltage sets a lower limit for the power-supply voltage (V dd​) because circuit delay
depends heavily on the ratio V t​/V dd​. A reduced V dd​would significantly degrade performance.
Inversion-Layer Thickness and Capacitance:
• The inversion-layer thickness, unaffected by constant-field scaling, contributes to a reduced total
gate capacitance per unit area.
• This series combination of the inversion and oxide capacitance increases by a factor less thanκ,
degrading inversion charge density and reducing current at low gate voltages
Depletion Region and Short-Channel Effects:
• Junction built-in potential and surface potential remain in the range of 0.6–1.0 V,
relatively constant with scaling.
• Consequently, depletion-region widths do not scale proportionally to device
dimensions.
• This mismatch exacerbates short-channel effects in scaled MOSFETs, a
Doping Requirements:
• To mitigate short-channel effects and manage increased off current, the doping
concentration must be increased beyond what is suggested by constant-field or
generalized scaling.
Conclusion:
• Threshold voltage scaling imposes inherent trade-offs in dynamic performance, power
dissipation, and short-channel control. Limitations such as increased off current,
inversion-layer thickness effects, and unchanged depletion region scaling challenge the
effective scaling of V t and V dd
• These constraints necessitate adjustments in doping and design strategies to maintain
performance and reduce power in scaled MOSFETs.
Secondary Nonscaling Factors
• mobility decreases with increasing electric field
Mobility Degradation:
• Electric Field Dependence: Carrier mobility decreases with increasing electric field, as described
by the relation ∝eff∝ 𝐸 −1/3, where E represents the field intensity. Beyond 𝐸=5×105 V/cmE=5×10 5
V/cm, mobility decreases even faster due to surface roughness scattering.
• Impact on Device Performance: Reduced mobility limits the current and delay improvements that
scaling would otherwise achieve. The benefits of scaling are closer to those expected under
velocity saturation conditions, as shown in Table 4.3.
Gate Oxide and Channel Doping Adjustments:
• Oxide Thickness Constraints: To mitigate increasing oxide fields and prevent breakdown, the gate
oxide thickness (t ox​) is reduced less than the lateral dimensions (e.g., channel length).
• Increased Channel Doping: Higher doping concentrations are required to control short-channel

triggers changes in subthreshold slope (𝑚≈1+(3tox/𝑊dm)and substrate sensitivity dV t​/d(−V

effects, resulting in reduced gate depletion width (W dm​) relative to t ox​. This adjustment

bs​)=m).
Velocity Saturation Effects:
• With higher fields, devices are pushed further into the velocity-saturated regime, reducing the potential
gains in current and delay. Beyond a certain point, operating at higher fields or voltages provides diminishing
returns.
Reliability and Power Challenges:
• Power Density: The increased electric field raises power density by a factor of 0.2–0.3, adding to thermal
management burdens.
• Reliability Risks: High fields exacerbate problems such as oxide breakdown, channel degradation, and
increased current densities. Electromigration in interconnects, particularly aluminum lines, worsens due to
higher current densities, compounding reliability issues already seen in constant-field scaling.
Conclusion
• While generalized scaling offers greater flexibility compared to constant-field scaling, it introduces complex
trade-offs. The degradation in mobility, rising power density, and reliability concerns highlight the challenges
of designing smaller, faster, and more efficient MOSFETs. These effects emphasize the importance of
innovative material, structural, and design solutions to sustain progress in semiconductor technology.
Other Nonscaling Factors
• One kind of nonscaling effect is related to the gate and source-drain doping
levels. If not properly scaled up, they may lead to gate depletion and sourcedrain
series resistance problems
• Doping-Related Nonscaling Effects:
• Gate Depletion:Gate polysilicon depletion adds a capacitance 𝐶𝑝 in series with
oxide capacitance C ox
• To maintain scaling consistency, gate doping concentration (N p ) must scale up
proportionally:
• By κ in constant-field scaling.
• By ακ in generalized scaling.
• In practice, achieving such high doping concentrations is limited by solid
solubility, leading to reduced gate capacitance scaling, degradation of inversion
charge density, and lower transconductance.
Source-Drain Doping and Resistance:
• Scaling down junction depths and increasing source-drain doping levels is challenging due to abrupt profile
requirements.
• Source-drain series resistance does not scale proportionally with channel resistance, making parasitic
resistance a larger fraction of the total resistance and reducing current drive.
Process Tolerances:
• Process tolerances must scale down proportionally with device dimensions to fully realize the benefits of
scaling. Examples include:
Channel length tolerance.
Oxide thickness tolerance.
Threshold voltage tolerance.
• Maintaining tolerances as a constant percentage of the scaled parameter is critical but increasingly difficult
as dimensions shrink to atomic levels (e.g., a few angstroms for channel lengths or gate oxides).
• Tighter tolerances drive up manufacturing complexity and costs, posing challenges for VLSI technology
development.
Conclusion:
• The practical limitations of doping concentration scaling and process tolerances introduce significant
nonscaling effects. These factors degrade device performance and increase manufacturing challenges,
making them key considerations in advanced CMOS scaling strategies.