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FPGA Architecture

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30 views

FPGA Architecture

Uploaded by

Ayan Shaikh
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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FPGA architecture

A simple programmable function


Unprogrammed fusible links
Programmed fusible link
Unprogrammed fusible link
Growing an antifuse
Programmed antifuse links
Internal logic diagram of 4x2 ROM
General structure of PLA
Implement the following design using
PROM

Implementation of Boolean
Function would require
8x2 PROM
Implement full adder using PROM
PLA
Programmable logic array
PLA architecture and table
Gate level diagram of PLA
f 2  x1 x2  x1 x2 x3  x1 x3
Customary diagram for PLA
Implement full adder using PLA
Programmable array logic
PAL
Implement following functions using
PAL
Extra circuit to PAL
Architecture of OLMC
(Output logic macrocell)
Generic array logic
CPLD
CPLD function block and Macrocell
Lay out of typical FPGA
FPGA
LB of FPGA
Simplified CLBs
Summary of programming technologies
Logic realization techniques
•There are two fundamental methods employed
by vendors for the programmable logic blocks
used to form the medium-grained architectures
–MUX (multiplexer) based
–LUT (lookup table) based
Key terms
•Look-up table (LUT): A circuit that implements a combinational
logic function by storing a list of output values that correspond to
all possible input combinations.
•CLB: Configurable Logic Block is the name for programmable
logic block in a FPGA.
•Logic element (LE): A circuit internal to a FPGA used to
implement a logic function as a look-up table.
•Cascade chain: A circuit in a FPGA that allows the input width of
a Boolean function to expand beyond the width of one logic
element.
•Carry chain: A circuit in a FPGA that is optimized for efficient
operation of carry functions between logic elements.
•DCM: Digital clock manager is a very important circuit that offers
various clock management functions in a FPGA.
•Clock trees: Distribution of clock signal lines along the FPGA
architecture.
Generic FPGA architecture
•Contain the following blocks:
–Programmable logic block
–I/O blocks
–Programmable interconnect
•In addition the FPGA has:
–Clock distribution circuit
–Embedded memory blocks
–Special purpose blocks:
•DSP blocks:
•Hardware multipliers, adders and registers
–Embedded microprocessors/microcontrollers
–High-speed serial transceivers
Types of architectures
•Fine grained
–Each programmable logic block can be used to
implement only a very simple function. For example, it
might be possible to configure the block to act as any 3-
input function, such as a primitive logic gate (AND,OR,
NAND, etc.) or a storage element (D-type flip-flop, D-
type latch, etc.).
–fine-grained architectures are said to be particularly
efficient when executing systolic algorithms (functions
that benefit from massively parallel implementations).
–Fine-grained implementations require a relatively large
number of connections into and out of each block
compared to the amount of functionality that can be
supported by those blocks
Types of architectures
•Coarse grained
–In the case of a coarse-grained architecture, each
logic block contains a relatively large amount of
logic compared to their fine-grained counterparts.
For example, a logic block might contain four 4-
input LUTs, four multiplexers, four D-type flip-
flops, and some fast carry logic.
–As the granularity of the blocks increases to
medium-grained and higher, the amount of
connections into the blocks decreases compared to
the amount of functionality they can support.
Logic realization techniques
•There are two fundamental methods employed
by vendors for the programmable logic blocks
used to form the medium-grained architectures
–MUX (multiplexer) based
–LUT (lookup table) based
Implementation of AND gate with MUX

Implementation of Full adder using MUX


Logic module of ACTEL device
LUT based function
2 input LUT
2 input LUT
3 input LUT
Inclusion of FF in FPGA block
Basic block of Xilinx FPGA
Logic cells
Xilinx-CLB/ Altera-LAB
LC Slice CLB
• Fast interconnect between LC
• Slightly slower interconnect between slices
• Followed by interconnect between CLBs
A slice contains two LCs
• Each logic cell’s LUT, MUX, and register have
their own data inputs and outputs; the slice has one
set of clock, clock enable, and set/reset signals
common to both logic cells.
Full adder in 3 input LUT
LB architecture of XC4000 family
Xilinx 7 series
Performance
Zync board
Xilinx 7 series
• Artix 7 family: optimized for lowest cost and lowest
power and is ideally suited for handheld
applications as portable ultrasound machines,
digital camera control and SDR
• Kintex 7 family: provides perfect balance of features
and performance making it ideal for wireless LTE
infrastructure equipment, LED backlit, 3D video
displays, Medical imaging
• Virtex 7 family: highest in system performance
suitable for 400G line cards, 300G bridges,
On chip memory
• 20 to 2360 dual port BRAMs
• One Block RAM =36kbits configurable memory
• Portable data width
– Each port can be configured as 32kx1, 16kx2, 8kx4, 4kx8,
2kx16, 1kx36(32), 512x72(64)
– Each BRAM can be divided into two completely
independent 18k bits block RAMs
– Each configurable to any aspect ratio from 18kx1 to
512x32
– Two adjacent 36kbits BRAM can be configured as one
cascaded 64kx1 dual port RAM
On chip memory contd..
• FIFO controller
– Built in FIFO
– Increments the internal addresses
– Provides four handshaking modes as full, empty,
almost full, almost empty
– FIFO width and depth are programmable
Digital Signal Processing in series 7
• Dedicated full custom low power DSP slices
– Consists of dedicated 25x18 bit 2’s complement
multiplier and 48 bit accumulator
– SIMD arithmetic unit
Clocking
– Mixed mode clock manager
– PLL
• Both serve as frequency synthesizer
link
• https://www.eetimes.com/document.asp?
doc_id=1278724

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