Chapter 8

Memory Management Strategies

1
 Objectives and Outline

Objectives Outline
• Describe ways of organizing memory • Background
hardware – Address space
• discuss various memory-management – Logical address space
techniques, including paging and – MMU
segmentation
• Contiguous Memory Allocation
• Description of the Intel Pentium, which
• Paging
supports both pure segmentation and
segmentation with paging – Structure of the Page Table
• Segmentation
• Example: The Intel Pentium

2
 Background

• Program must be brought (from disk) into memory and placed within a
process for it to be run
• Main memory and registers are only storage CPU can access directly
• Register access in one CPU clock (or less)
• Main memory can take many cycles
• Cache sits between main memory and CPU registers
• Protection of memory required to ensure correct operation

3
 Background

Main Memory

CPU cache
instructions
Registers
data Process
program image
in memory

Operating
System
Disk

4
 Program addresses and memory

• When code is generated (or assembly

program is written) we use memory func variable
addresses for variables, functions and
branching/jumping. func variable

• Those addresses can be physical or func variable

logical memory addresses.
main
• In very early systems they are just
physical memory addresses. program
– A program has to be loaded to that
address to run.
– No relocation

5
 Program addresses and memory
physical addresses
RAM of RAM
Assume they are physical addresses
44
40
Program 36
32
Add 12 28
Mov 8 24
… 4 20
Jump 8 0 16
Add 12
Mov 8
… 4
Jump 8 0

6
 Program addresses and memory
physical addresses
RAM of RAM
44
40
36
32
Cmp 28

Program 2
Sub 24
Program 1 Program 2
… 20
Jump 12 16
Add 12 Cmp 12
Add 12
Mov 8 Sub 8 Program 1
Mov 8
… 4 … 4
… 4
Jump 8 0 Jump 12 0
Jump 8 0

7
 Logical address space concept

• We need logical address space

concept, that is different that the RAM
physical RAM (main memory) phy_max
addresses.

• A program uses logical

addresses.
logic_max limit Program
• Set of logical addresses used by
the program is its logical logical
address space base
address Program
– Logical address space can
be, for example, [0, space
max_address]
0
• Logical address space has to be 0
mapped somewhere in physical
memory

8
 Base and Limit Registers

A pair of base and limit registers define the address space of a process
A process should be accessing
and using that range.

Protection and Relocation can be

provided in this way.

also called Relocation Register

Each physical address should be in

range [base, base+limit]

9
 Logical vs. Physical Address Space

• The concept of a logical address space that is bound to a separate physical

address space is central to proper memory management

– Logical address – generated by the CPU; also referred to as virtual

address

– Physical address – address seen by the memory unit

• Logical and physical addresses are the same in compile-time and load-time
address-binding schemes; logical (virtual) and physical addresses differ in
execution-time address-binding scheme

10
 Logical and physical addresses
CPU Main Memory (RAM)
base limit 60
24 32 56
int x 52
PC int y; 48

physical addresses
M[28+base] cmp .. 44
IR mov r1, M[28] mov r1, M[28] 40
M[28+24] mov r2, M[24] 36
M[52] add r1, r2, r3
a relocatable program 32
jmp 16 28
28 int x mov .. 24
logical addresses

24 int y;
20
20 cmp ..
16
16 mov r1, M[28]
12
12 mov r2, M[24]
08
08 add r1, r2, r3
04
04 jmp 16
00
00 mov ..
11
 Memory-Management Unit (MMU)

• Hardware device that maps logical (virtual) to physical address

• In MMU scheme, the value in the relocation register (i.e., base register) is
added to every address generated by a user process at the time it is sent to
memory

• The user program deals with logical addresses; it never sees the real physical
addresses

12
Dynamic relocation using a relocation
register

13
 Binding of Instructions and Data to
Memory
• Address binding of instructions and data to RAM
(physical) memory addresses can happen
at three different stages
– Compile time: If memory location
known a priori, absolute code can be a program
generated; must recompile code if
Program
starting location changes ?
data
– Load time: Must generate relocatable
code if memory location is not known at
compile time instructions
– Execution time: Binding delayed until
run time if the process can be moved
during its execution from one memory
segment to another. Need hardware
support for address maps (e.g., base
and limit registers)

14
Multistep Processing of a User Program

Addresses may be represented in different

ways during these steps

15
 Dynamic Loading

• Routine is not loaded until it is called

• Better memory-space utilization; unused routine is never loaded
• Useful when large amounts of code are needed to handle infrequently
occurring cases
• No special support from the operating system is required, implemented
through program design

16
 Dynamic Linking

• Linking postponed until execution time

• Small piece of code, stub, used to locate the appropriate memory-resident
library routine
• Stub replaces itself with the address of the routine, and executes the routine
• Operating system needed to check if routine is in processes’ memory address
• Dynamic linking is particularly useful for libraries
– Standard C library is shared library that is dynamically linked, not statically
linked.
– You can link statically if you want.
• System also known as shared libraries

17
 Contiguous Memory Allocation
(Dynamic Memory Allocation Problem)

18
 Contiguous Allocation

• Main memory is partitioned usually into two partitions:

– Resident operating system, usually held in low memory with interrupt
vector
– User processes then held in high memory

• Relocation registers used to protect user processes from each other, and from
changing operating-system code and data
– Base register contains value of smallest physical address
– Limit register contains range of logical addresses – each logical address
must be less than the limit register
– MMU maps logical addresses dynamically

19
 Basic Memory Allocation Strategies

• In this chapter, we will cover 3 basic main memory allocation strategies to

processes

– 1) Contiguous allocation

– 2) Paging

– 3) Segmentation

20
Hardware Support for Relocation and Limit
Registers

21
 Contiguous Allocation (Cont)

• Multiple-partition allocation
– Hole – block of available memory; holes of various size are scattered throughout
memory
– When a process arrives, it is allocated memory from a hole large enough to
accommodate it
– Operating system maintains information about:
a) allocated partitions b) free partitions (hole)

OS OS OS OS

process 5 process 5 process 5 process 5

process 9 process 9

process 8 process 10

process 2 process 2 process 2 process 2

22
 Dynamic Storage-Allocation Problem

How to satisfy a request of size n from a list of free holes

• First-fit: Allocate the first hole that is big enough
• Best-fit: Allocate the smallest hole that is big enough; must search
entire list, unless ordered by size
– Produces the smallest leftover hole
• Worst-fit: Allocate the largest hole; must also search entire list
– Produces the largest leftover hole

First-fit and best-fit better than worst-fit in terms of

speed and storage utilization

23
Paging

24
 Fragmentation

• External Fragmentation – total memory space exists to satisfy a request, but

it is not contiguous
• Internal Fragmentation – allocated memory may be slightly larger than
requested memory; this size difference is memory internal to a partition
(allocation), but not being used
• Reduce external fragmentation by compaction
– Shuffle memory contents to place all free memory together in one large
block
– Compaction is possible only if relocation is dynamic, and is done at
execution time
– I/O problem
• Latch job in memory while it is involved in I/O
• Do I/O only into OS buffers

25
 Paging

• Physical address space of a process can be noncontiguous; process is

allocated physical memory whenever the latter is available
– Physical address space will also be noncontiguous.
• Divide physical memory into fixed-sized blocks called frames (size is power
of 2, between 512 bytes and 8,192 bytes)
• Divide logical memory into blocks of same size called pages
• Keep track of all free frames
• To run a program of size n pages, need to find n free frames and load
program
• Set up a page table to translate logical to physical addresses
• Internal fragmentation

26
 Paging
RAM (Physical Memory)
a program
0
0
logical address space
1 a frame
1 (size = 2x)
2
2
3
3
4 physical memory:
4
5 set of fixed sized
5 frames
7
program: set of pages
6
8
Page size = Frame size
9

27
 Paging
RAM
a program
0
0
0 1
1
2 2
2
3
3 load
1 4
4
5
5 0 mapped_to 1
1 mapped_to 4 3 7
2 mapped_to 2 5 6
3 mapped_to 7
4 mapped_to 9 8
5 mapped_to 6 4 9
page table
28
Example

29
 Address Translation Scheme

– Assume Logical Addresses are m bits. Then logical address space

is 2m bytes.
– Assume page size is 2n bytes.

• Logical Address generated by CPU is divided into:

– Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
– Page offset (d) – combined with base address to define the physical
memory address that is sent to the memory unit

page number page offset

p d
(m – n) bits n bits
m bits

30
 Simple example

Assume m is 3 and n is 2

Logical addresses
000 000
001 001 page0
010 010
011 011
100 100
101 101 page1
110 110
111 111

31
Paging Hardware:
address translation

32
 Paging Example

LA = 5
page size = 4 bytes
PA = ?
= 22
5 is 0101
PA = 11001

4 bit logical address

32 byte memory
LA = 11
PA = ?
11 is 1011
PA = 00111

offset
page (dispacement) LA = 13
number inside PA = ?
page
13 is 1101
PA = 01001

33
 Address translation example 1

15 000 0
16 bit logical address 14 000 0
0010000000000100 13 000 0
12 000 0 page size = 4096 bytes
p# offset (offset is 12 bits)
11 111 1
10 000 0
9 101 1
8 000 0
mapping 7 000 0
6 000 0
5 011 1
frame number
4 100 1
valid/invalid bit
f# offset 3 000 1
2 110 1
110 000000000100 1 001 1
15 bit physical address 0 010 1
page table
34
 Address translation example 2

m=3; 23 = 8 logical addresses 2 bits for offset 0000

n=2; page size = 22 = 4 0001 frame 00
0010
000 A 0011
001 B 0100
page 0
010 C 0101
011 D frame 01
0110
100 E 0111
1 bit for page# page 1 101 F 1000 E
110 G 1001 F frame 10
111 H 1010 G
Logical Memory 1011 H
page table 1100 A
0 11 1101 B frame 11
1 10 1110 C
each entry is used to map 1111 D
4 addresses (page size addresses) 2 bits for frame# Physical Memory
35
 Free Frames

OS keeps info
about the frames
in its frame table

Before allocation After allocation

36
 Implementation of Page Table

• Page table is kept in main memory

• Page-table base register (PTBR) points to the page table
• Page-table length register (PTLR) indicates size of the page table
• In this scheme every data/instruction access requires two memory accesses.
One for the page table and one for the data/instruction.

• The two memory access problem can be solved by the use of a special fast-
lookup hardware cache called associative memory or translation look-aside
buffers (TLBs)
• Some TLBs store address-space identifiers (ASIDs) in each TLB entry –
uniquely identifies each process to provide address-space protection for that
process

37
 Implementation of Page Table

RAM
Program Program
CPU
P1 P2
PC

PT1 PT2 Kernel

Memory
PTBR Page Page
Table Table
PTLR of of
P1 P2

Currently running
process is process 1 (P1)
PCB1 PCB2

38
 TLB Associative Memory

• Associative memory – parallel search

Page # Frame #

Address translation (p, d)

– If p is in TLB, get frame # out
– Otherwise get frame # from page table in memory

39
Paging Hardware With TLB

40
 Effective Memory Access Time

• TLB (associative registers) Lookup =  time unit

• Assume memory cycle time is 1 microsecond
• Hit ratio – percentage of times that a page number is found in the
TLB; ratio related to the TLB size
• Hit ratio = 

• Effective Access Time (EAT)

EAT = (1 + )  + (2 + )(1 – )
=2+–

41
 Memory Protection

• Memory protection implemented by associating a protection bit with each page

– Read only page
– Executable page
– Read-write page

• Valid-invalid bit attached to each entry in the page table:

– “valid” indicates that the page is in the process’ logical address space, and
is thus a legal page
– “invalid” indicates that the page is not in the process’ logical address space

42
Valid (v) or Invalid (i) Bit In A Page Table

43
 Page Table Entry Structure

• A typical size of a page table entry can be 32 bits. Depends on the architecture

• Typically we have the following fields in a page table entry.

Referenced Protection bits

bit (read, read-write, execute)

Reserved Page Frame Number

Caching Modified Valid/Invalid

Disabled (Dirty) (Present/Absent)
bit bit bit

44
 Shared Pages

• Shared code
– One copy of read-only (reentrant) code shared among processes (i.e., text
editors, compilers, window systems).
– Shared code must appear in same location in the logical address space of
all processes

• Private code and data

– Each process keeps a separate copy of the code and data
– The pages for the private code and data can appear anywhere in the
logical address space

45
Shared Pages Example

46
Structure of the Page Table
 Structure of the Page Table

• Hierarchical Paging

• Hashed Page Tables

• Inverted Page Tables

48
 Hierarchical Page Tables

• Break up the logical address space into multiple page tables

• A simple technique is a two-level page table

00

01
00
01
10
11
10
PT

11
PT
Log Mem Log Mem

49
Two-Level Paging Scheme

50
 Two-Level Paging Scheme
logical address logical address
offset offset
00
0000 01
0001 10
0010 11
0011
0100 00
0101 01
0110 00 10
0111 01 11
1000 10
1001 11 00
1010 01
1011 10
1100 11
1101
1110
1111 two-level 00
01
single level page table 10
Page table 11

51
 Two-Level Paging Example
• A logical address (on 32-bit machine with 1K page size) is divided into:
– a page number consisting of 22 bits
– a page offset consisting of 10 bits
• Since the page table is paged, the page number is further divided into:
– a 12-bit page number
– a 10-bit page offset
• Thus, a logical address is as follows:

page number page offset

p1 p2 d

where pi is an index into12

10 10
the outer page table, and p2 is the index into the inner page
table

52
Address-Translation Scheme

53
 Example: two level page table need

logical address length = 32 bits

pagesize = 4096 bytes
used 8 MB
logical address division: 10, 10, 12

unused What is total size of two

232 bytes = 4 GB level page
table if entry size
is 4 bytes?
logical address space size
(only partially used)
used 12 MB

54
Example: two level page table need

Each entry of a second

10 10 12 level page table translates
a page# to a frame#;
i.e. each entry maps a page
which is 4096 bytes
210
There are 1024 entries
entries
In a second level page table
210
…… Hence, a second level
entries
page table can map
210 210 * 212 = 222 = 4 MB
Top level entries of logical address space
page table
a second level page
table
55
Example: two level page table need

8 MB 8 MB / 4 MB = 2 second level page

tables required to map
8 MB of logical memory

Total = 3 + 2 = 5 second level

232 bytes = 4 GB page tables required

12 MB / 4 MB = 3 second level page

tables required to map 12 MB
12 MB of logical memory

56
 Example: two level page table need

2nd level page tables

8 MB 210
entries
210
entries 1K * 4Bytes +
5 * 1K * 4Bytes
210 ….
2 bytes
32 unused
= 24 KB
entries 210
= 4 GB space needed
entries
to hold
210 the page
top level
entries tables of the
page table
process
12 MB 210
entries

57
Three-level Paging Scheme

64 bit addresses

58
 Hashed Page Tables

• Common in address spaces > 32 bits

• Page table is a hash table

• A virtual page number is hashed into a page table entry

• A page table entry contains a chain of elements hashing to the same location
– each element = <a virtual page number, frame number>

• Virtual page numbers are compared in this chain searching for a match
– If a match is found, the corresponding physical frame is extracted

59
Hashed Page Table

frame number
virtual page number

60
 Inverted Page Table

• One entry for each real page frame of physical memory

• Entry consists of the page number of the virtual page stored in that real
memory location (frame), with information about the process that owns that
page
– Entry content: <pid, virtual page number>

• Decreases memory needed to store each page table, but increases time
needed to search the table when a page reference occurs

61
Inverted Page Table Architecture

62
Segmentation

63
 Segmentation

• Memory-management scheme that supports user view of memory

• A program is a collection of segments

– A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays

64
User’s View of a Program

65
Logical View of Segmentation

segment 1

4
1

3 2
4

user space physical memory space

66
 Segmentation Architecture

• Logical address consists of a two tuple:

<segment-number, offset>

• Segment table – maps two-dimensional logical addresses; each

table entry has:
– base – contains the starting physical address where the
segments reside in memory
– limit – specifies the length of the segment

• Segment-table base register (STBR) points to the segment table’s

location in memory
• Segment-table length register (STLR) indicates number of
segments used by a program;
segment number s is legal if s < STLR

67
Segmentation Hardware

68
 Segmentation Architecture (Cont.)

• Protection
– With each entry in segment table associate:
• validation bit = 0  illegal segment
• read/write/execute privileges

• Protection bits associated with segments; code sharing occurs at segment level
– Code segment: READONLY; sharable; …
– Data segment: RED-WRITE; not-sharable

• Since segments vary in length, memory allocation is a dynamic storage-allocation

problem

69
Example of Segmentation

70
Intel Pentium
 Example: The Intel Pentium
• Supports both segmentation and segmentation with paging

• CPU generates logical address (<segment#, offset> pairs)

– Given to segmentation unit
• Which produces linear addresses

– Linear address given to paging unit

• Which generates physical address in main memory
• Paging unit forms equivalent of MMU

72
 Logical to Physical Address Translation in
Pentium

SEGMENTATION PAGING
UNIT UNIT

segment s
d

Logical segment page

Memory table table

Linear Logical Memory Physical Memory

73
Logical to Physical Address Translation in Pentium

74
 Intel Pentium Segmentation

base

base+offset

base address limit

75
 Pentium Paging Architecture

• Pentium architecture allows a page size of either 4 KB or 4 MB.

• For 4 KB pages, two-level paging scheme is used in a 32 bit machine

– Address division: <10, 10, 12> bits

• For 4 MB pages, we can skip the inner page tables (secondary page table). A top level
page table entry will point directly to a 4 MB page.

76
Pentium Paging Architecture

77
 Linux on Pentium: Segmentation

• Linux is designed to run on a lot of hardware platforms: Pentium, Arm, Motorola, Sparc,
MIPS, …

• Therefore it does not rely on segmentation and makes minimal use of segmentation in
Pentium.

78
 Linux on Pentium: Paging

• Linux can run both on 32 bit and 64 bit machines.

– Therefore having just two level paging is not enough.
– Linux adapted a three level paging that can be used both in 32bit and 64bit
machines.

• A linear address in Linux is broken into 4 parts:

– P1: global directory
– P2: middle directory
– P3: page table
– P4: offset

• Number of bits in each part depends on the architecture

79
 Linear Address in Linux
Broken into four parts:

• In a 64 bit machine (very large address space), we use all 4 parts

• In a 32 bit Intel machine, that uses two-level paging, we ignore the middle directory (its
size is 0), and use 3 parts.

80
Three-level Paging in Linux

81
 Linux Paging: some kernel structures

struct task_struct
{
…
…
struct mm_struct *mm;
struct mm_struct
} {
the PCB object …
top level
of a process X pgd_t *pgd;
page table
….
of process X
}
(called
mm object
page
of process X
global
(keeps memory
directory)
management
related
information)
82
 References

• The slides here are adapted/modified from the textbook and its slides:
Operating System Concepts, Silberschatz et al., 7th & 8th editions, Wiley.
• Operating System Concepts, 7th and 8th editions, Silberschatz et al. Wiley.
• Modern Operating Systems, Andrew S. Tanenbaum, 3rd edition, 2009.

83
Additional Study Material

84
 Swapping

• A process can be swapped temporarily out of memory to a backing store, and then
brought back into memory for continued execution

• Backing store – fast disk large enough to accommodate copies of all memory images
for all users; must provide direct access to these memory images

• Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-
priority process is swapped out so higher-priority process can be loaded and executed

• Major part of swap time is transfer time; total transfer time is directly proportional to the
amount of memory swapped

• Modified versions of swapping are found on many systems (i.e., UNIX, Linux, and
Windows)
• System maintains a ready queue of ready-to-run processes which have memory images
on disk

85
Schematic View of Swapping

86