Chapter-4

Instruction sets Architecture

• Instruction types
• Instruction cycle
• Instruction formats
• Addressing modes
Instruction Set Architecture
• An instruction is an order given to a computer
processor by a computer program.
• At the lowest level, each instruction is a
sequence of
0s and 1s that describes a physical operation
the computer is to perform (such as "Add").
• Depending on the particular instruction type,
the specification of special storage areas called
registers that may contain data to be used in
carrying out the instruction, or the location in
computer memory of data.
Instruction Set Architecture
• Instruction set is the complete collection of
instructions that are understood by a CPU.
• It has its own structure/formats and elements
• Instruction set architecture is the structure of a
computer that a machine language programmer
must understand to write a correct program for
that machine.
• It is also the machine description that a
hardware designer must understand to design a
correct implementation of the computer.
• It is the set of the instructions that the
Microprocessor/CPU can execute.
Instruction Set Architecture (ISA)

Instruction set is the boundary where the computer designer

and computer programmer see the same computer from
different viewpoints.
From the designer, point of view, the computer instruction set
provides a functional description of a processor, that is :
(i) detailed list of the instructions that a processor is capable
of processing.
(ii) describes of the types/locations/access methods for
operands.
The common goal of computer designer is to build the
hardware for implementing the machine's instructions for
CPU.
Cont….
From the programmer's point of view, the user must
understand machine or assembly language for low-level
programming.
Moreover, the user must be aware of the register set,
instruction types and the function that each instruction
performs.
However, our main focus is the programmer's viewpoint with
the design of instruction set.
Instruction Types
Instructions, of most modern computers, may be
classified into the following groups:
Data transfer: These instructions transfer data
from one location in the computer to another
location without changing the data contents.
The most common transfer are between:
Resister to register.
Memory to register.
Register to memory.
Register to I/O part and vice versa.
Data transfer
Some of data transfer instructions are
Store
Load
Exchange
 move
 push, pop
• Specifies: source and destination (memory,
register, stack), amount of data
• May be different instructions for different (size,
location) movements
Instruction Types
Arithmetic and Logical: These instructions
perform arithmetic and logical operations on
data.
Arithmetic ADD, SUB, DIV, MUL
Logical AND, OR, NOT, SHIFT, ROTATE
INPUT/OUTPUT
• May be specific instructions, e.g. INPUT,
OUTPUT
• May be done using data movement instructions
(memory mapped I/O)
• Program-control
Instruction format
An instruction is normally made up of a combination
of an operation code and some way of specifying
an operand, most commonly by its location
or address in memory though non memory reference
instructions can exist.
Some operation codes deal with more than one
operand; the locations of these operands may be
specified using any of the many addressing schemes.
The bits of the instruction are divided into groups
called fields.
1. An operation code field that specifies the operation
to be performed.
2. An address field that designates a memory address
or a processor registers.
3. A mode field that specifies the way the operand or
the effective address is determined.
Instruction format
In order to execute the instruction CPU needs to know three
things.
Operation code (opcode): specifies the type of action to be
performed
Example: add, sub, mul, div
Operands are the data on which the operation is to be
performed.
MOV B, A Here MOV is operation and (B & A) are operands.
ADD B Here ADD is operation and (B) is operand.
Operand can be place either in one of the processor register
or in memory.
Operands residing in memory are specified with their memory
address
Addressing mode: The way in which the operand is taken from
register or memory.
Instruction format
Mode Operation code Address/data
Addressing mode opcode operands

|-----------------------------Machine instruction format-----------------------------|

Instruction classification
Assume the instruction C= A+B
Three address instructions Evaluate X=(A+B) * (C+D)
Syntax: opcode, source1, Three address instructions
source2,destination 1. ADD A, B, R1;R1 ← M[A] + M[B]
Eg: ADD A,B, C 2. ADD C, D, R2 ; R2 ← M[C] + M[D]
C ->[A]+[B] 3. MUL R1, R2, X; M[X] ← R1 * R2
Two address instructions Two address instructions
Syntax: opcode source, destination 1. MOV A, R1; R1 ← M[A]
Eg: ADD A, B 2. ADD B, R1 ; R1 ← R1 +M[B]
B = [A]+[B] 3. MOV C, R2; R2 ← M[C]
MOVB,C 4. ADD D, R2 ; R2 ← R2 +M[D]
C -> [B] 5. MUL R2, R1;R1 ← R1 * R2
6. MOV R1, X; M[X] ← R1
Instruction classification
One address instructions One-Address
Syntax: opcode source 1. LOAD A ; AC← M[A]

ADD A 2. ADD B ; AC← AC + M[B]

3. STORE T; M[T]← AC
LOAD A (copies content of memory location
A to accumulator) 4. LOAD C ; AC← M[C]
ACC [A] 5. ADD D ; AC← AC + M[D]

ADD B 6. MUL T ; AC← AC *M[T]

ACC [B]+[ACC] 7. STORE X ; M[X] ← AC

STORE C (copies content of accumulator to Zero-Address

memory location C) 1. PUSH A ; Top Of Stack← A
C [ACC] 2. PUSH B ; TOS← B
Zero-address instructions stack operation 3. ADD ; TOS← (A + B)
Syntax: opcode 4. PUSH C ; TOS← C
Eg: PUSH A 5. PUSH D ; TOS← D
PUSH B, POP C 6. ADD ; TOS← (C + D)
7. MUL ; TOS← (C+D)*(A+B)
8. POP X ; M[X] ← TOS
Addressing mode
The operation field of an instruction specifies the operation to be performed.
This operation must be executed on some data stored in computer registers or memory.
The way the operands are chosen during program execution in dependent on the
addressing mode of the instruction.
The addressing mode specifies a rule for interpreting or modifying the address field of the
instruction before the operand is actually referenced.
1. Immediate Addressing Mode
2. Register Addressing Mode
3. Register Indirect Addressing Mode
4. Direct Addressing Mode
5. Indirect Addressing Mode
6. Implied Addressing Mode
7. Relative Addressing Mode
8. Indexed Addressing Mode
9. Base Register Addressing Mode
10. Autoincrement or Autodecrement Addressing Mode
Addressing mode
Immediate Addressing Mode
The operand is specified with in the instruction.
Operand itself is provided in the instruction rather than its
address.
Move Immediate
• MOVI A , 15h A ← 15h Here 15h is the immediate operand
Add Immediate
• ADDI 3Eh, A ← A + 3Eh Here 3Eh is the immediate
operand
Addressing mode
Register Addressing Mode
The operand is specified with in one of the processor
register.
Instruction specifies the register in which the operand is
stored.
Move
• MOV C , A C ← A Here A is the operand specified in
register
Add
• ADD B, A ← A + B Here B is the operand specified in
register
Cont…..
Register Indirect Addressing Mode
The instruction specifies the register in which the memory
address of operand is placed.
It do not specify the operand itself but its location with in the
memory where operand is placed.
Move
MOV A , M A ← [[H][L]]
Example:
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The instruction cycle (also known as the fetch–decode–execute cycle,
or simply the fetch-execute cycle) is the cycle that the central processing
unit (CPU) follows from boot-up until the computer has shut down in
order to process instructions.
A program consisting of sequence of instructions is executed in the
computer by going through a cycle for each instruction.
Each instruction cycle is subdivided in to sub cycles or phases. They are
Fetch an instruction from memory
Decode instruction
Read effective address from memory if instruction has an indirect
address
Execute instruction
This cycle repeats indefinitely unless a HALT instruction is encountered
Instruction Cycle State Diagram