Department of E&C Engineering,

VFSTR, Guntur

Analysis of second order phase-locked

loop
(PLL)

Presentation
By
BATCH :7

Shaik .Mahammad Akeef - 211FA05028

R. Jagadeesh Nayak - 211FA05048
A.BINDU HARI CHANDANA - 211FA05103
B.SAMPATHKUMAR - 211FA05286
 Presentation Outline

Introduction

Basic PLL System

Phase/Frequency Detector (PFD)

Application of PLL &PLL Linear Model

Phase & Frequency Relationships

PLL Transfer Functions & PLL Order & Type

Conclusion
 What is Phase Locked Loop (PLL)

• PLL is an Electronic Module (Circuit) that locks the phase

of the output to the input.

Vi(t) Phase Vo(t)

Locked
Loop
Locked Vs. Unlocked Phase

• Example of locked phase

Vi(t)

Vo(t)

• Example of unlocked phase

Vo(t)

Vi(t)

Phase Error
( ∆φ)
 Basic PLL System

•PLL is a feedback system that detects the phase error ∆φ and then adjusts the phase of
the output.
Vi(t) Phase Vo(t)
Locked
Loop
VI
Phase ∆φ Vo
VCO
Detector

• The Phase Detector (PD), detects ∆φ between the output and the input through feedback
system
• Voltage Control Oscillator (VCO) adjusts the phase difference
 Implementation of PD

Phase Detector is an XOR

gate

VI
V1 Phase ∆φ Vo
∆φ VCO
Vo Detector

   1 VI 
 0 VI  o
Vo V
Vo(t)

Vi(t)

Phase Error
( ∆φ)
 What is VCO ?

• VCO is a circuit module that oscillates at

a controlled frequency ω. ω
• The Oscillating Frequency is controlled ω0
using Voltage VControl.
VControl
– That is why the module is called Voltage Control Oscillator

VControl VCO ω
  o  KVCOVControl

• Vcontrol must be in the steady state for the VCO to operate

properly
 Simple PLL

• Structure
– Phase Detector ( XOR ) that detects the phase
error ∆φ.

– Low Pass Filter ( to smooth ∆φ ) VI ∆φ

Phase LPF VCO Vout
VControl
Detector
Vout ∆φ
– Voltage Control Oscillator (VCO)

• Basic Idea
– If VI and Vout are out of phase
(unlocked), then the PD module detects the
error and the LPF smoothes the error signal. The
control signal slows down or speeds up the
VCO module. Hence, the phase is corrected
(locked).
Locked Condition

– Locked Condition
d
dt  in out

– that 0
This implies
in out
VI
Phase ∆φ
LPF VControl VCO Vout
Detector
Vout ∆φ
 Example: In the UNLOCKED State

VI and Vout has ∆φ at the same

frequency ω1
V(t)
i

• The phase detector must Vo(t)

Phase Error
( ∆φ)
produce VI
VControl
• Hence, VCO is dynamically changing
VControl
ω V1
and PD is creating VControl to adjust ω1
ω0
φ0
for the phase difference. V1
VControl

• The PLL is in the Locked state

Dynamics of Simple PLL

• PLL is a feedback system

– PD is a gain amplifier
– LPF be first order filter ( as an example)
– VCO is a unit step module
• The transfer function of the feedback system is given
as:
 out   2
KPD KVCOLPF
H (s)  (s)  out (s) n
H(s)
in s2  2n s
2
  in n  s2  LPF s  KPD KVCO LPF
 
LPF
PD VCO
1
φin KPD s KVCO φout
1
LPF s
Transient Response to PLL

• The unit step response to second order

system ω

–– Overdamped
Critically damped
i

– Underdamped
• Problems with this PLL t
– Settling time Vs. ripple of
ωout
Vcontor
– Stability of the system
– Lacks performance in ICs

H (s)   out (s)   out (s) n2 t

  in in LPF s2  2n s 2
n
PD  VCO
1
φin K φout
KPD s VCO
1 s
LPF
 Application of PLL

• Clock Skew Reduction VI

Buffer
– Buffers are used to distribute the PFD ∆φ VControl
LPF VCO Vout
clock Vout ∆φ
– Embed the buffer within the
loop

• Jitter Reduction

Frequency Multiplications
– The feedback loop has frequency division
– Frequency division is implemented using a PFD ∆φ VControl
LPF VCO Vout
counter VI
∆φ
Counter
(Frequency
Clock Skew Reduction Division)

Buffers are used to distribute the clock

Embed the buffer within the loop
PLL Block Diagram

[Perrot
t]

• A phase-locked loop (PLL) is a negative feedback system where an

oscillator-generated signal is phase AND frequency locked to a reference
signal

14
 PLL Applications

• PLLs applications
• Frequency synthesis
• Multiplying a 100MHz reference clock to 10GHz
• Skew cancellation
• Phase aligning an internal clock to an I/O clock
• Clock recovery
• Extract from incoming data stream the clock frequency and
optimum phase of high-speed sampling clocks
• Modulation/De-modulation
• Wireless systems
• Spread-spectrum clocking

15
Forward Clock I/O Circuits
• TX PLL
• TX Clock Distribution
• Replica TX Clock
Driver
• Channel
• Forward Clock
Amplifier
• RX Clock Distribution
• De-Skew Circuit
• DLL/PI
• Injection-Locked
16
Embedded Clock I/O Circuits
• TX PLL

• TX Clock Distribution

• CDR
• Per-channel PLL-based
• Dual-loop w/ Global PLL &
• Local DLL/PI
• Local Phase-Rotator
PLLs
• Global PLL requires
RX clock distribution
to individual channels

17
Linear PLL Model

• Phase is generally the key variable of interest

• Linear “small-signal” analysis is useful for understand PLL
dynamics if
• PLL is locked (or near lock)
• Input phase deviation amplitude is small enough to maintain
18
operation in lock range
Phase Detector

e
ref

fb

• Detects phase difference between feedback clock and

reference clock
• The loop filter will filter the phase detector output, thus to
characterize phase detector gain, extract average output
19
 Loop Filter

VDD

I
Charging VCO Control
Voltage

C1 C2
Discharging
I R
F(s)
VSS

• Lowpass filter extracts average of phase detector error

pulses

20
 Voltage-Controlled Oscillator

KVCO
0 1

VDD/2

VDD

ω o u t t   ω 0  ωout
Laplace t   ω 0  KVCO vc
Domain
t  Model
• Time-domain phase relationship
ϕ t     ω t dt  K  v
out out VCO c
ϕout(t)
t dt

21
 Loop Divider

ϕout(t) ϕfb(t)

• Time-domain model

ω fb t   1 out
ω
N
t 
ϕfb t  1 ω t dt N 1 ϕ
out out

t  22
N
 Phase & Frequency Relationships

Angular Frequency is the first derivative (rate of change vs time) of phase

dϕt  t
ω 
dt t

ϕt  
o 
ωτ
Consider a sinusoid u1 t dwith
τ angular frequency ω1 t and phase
ϕ1 t 
u1 t   sinω1 tt  ϕ1 t  [Best
]
• Phase Step
ϕ1 t   ut 
u1 tNo
 change
sinω1intfrequency
 ut 


23
 Phase & Frequency Relationships

• Frequency Step ω1 t   ω0  ω
u1 t   sinω0t  ωt   sinω0t  ϕ1 t

where ϕ1 t   ωt

[Best A frequency step produces a ramp in phase

]

ϕ1 t  
ωt
24
 Understanding PLL Frequency Response

• Linear “small-signal” analysis is useful for understand PLL dynamics if

• PLL is locked (or near lock)
• Input phase deviation amplitude is small enough to maintain operation in lock
range
• Frequency domain analysis can tell us how well the PLL tracks the input phase
as it changes at a certain frequency
• PLL transfer function is different depending on which point in the loop the
output is responding to
Input phase response VCO output
response

[Fischett
e] 25
Open-Loop PLL Transfer
Function


Gs  out
s  K PD KVCO F
e s
s s
• Open-loop response generally decreases with
frequency 26
 Closed-Loop PLL Transfer Function

Forward Path Gain 

Gs
Loop Gain
out s Gs KPD KVCO F
K PD K VCO F s H s  
l1  
Gs sN


ref  sKPD KVCO F s
1 s
Forward Path Determinant 1 N
1
 1 0  s Gs
N N
• Low-pass response whose overall order is set
 Gs 
System Determinant   1  N   0  1 N
by F(s)
Gs
27
 PLL Error Transfer Function

Forward Path Gain  1 s

1
Es ref

e s
 
s G s
K VCO
PD
K F
Loop Gain  1 Ns s N
K PD KVCO F s
l1    
GssN
N 1 0 
Forward Path Determinant 1  • Ideally, we want this to be zero
1
• Phase error generally increases with
 Gs 
System Determinant   1  N   0  1 N
frequency due to this high-pass response
Gs
28
 PLL Order and Type

• The PLL order refers to the number of poles in the

closed-loop transfer function
• This is typically one greater than the number of loop
filter poles

• The PLL type refers to the number of integrators

within the loop
• A PLL is always at lease Type 1 due to the VCO
integrator

• Note, the order can never be less than the type

29
 First-Order PLL

F s 
K1
KPD KVCO K1 NKDC
Forward Path Gain : Gs  
s s
  K K K
DC Loop Gain Magnitude : KDC     PD VCO 1
sG   N
• Simple first-order lim s0 

s NKDC
low- pass transfer Transfer Function : H s KPD KVCO K1 N 
Nω3dB 
s  KDC
 KPD KVCO K1 s  ω3dB
function s N

• Closed-loop Closed - Loop Bandwidth : ω 3dB 

KPD KVCO K1
N  K DC

bandwidth is equal s s s
Error Function : Es  
to the DC loop gain  K KVCO K1
s  PD N s  ω3dB
s  KDC

magnitude

30
 First-Order PLL Tracking Response

• The PLL’s tracking behavior, or how the phase error responds to an input phase
change, varies with the PLL type
• Phase Step Response [Best
]
ϕ1 t   ut 
u1 t   sinω1 t 
ut 

• The No change
final valueintheorem
frequencycan be used to find the steady-state phase error

lim  sEs  lim s 

s0 
s  s0 s  K
0 DC

• All PLLs should have no steady-state phase error with a phase step error Note,
this assumes that the frequency of operation is the same as the VCO center frequency
(Vctrl=0).Working at a frequency other than the VCO center frequency is considered
having a frequency offset (step).

31
 First-Order PLL Tracking Response

• Frequency Offset [Best

]
(Step)
ω1 t   ω0  ω
u1 t   sinω0t  ωt   sinω0t  ϕ1 t

where ϕ1 t   ωt
• The final value theorem can be used to find the steady- state
A frequency step produces a ramp in phase
phase error
ω ω ω
lim  2 sEs s0lim
s  KDC 
s0  s  KDC

• With a frequency offset (step), a first-order PLL will lock

with a steady-state phase error that is inversely proportional
to the loop gain
32
 First-Order PLL Issues

• The DC loop gain directly sets the PLL bandwidth

• No degrees of freedom

• In order to have low phase error, a large loop gain is

necessary, which implies a wide bandwidth
• This may not be desired in applications where we would like to filter
input reference clock phase noise

• First-order PLLs offer no filtering of the phase detector

output
• Without this filtering, the PD may not be well approximated by a
simple KPD factor
• Multiplier PDs have a “second-harmonic” term
• Digital PDs output square pulses that need to be filtered
33
 Second-Order Type-1 PLL w/ Passive Lag-Lead Filter

Passive Lag-Lead Loop

[Allen
Filter
]

1 sτ 2
F s
1 sτ1  τ

τ1  R1C τ2
 
2

R2C 34
 Second-Order Type-1 PLL / Passive Lag-Lead Filter

1 sτ  τ 
F s NK DC 
τ  s 
1

12 s 1τ  Forward Path Gain : Gs K PD KVCO 1  sτ  1 τ2  τ2 
2
2

 s1 sτ1 τ 
  
τ1  τ τ
2 1 
s s 
2 

2   1 τ 2 

K K
R1C R2C sGs τ
DC Loop Gain Magnitude : KDC  lim  N   PDN VCO
s0 
 Nωn 
KPD KVCOτ  1 2

τ1 2
2
s  ω n 2ζ  PD K VCO s  ωn

Transfer Function : H s  τ2   

τ s 2  2ζωn s  ωn
  1 K PDK VCOτ 2 N  K K VCO N K
s 
2
τ1 τ 2 s  N PDτ τ
2

  1

 τ2 2 
KDC   s  
τ 1 τ 2 1  τ 2 
N
2  1 K τ  K
s   τ DCτ 2 s  DC
 1 2  1 2
τ
Natural Frequency : ωn τ KPD KVCO
 N τ 1 2τ

ω 
 N 
Damping Factor :ζ  n
2  
2  K PD KVCO 
τ
s s  Nω n 2 
 KPD KVCO
Error Function : Es
 s2  2ζωn s  ωn 2
2
 Second-Order Type-1 PLL Tracking Response

• Phase Step Response

 Nω2 
s s  n


lim  sEs s0 K PD KVCO 
s0 
s  s  ζωn s  n2  0
2

lim 2 ω
Again, phase error should be zero with a phase
step

• Frequency Offset (Step)

 Nω2 
ω s  n

ω
lim  2 sEs K PD KVCO2 
s0 s 2  2ζω 
ω
 n s  n
lim s KDC
s0
ω
• A second-order type-1 PLL will still lock with a phase error if
there is a frequency offset!

36
 Second-Order Type-1 PLL Properties
• While the second-order type-1 PLL will still lock with a phase
error with a frequency offset, it is much more useful than a first-
order PLL

• There are sufficient design parameters (degrees of freedom) to

independently set n and KDC
• The loop filter conditions the phase detector output for proper
VCO control
• Loop stability needs to be considered for the second-order
system

37
 Second-Order Type-2 PLL / Passive Series-RC Lag-Lead Filter

Passive Series-RC Loop

Filter

1 
R s  
F s   RC
s

• Note, this type of loop filter is typically used with a charge- pump driving it.
Thus, the filter transfer function is equal to the impedance.

38
 Second-Order Type-2 PLL / Passive Series-RC Lag-Lead Filter

1 
R s   DC Loop Gain Magnitude : KDC   (ideally)
F s   RC
s
1 
K PD KVCO R s 
RC 

Forward Path Gain : Gs
 s2
 ωn 
1 
K PD KVCO R s  N 2ζωn  s  2ζ
RC 

Transfer Function : H s  
 K PD KVCO R  K PD KVCO  s 2  2ζωn s  n2
 2
s  s
 N  NC ω

Natural Frequency : ωn KPD KVCO

 NC

ω
Damping Factor :ζ 2 n
RC
Error Function : Es 2 s2
 s  2ζωn s  2
n
ω
39
Second-Order Type-2 PLL Tracking
Response
• Phase Step Response
s2
lim      2
sE s

s0 
s lim s0 s  2ζωn s  2
0
ωn
Again, phase error should be zero with a phase
step

• Frequency Offset (Step)

ω ωs
lim  2 sEs  lim2  2ζω 2 
s0  s  s0 s n s  n
0 ω

• A second-order type-2 PLL will lock with no phase error with a

frequency offset!

40
 Second-Order Type-2 PLL
Properties
• A big advantage of the type-2 PLL is that it has zero phase error even with a
frequency offset This is why type-2 PLLs are very popular

• A type-2 PLL requires a zero in the loop filter for stability. Note, this is not
required in a type-1 PLL

• This zero can cause extra peaking in the frequency response

• Important to minimize this in some applications, such as cascaded CDR
systems

41