0% found this document useful (0 votes)
17 views16 pages

Intrupt

Uploaded by

nohomaj999
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
17 views16 pages

Intrupt

Uploaded by

nohomaj999
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 16

Computer Organization

and Architecture

Chapter 3
System Buses
Instruction Cycle -
State Diagram
Interrupts
• Mechanism by which other modules (e.g.
I/O) may interrupt normal sequence of
processing
• Program
—e.g. overflow, division by zero
• Timer
—Generated by internal processor timer
—Used in pre-emptive multi-tasking
• I/O
—from I/O controller, completion of I/O or error
• Hardware failure
—e.g. memory parity error, power failure
Why are Interrupts Useful?
• Devices are slow,
using interrupt improves processing
efficiency by
—letting CPU execute its normal instruction
sequence and
—pause to service the external devices when they
signal that they are ready for CPU’s attention
Program Flow Control (1)
Program Timing
Short I/O Wait
Program Timing
Long I/O Wait
Program Flow Control (2)
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
—Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
—Suspend execution of current program
—Save context
—Set PC to start address of interrupt handler
routine
—Process interrupt
—Restore context and continue interrupted program
Instruction Cycle with Interrupts
Instruction Cycle (with Interrupts) - State
Diagram
Multiple Interrupts
• Disable interrupts - Sequential approach
—Processor will ignore further interrupts whilst
processing one interrupt
—Interrupts remain pending and are checked
after first interrupt has been processed
—Interrupts handled in sequence as they occur
• Define priorities - Nested approach
—Low priority interrupts can be interrupted by
higher priority interrupts
—When higher priority interrupt has been
processed, processor returns to previous
interrupt
Multiple Interrupts - Sequential
Multiple Interrupts - Nested
Time Sequence of Multiple Interrupts
Interconnection Structures
• All the units must be connected
• Interconnection structure:
The collection of paths connecting system
modules
• Different type of connection for different
type of unit
—Memory
—Input/Output
—CPU
• Design depends on necessary exchanges
between modules

You might also like