Computer Organization

and Architecture

Chapter 3
System Buses
Topics
• Computer Components
• Computer Function
• Interconnection Structures
• Bus Interconnection
• PC Buses
Interconnection Structures
• All the units must be connected
• Interconnection structure:
The collection of paths connecting system
modules
• Different type of connection for different
type of unit
—Memory
—Input/Output
—CPU
• Design depends on necessary exchanges
between modules
Data Transfer
• Memory  CPU
• CPU  Memory
• I/O  CPU
• CPU  I/O
• I/O  Memory (?)
DMA: direct memory access
Computer Modules
Memory Connection
• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
—Read
—Write
—Timing
Input/Output Connection(1)
• Similar to memory from computer’s
viewpoint
• Output
—Receive data from computer
—Send data to peripheral
• Input
—Receive data from peripheral
—Send data to computer
Input/Output Connection(2)
• Receive control signals from computer
• Send control signals to peripherals
—e.g. spin disk
• Receive addresses from computer
—e.g. port number to identify peripheral
• Send interrupt signals (control)
CPU Connection
• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives (& acts on) interrupts
Bus Interconnection (1)
• Bus:
—A communication pathway connecting two or
more devices
—Characteristics
– shared transmission medium
– Usually broadcast
– must ensure only one device transmitting at a time
—Often grouped
– A number of channels in one bus
– e.g. 32 bit data bus is 32 separate single bit channels
Buses Interconnection (2)
• There are a number of possible
interconnection systems
• Single and multiple BUS structures are
most common
—e.g. Control/Address/Data bus (PC)
—e.g. Unibus (DEC-PDP)
System Bus
• Bus that connects major computer
components
• Typically 50-100 separate lines
• Three functional groups of lines
—Data
—Address
—Control
• Misc. lines
—power
—ground
—clock
Data Bus
• Carries data
—I.e., moves data between system modules
—Remember that there is no difference between
“data” and “instruction” at this level
• Width is a key determinant of
performance
—Number of lines (1 bit carried by a line at a
time)
—Determines number of bits can be transferred
at a time
—8, 16, 32, 64 bit
Address bus
• Identify the source or destination of data
—e.g. CPU needs to read an instruction (data)
from a given location in memory or an I/O port
• Width determines maximum memory
capacity of system
—e.g. 8080 has 16 bit address bus giving 64k
address space
 Control Bus
• Control and timing information
— Memory read/write signal
— Interrupt request
— Clock signals
— access/use of data/address lines
• Typical control lines include
• • Memory write: Causes data on the bus to be written into the addressed
location
• • Memory read: Causes data from the addressed location to be placed on the
bus
• • I/O write: Causes data on the bus to be output to the addressed I/O port
• • I/O read: Causes data from the addressed I/O port to be placed on the bus
• • Transfer ACK: Indicates that data have been accepted from or placed on
• the bus
• • Bus request: Indicates that a module needs to gain control of the bus
• • Bus grant: Indicates that a requesting module has been granted control of the
bus
• • Interrupt request: Indicates that an interrupt is pending
• • Interrupt ACK: Acknowledges that the pending interrupt has been recognized
• • Clock: Is used to synchronize operations
• • Reset: Initializes all modules
Bus Interconnection Scheme
Big and Yellow?
• What do buses look like?
—Parallel lines on circuit boards
—Ribbon cables
—Strip connectors on mother boards
– e.g. PCI
—Sets of wires
 Bus Operation
• Module wishing to send
1. Obtain use of bus
2. Transfer data via bus
• The operation of the bus is as follows. If one module wishes to send data to
another,it must do two things: (1) obtain the use of the bus, and (2) transfer
data via the bus.
• If one module wishes to request data from another module, it must (1)
obtain the use of the bus, and (2) transfer a request to the other module
over the appropriate control and address lines. It must then wait for that
second module to send the data.

• Module wishing to receive

—Obtain use of bus
—Transfer request to the other module
—Wait
 Single Bus Problems
• If a great number of devices are connected to the bus, performance will
suffer.
There are two main causes:
1. In general, the more devices attached to the bus, the greater the bus length and hence the
greater the propagation delay. This delay determines the time it takes for devices to coordinate
the use of the bus. When control of the bus passes from one device to another frequently, these
propagation delays can noticeably affect performance.
2.The bus may become a bottleneck as the aggregate data transfer demand approaches the
capacity of the bus. This problem can be countered to some extent by increasing the data rate
that the bus can carry and by using wider buses (e.g., increasing the data bus from 32 to 64
bits). However, because the data rates generated by attached devices (e.g., graphics and video
controllers, network interfaces) are growing rapidly, this is a race that a single bus is ultimately
destined to lose.

• Most systems use multiple buses to overcome

these problems
—Hierarchical
—Traditional
—High-performance
Traditional (ISA)
(with cache)
High Performance Bus
Elements of Bus Design
• Bus type
• Bus width
• Data transfer type
• Arbitration method
• Bus timing
 Bus Types
• Dedicated
• A dedicated bus line is permanently assigned either to one function (e.g. address bus) or
to a physical subset of computer components(e.g. I/O bus connects all I/O
modules).
—Separate data & address lines which is common on many buses.

• Multiplexed
• • In a multiplexed bus, a bus can be used for both addresses
and data. In this case, an address valid control line is needed
to determine whether the data is an address or data. Time
multiplexing is using the same lines for multiple purposes.
—Advantage - fewer lines
—Disadvantages
– More complex control
– Potential reduction in performance
Bus Width and Data Transfer Type
• Bus width
—Data
—Address
• Data transfer type
—Read
—Write
—Read-modify-write: protecting shared memory
—Read-after-write: checking
—Block data transfer
 Bus Arbitration
• Why arbitration?
—More than one module controlling the bus, e.g. CPU
and DMA controller
—We want to make sure that only one module can
successfully transmit over bus at a time
• Arbitration may be centralised or distributed
In a centralized scheme, a single hardware device, referred to as a bus
• controller or arbiter, is responsible for allocating time on the bus.The
device may be separate module or part of the processor.
• In a distributed scheme, there is no central controller. Rather, each
module contains access control logic and the modules act together to
share the bus.
• With both methods of arbitration, the purpose is to designate one device,
either the processor or an I/O module, as master.
• may then initiate a data transfer (e.g., read or write) with some other
device, which acts as slave for this particular exchange
Centralised Arbitration
• Single hardware device controlling bus
access
—Bus Controller
—Arbiter
• May be part of CPU or separate
Distributed Arbitration
• Each module may claim the bus
• Control logic on all modules
Bus Timing (1)
• Co-ordination of events on bus
—Synchronous (e.g., PCI)
—Asynchronous (e.g., Futurebus+)
• Synchronous
—Events determined by clock signals
—Control Bus includes clock line transmits a regular sequence of
alternating 1s and 0s of equal duration

—A single 1-0 is referred to a bus cycle

—All devices can read clock line and event start
with clock cycle
—Usually sync on leading edge
—An event start at the beginning of a clock cycle,
usually a single cycle for an event
 Bus Timing (2)
• Asynchronous
—Occurrence of one event on a bus follows and
depends on the occurrence of a previous event.
—More flexible in accommodating devices of various
speed
—More complicated

• Synchronous timing is simpler to implement and test. However, it is

less flexible
• than asynchronous timing. Because all devices on a synchronous bus
are tied to
• a fixed clock rate, the system cannot take advantage of advances in
device performance.
• With asynchronous timing, a mixture of slow and fast devices, using
older
• and newer technology, can share a bus.
Synchronous Timing Diagram
Asynchronous Timing – Read Diagram
Asynchronous Timing – Write Diagram
• BUS WIDTH
• The width of the data bus has an impact on system performance:
The wider the data bus, the greater
• the number of bits transferred at one time.The width of the
address bus has an impact
• on system capacity: the wider the address bus, the greater the
range of locations
• that can be referenced.
PCI Bus
• Peripheral Component Interconnectionis a popular
high-bandwidth, processor-independent bus that can function as a
mezzanine or peripheral bus.
• PCI delivers better system performance for high-speed I/O subsystems
(e.g., graphic display adapters, network interface controllers, disk
controllers, and so on).

• Intel released to public domain

• 32 or 64 bit
• 49 mandatory and 51 optional signal lines
(see Tables 3.3 and 3.4, respectively)
• Current standard
—Up to 64 data lines at 66Mhz
—Q: what is the max raw transfer rate?
— raw transfer rate of 528 MByte/s, or 4.224 Gbps
• PCI may be configured as a 32- or 64-bit bus.
• Table 3.3 defines the 49 mandatory signal
• lines for PCI.These are divided into the following functional groups:
• • System pins: Include the clock and reset pins.
• • Address and data pins: Include 32 lines that are time multiplexed
for addresses
• and data. The other lines in this group are used to interpret and
validate
• the signal lines that carry the addresses and data.
• • Interface control pins: Control the timing of transactions and
provide coordination among initiators and targets.
• Arbitration pins: Unlike the other PCI signal lines, these are not
shared lines.
• Rather, each PCI master has its own pair of arbitration lines that
connect it directly
• to the PCI bus arbiter.
• • Error reporting pins: Used to report parity and other errors.
PCI Bus Data Transfers
• • Every data transfer on the PCI bus is a
single transaction consisting of one address
phase and one or more data phases.
• • Transaction between initiator (master)
and target (slave)
• • Master claims bus
• • Determine type of transaction —e.g. I/O
read/write
• • Address phase
• • One or more data phases
Foreground Reading
• Stallings, chapter 3
• www.pcguide.com/ref/mbsys/buses/, you
may also read the whole site:
www.pcguide.com/
• Futurebus+:
http://granite.sru.edu/~stringer/fb.html