Internal Memory (RAM+

ROM)
• The two basic forms of semiconductor random access
memory (RAM) are dynamic RAM (DRAM) and static
RAM (SRAM).

• SRAM is faster, more expensive, and less dense than DRAM,

and is used for cache memory. DRAM is used for main
memory.

• To compensate for the relatively slow speed of DRAM, a

number of advanced DRAM organizations have been
introduced. The two most common are synchronous DRAM
and RamBus DRAM. Both of these involve using the system
clock to provide for the transfer of blocks of data.
 Organization
• The basic element of a semiconductor
memory is the memory cell.
• All semiconductor memory cells share
certain properties:

▫ They exhibit two stable (or semistable) states,

which can be used to represent binary 1 and
0.
▫ They are capable of being written into (at
least once), to set the state.
▫ They are capable of being read to sense the
state.
Memory Cell Operation
• The cell has three functional terminals capable of
carrying an electrical signal. The select terminal is to
select a memory cell for a read or write operation.

• The control terminal indicates read or write.

• For writing, the third terminal is to provide an electrical

signal that sets the state of the cell to 1 or 0. For reading,
that terminal is used for output of the cell’s state.
 Semiconductor Memory Types
Memory Type Category Erasure Write Mechanism Volatility

Random-access Read-write Electrically, byte-

Electrically Volatile
memory (RAM) memory level

Read-only
Masks
memory (ROM) Read-only
Not possible
memory
Programmable
ROM (PROM)

Erasable PROM UV light, chip-

(EPROM) level Nonvolatile

Electrically
Electrically Read-mostly
Electrically, byte-
Erasable PROM memory
level
(EEPROM)

Electrically,
Flash memory
block-level
 Random Access Memory (RAM)
• The most common is referred to as random-access
memory (RAM).

• One distinguishing characteristic of RAM is that it is

possible both to read data from the memory and to write
new data into the memory easily and rapidly.

• The other distinguishing characteristic of RAM is that it is

volatile.

• The two traditional forms of RAM used in computers are

DRAM and SRAM.
 Semiconductor Main Memory
• Random Access Memory (RAM)
▫ Misnamed as all semiconductor memory is random
access.
▫ Read/Write.
▫ Volatile.
▫ Temporary storage.
▫ Static or dynamic.
 Dynamic RAM (DRAM)
• Bits stored as charge in capacitors.
• Charges leak.
• Need refreshing even when powered.
• Simpler construction.
• Smaller per bit.
• Less expensive.
• Need refresh circuits.
• Slower.
• Used for main memory.
• Essentially an analogue device:
▫ Level of charge determines value.
• DRAM is made with cells that store data as charge on
capacitors. The presence or absence of charge in a
capacitor is interpreted as a binary 1 or 0.

• The next diagram is a typical DRAM structure for an

individual cell that stores 1 bit. The address line is
activated when the bit value from this cell is to be read
or written. The transistor acts as a switch that is closed
(allowing current to flow) if a voltage is applied to the
address line and open (no current flows) if no voltage is
present on the address line.
Dynamic RAM (DRAM) Cell Structure
 DRAM Operation
• Address line active when bit is to be read or written.
▫ Transistor switch closed (current flows).
• For write operation:
▫ Voltage signal is applied to the bit line.
 High voltage for 1, low voltage for 0.
▫ Then a signal is applied to the address line.
 Transfers charge to the capacitor.
• For read operation:
▫ Address line is selected.
 transistor turns on.
▫ Charge on capacitor is fed out onto bit line to sense amplifier.
 Sense amplifier compares capacitor voltage with reference value
to determine if the cell has 0 or 1.
▫ Capacitor charge must be restored
 Static RAM (SRAM)
• Bits stored as on/off switches.
• No charges to leak.
• No refreshing needed when powered.
• More complex construction.
• Larger per bit.
• More expensive.
• Does not need refresh circuits.
• Faster.
• Used for cache memory.
• Digital device:
▫ Uses flip-flops.
Static RAM (SRAM) Cell Structure
 Static RAM (SRAM) Operation
• Four transistors T1,T2,T3,T4 connected in an arrangement gives stable
logic state.

• State 1:
▫C1 high, C2 low
▫T1 T4 off, T2 T3 on

• State 0:
▫C2 high, C1 low
▫T2 T3 off, T1 T4 on

• Address line controls the two transistors T5 T6 by switch it on to

allowing read or write operation.
 Static RAM (SRAM) Operation

• For write operation:

▫ The desired bit value is applied to line B, while its
complement is applied to line B’ .
▫ This forces the four transistors (T1, T2, T3, T4) into the
proper state.

• For a read operation:

▫ The bit value is read from line B.
 Static RAM (SRAM)

• A static RAM will hold its data as long as power is

supplied to it.

• Both states are stable as long as the direct current (dc)

voltage is applied.

• Unlike the DRAM, no refresh is needed to retain (hold)

data.
 SRAM versus DRAM
• Both volatile.
▫ Power needed to preserve data.
• Dynamic Memory Cell:
▫ Simpler to build, smaller.
▫ More dense (smaller cells = more cells per unit area).
▫ Less expensive.
▫ Needs refresh circuitry.
▫ Favoured for larger memory units.
• Static Memory Cell:
▫ Faster.
▫ Used for cache memory (both on and off chip).
 Read Only Memory (ROM)

• It contains a permanent pattern of data that cannot be

changed.
• A ROM is nonvolatile.
• While it is possible to read a ROM, it is not possible to
write new data into it.
• An important application of ROMs is:
▫ Systems Library.
▫ Systems programs (BIOS).
▫ Function tables.
 Types of ROM
• Written during manufacture:
▫ Very expensive for small runs.
• Programmable (once):
▫ PROM.
▫ Needs special equipment to program.
• Read “mostly”:
▫ Erasable Programmable (EPROM).
 Erased by UV.
▫ Electrically Erasable (EEPROM).
 Takes much longer to write than read.
▫ Flash memory.
 Erase whole memory electrically.
 Programmable ROM (PROM)
• When only a small number of ROMs with a particular
memory content is needed, a less expensive alternative is the
programmable ROM (PROM).
• It is nonvolatile and may be written into only once. For the
PROM,
• The writing process is performed electrically and may be
performed by a supplier or customer at a time later than the
original chip fabrication.
• Special equipment is required for the writing or
“programming” process.
• PROMs provide flexibility and convenience.
 Erasable Programmable (EPROM)

• It is read and written with UV light, at chip-level, as with

PROM.
• It can be altered multiple times and, like the ROM and
PROM, holds its data virtually indefinitely.

• For comparable amounts of storage, the EPROM is more

expensive than PROM, but it has the advantage of the
multiple update capability.
 Electrically Erasable Programmable
Read-Only Memory (EEPROM)

• It is a read-mostly memory that can be written into at any

time without erasing prior contents; only the byte or bytes
addressed are updated.
• It is read and written using Electrivity.
• It combines the advantage of non volatility with the
flexibility of being updatable in place, using ordinary bus
control, address, and data lines.

• EEPROM is more expensive than EPROM and also is

less dense, supporting fewer bits per chip.
 Flash Memory

• Like EEPROM, flash memory uses an electrical erasing

technology.
• An entire flash memory can be erased in one or a few
seconds, which is much faster than EPROM.
• In addition, it is possible to erase just blocks of memory
rather than an entire chip.
• Like EPROM, flash memory uses only one transistor per
bit, and so achieves the high density.
 Chip Logic

• Semiconductor memory comes in packaged chips like in

next slide.
• Each chip contains an array of memory cells.
• For semiconductor memories, one of the key design
issues is the number of bits of data that may be
read/written at a time. At one extreme is an organization in
which the physical arrangement of cells in the array is the
same as the logical arrangement (as perceived by the
processor) of words in memory.
 Refreshing

• Refresh circuit included on chip.

• Disable DRAM chip while all data cells are refreshed.
• Count through rows.
• The data are read out and written back into the same
location. This causes each cell in the row to be refreshed.
• Takes time.
• Slows down apparent performance.
 Synchronous DRAM (SDRAM)

• Access is synchronized with an external clock.

• Address is presented to RAM.
• RAM finds data (CPU waits in conventional DRAM).
• Since SDRAM moves data in time with system
clock, CPU knows when data will be ready.
• CPU does not have to wait, it can do something
else.
• Burst mode allows SDRAM to set up stream of data
and fire it out in block.
• DDR-SDRAM sends data twice per clock cycle
(leading & trailing edge).
• One of the most widely used forms of DRAM is the
synchronous DRAM.

• SDRAM exchanges data with the processor synchronized to

an external clock signal and running at the full speed of the
processor/memory bus without imposing wait states.

• The traditional DRAM chip is constrained both by its

internal architecture and by its interface to the processor’s
memory bus.
• With synchronous access, the DRAM moves data in and
out under control of the system clock.
• The processor or other master issues the instruction and
address information, which is latched by the DRAM.
• The DRAM then responds after a set number of clock
cycles.
• Meanwhile, the master can safely do other tasks while
the SDRAM is processing the request.

• The SDRAM performs best when it is transferring large

blocks of data serially, such as for applications like
word processing, spreadsheets, and multimedia.
 DDR SDRAM

• SDRAM can only send data once per clock.

• Double-data-rate SDRAM can send data twice per

clock cycle.
▫Once on rising edge and once on falling edge.

• DDR chips are widely used in desktop computers and

servers.
• There have been two generations of improvement to the
DDR technology:
▫ DDR2 increases the data transfer rate by increasing the
operational frequency of the RAM chip and by increasing
the prefetch buffer from 2 bits to 4 bits per chip.
 The prefetch buffer is a memory cache located on the RAM
chip.
 The buffer enables the RAM chip to preposition bits to be
placed on the data base as rapidly as possible.

▫ DDR3 increases the prefetch buffer size to 8 bits.