An Introduction to VHDL

languages

Dr. Hakem Beitollahi

Computer Engineering Department

Elmo Sanat University
Outline
 Types of HDL
 VHDL versus Verilog
 VHDL (introduction)

HDL— 2
hardware description language
 A hardware description language (HDL) is a
specialized computer language used to describe
the structure and behavior of digital systems
 A hardware description language looks much like
a programming language such as C.
 The main difference with software programming
languages is the nature of HDL is parallel; while
the nature of software languages is sequential
 It is a textual description consisting of
expressions, statements and control structures
 Most commercial designs built using HDLs
HDL — 3
 HDL vs. Schematic
 Schematic’s advantages
 Useful for small projects
 Easy to learn and design

 Schematic’s disadvantages
 difficult to manage when
complexity grows (million gates
ASICs-FPGAs)
 difficult to maintain for a long
lifetime
HDL — 4
Types of HDL languages
• Two leading HDLs:
– Verilog
• developed in 1984 by Gateway Design Automation
• became an IEEE standard (1364) in 1995
– VHDL
• Developed in 1981 by the Department of Defense
• Became an IEEE standard (1076) in 1987
• Other HDL languages
• GEZEL
• SystemC (enhance C for hardware design)
• System Verilog (Add system level design to Verilog)
• Ruby
• JHDL
• Etc.
HDL — 5
VHDL vs. Verilog
 Verilog is based on C, while VHDL is based on Pascal and Ada.
 Unlike Verilog, VHDL is strongly typed.
 Unlike VHDL, Verilog is case sensitive.
Verilog is easier to learn compared to VHDL.
 Verilog has very simple data types, while VHDL allows users to create more
complex data types
 Verilog will not allow programmers to put needed modules in separate files that
are called during compilation. Large projects on Verilog might end up in a large,
and difficult to trace, file.
 VHDL more popular with European companies, Verilog more popular with US
companies

HDL — 6
VHDL vs. Verilog
 High level constructs

VHDL:

There are more constructs and features for high-level
modeling in VHDL than there are in Verilog.

Abstract data types can be used along with the following
statements:

package statements for model reuse,

configuration statements for configuring design structure,

generate statements for replicating structure,

generic statements for generic models that can be individually
characterized, for example, bit width.

Verilog:

there is no equivalent to the high-level VHDL modeling
statements in Verilog
HDL — 7
VHDL vs. Verilog
 Libraries
 VHDL:

A library is a store for compiled entities,
architectures, packages and configurations. Useful
for managing multiple design projects.
 Verilog:

There is no concept of a library in Verilog. This is
due to it's origins as an interpretive language.

HDL — 8
VHDL vs. Verilog
 Low level constructs
 VHDL

Simple two input logical operators are built into the language,
they are: NOT, AND, OR, NAND, NOR, XOR and XNOR.

Any timing must be separately specified using the after
clause.
 Verilog

The Verilog language was originally developed with gate
level modeling in mind, and so has very good

constructs for modeling at this level and for modeling the cell
primitives of ASIC and FPGA libraries.

Examples include User Defined Primitives (UDP), truth tables
and the specify block for specifying timing delays across a
module.

HDL — 9
VHDL vs. Verilog
 Example [Binary up counter]
process (clock) VHDL
begin
if clock='1' and clock'event then
counter <= counter + 1;
end if;
end process;

Verilog
reg [upper:0] counter;
always @(posedge clock)
counter <= counter + 1;

HDL — 10
VHDL vs. Verilog
 Verilog and VHDL are equivalent for RTL modeling (code
that will be synthesized).
 For high level behavioral modeling, VHDL is better

Verilog does not have ability to define new data types

Other missing features for high level modeling
 Verilog has built-in gate level and transistor level primitives

Verilog much better than VHDL at below the RTL level.
 The choice of which to use is not therefore based solely
on technical capability but on:

Personal preferences

EDA (Electronic design automation) tool availability

Commercial, business and marketing issues
 Bottom Line: You should know both!!!!!
HDL — 11
VHDL

HDL — 12
Introduction to VHDL
 VHDL: VHSIC Hardware Description Language

VHSIC: Very High Speed Integrated Circuit
 History of VHDL

1980: initiated by US army (Pentagon) to describe and
to document of electronic systems

1985: 7.2 version of VHDL by IBM, Intermetrics and
Texas Instruments

1986: All rights transfer to IEEE

1987: first IEEE version – IEEE1067-1987

1993: Revised Standard- IEEE1076-1993 (vhdl-93)

2000: minor revision

2002: minor revision

2008: major revision

2019: major revision (latest version of VHDL)

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Introduction to VHDL
 How is VHDL used?

For design specification

For simulation

For documentation

For implementation

For test & verification

As an alternative to schematic design
 Why VHDL?

Achieve Maximum Reliability With

Minimum cost

Minimum development time

Allow Automatic Synthesis of Design into
Hardware

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Introduction to VHDL

 C:
 Procedural (method) programming languages
 Typically describe methods for computing a math function
or manipulation of data (e.g., sorting, matrix computing)
 A program is a recipe or a sequence of steps for how to
perform a computation or manipulate data.
 VHDL:
 A language to describe digital systems.
 Purposes: simulation and synthesis of digital systems.

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Design Process

HDL — 16
Digital System Design Process

HDL — 17
Different perspectives of a system
 Behavioral view:
 Describe functionalities and i/o behavior
 Treat the system as a black box
 Use flowcharts, Pseudocode, flow graph
 Structural view:
 Describe the internal implementation (components and
interconnections)
 Essentially block diagram
 Registers, logic components are connected via buses
(directional or bi-directional)
 Physical view:
 Add more info to structural view: component size, component
locations, routing wires
 E.g., layout of a print circuit board
Structural view vs. physical view

HDL — 19
VHDL: Abstraction Levels (I)
Abstraction levels of System Design

HDL — 20
VHDL: Abstraction Levels (II)

HDL — 21
 Behavioral Description in VHDL
• This level describes a system by
concurrent algorithms (Behavioral).
• Each algorithm itself is sequential
(consists of a set of instructions that
are executed one after the other.)
• Functions, procedures are the main
elements. There is no regard to the
structural realization of the design.

• We describe the behavior of an

entity using sequential statements
• It very similar to high-level
programming languages in syntax
and semantics
• Writing a program in behavioral
style is by using something called a
“process”.

Such descriptions are usually simulatable, but not synthesizable. HDL — 22

 RT Level in VHDL (Data flow)
RTL: Register Transfer Level

Specifying the characteristics of a circuit by how data is transformed as it is

passed from register to register.

The transforming of the data is performed by the combinational logic that exists
between the registers.

The description is divided into combinational logic and storage elements. The
storage elements (flip-flops, latches) are controlled by a system clock.
Modern definition of a RTL code is "Any code that is synthesizable is called
RTL code".
The description is synthesizable. HDL — 23
 Gate-level in VHDL (Structural)

The description has been synthesized.

A gate level description consists of a network of gates and registers instanced

from a technology library

The interconnection of components within an architecture.

It is called netlisting language
The design is represented as a netlist with gates (AND, OR, NOT,...) and storage
elements, all with cell delays. HDL — 24
Layout Level Description
 The different cells of the target technology are
placed on the chip and the connections are
routed.
 After the layout has been verified, the circuit is
ready for the production process.
 If the layout is completed, the wire lengths and
thus the propagation delays due to parasitic
will be known. The design can be simulated on
gate level netlist added with propagation
delays, after back-annotation, and,
consequently, the timing behavior of the
entire circuit can be validated.
 Back Annotation: Taking the delays from the
layout (after place&route phase) and entering
them into the description (schematic or HDL-
based), this way allowing to do more realistic
simulation.
HDL — 25
Let’s start VHDL

HDL — 26
Let’s Start Simple
The structure of a Full Adder

s1
In1 sum
In2

s2

s3 c_out

c_in

HDL — 27
Entity-Architecture Pair
1- in
2- out
3- inout
4- buffer

entity name port names port mode (direction)

port type punctuation

reserved words
28
Entity Declarations
 The entity describes the interface to the
outside world.
 It specifies the number of ports, the direction
of the ports, and the type of the ports
 The interface signals are listed in the PORT
clause
 In this respect, the entity is akin to the

schematic symbol for the component

 Entity is roughly equivalent to a function
definition in C

29
Entity Example

x
FULL cout
y sum
Adder
cin
ENTITY full_adder IS

PORT( x, y, cin : IN BIT;

cout, sum : OUT BIT);
END full_adder;

30
Entity Declarations
Port Clause

 Three parts of the PORT clause

 Name
 Mode
 Data type

PORT
PORT (signal_name
(signal_name :: mode
mode data_type);
data_type);

PORT
PORT (( input
input :: IN
IN BIT_VECTOR(3
BIT_VECTOR(3 DOWNTO
DOWNTO 0);
0);
ready,
ready, output
output :: OUT
OUT BIT
BIT );
);

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 Entity Declarations

 The Port Mode of the interface describes the direction in

which data travels with respect to the Component
 Four Port Modes
1. In (Input port): A variable or a signal can read a value from a
port of mode in, but is not allowed to assign a value to it.

2. Out (Output port): It is allowed to make signal assignments to

a port of the mode out, but it is not legal to read from it.

3. Inout (bidirectional port): Both assignments to such a port and

reading from it are allowed.

4. Buffer: output port with read capability. It differs from inout in

that it can be updated by at most one source, whereas inout
can be updated by zero or more sources.
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About Buffer port mode
 VHDL allows buffer port mode when a
signal is used both internally, and as an
output port when there is only one internal
driver.
 Buffer ports are a potential source of errors
during synthesis, and complicate validation
of post-synthesis results through
simulation.

 RECOMMENDED: Do not use buffer port mode!

HDL — 33
Entity: Example
8
inputs
3 Mux8to1 output
Select_s

entity Mux8to1 is
port (
Inputs : in Std_Logic_Vector(7 downto 0);
Select_s : in Std_Logic_Vector(2 downto 0);
Output : out Std_Logic
);
end Mux8to1;

HDL — 34
Architecture Body
 Describes the operation of the component, Not just
its interface
 It describes the underlying functionality of the entity
and contains the statements that model the behavior
of the entity.

 More than one architecture can (and usually) is

associated with each entity

 Each architecture suited to different type of modeling

 E.g., a behavioral arch., a structural arch, a RTL arch.

35
Architecture Body (II)
 Consists of Two Parts
1. Declarative part -- includes necessary declarations,
e.g.

Type declarations

Signal declarations

Component declarations

Subprogram declarations
2. Statement part -- includes statements that describe
organization and/or functional operation of
component, e.g.

Concurrent signal assignment statements

Process statements

Component instantiation statements

36
 Architecture Body, e.g. The
architecture
name

ARCHITECTURE structural OF full_adder IS

-- architecture declarative part
Declarative Part
SIGNAL xor_res : BIT ;
-- architecture statement part
BEGIN
cout <= (x AND y) OR (x AND cin) OR (y
Statement Part
AND cin) ;
xor_res <= x XOR y ;
sum <= xor_res XOR cin; The Entity
name

END structural ;
End of
architecture

37
VHDL Description of Combinational Networks

38
 Lexical Elements of VHDL
 Comments

two dashes to end of line is a comment, e.g.,
--this is a comment
 Basic Identifiers

Can Only Use

alphabetic letters ( A-Z, a-z ), or

Decimal digits ( 0-9 ), or

Underline character ( _ )

Not case sensitive
( LastValue = = lAsTvALue)
 Reserved Words

Do not use as identifiers
 Special Symbols

Single characters
& ‘ ( ) * + , - . / : ; < = > |

Double characters (no intervening space)
=> ** := /= >= <= <>

Copyright  1997, KJH

39
Identifiers
 Identifiers are used to name items in a
VHDL model
 may only contain alphabetic letters (‘A’ to
‘Z’ and ‘a’ to ‘z’), decimal digits (‘0’ to ‘9’)
and the underline character (‘_’);
 must start with an alphabetic letter;
 may not end with an underline character;
and
 may not include two successive underline
characters.
40
Examples of identifiers
 Some examples of valid basic identifiers are

A

X0

counter

Next_Value

generate_read_cycle
 Some examples of invalid basic identifiers are

last@value –– contains an illegal character for an identifier

5bit_counter –– starts with a nonalphabetic character

_A0 –– starts with an underline

A0_ –– ends with an underline

clock__pulse –– two successive underlines

41
Reserved Words
we cannot use reserved words as identifiers for items we define

Reserved words in VHDL

abs disconnect is out sli
access downto label package sra
after else library port srl
alias elsif linkage postponed subtype
all end literal procedure then
and entity loop process to
architecture exit map pure transport
array file mod range type
assert for nand record unaffected
attribute function new register units
begin generate next reject until
block generic nor return use
body group not rol variable
buffer guarded null ror wait
bus if of select when
case impure on severity while
component in open signal with
configuration inertial or shared xnor
constant inout others sla xor

42
Strings
 Bit Strings
 B for binary ( b”0100_1001” )
 O for Octal ( o”76443” )
 X for hexadecimal ( x”FFFE_F138” )

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