Operators and Attributes

Dr. Hakem Beitollahi

Computer Engineering Department

Elmo Sanat University
Outline
 Concatenation
 Aggregate
 Alias
 Operators
 Attributes

—2
 Concatenation

architecture EXAMPLE_1 of CONCATENATION is

signal BYTE : bit_vector (7 downto 0);
signal A_BUS, B_BUS : bit_vector (3 downto 0);
begin
BYTE <= A_BUS & B_BUS;
end EXAMPLE;

3
 Aggregate (I)
 A basic operation that combines one or more values into a composite
value of a record or array type;
 Aggregates are a grouping of values to form an array or record expression.

Variable data_1 :Bit_vector(0 to 3) := (‘0’,’1’,’0’,’1’);

Variable data_1 :Bit_vector(0 to 3) := (1=>‘1’,0=>’0’, 3=>’1’,2=>’0’);


Signal data_Bus :std_logic_vector (15 downto 0)

data_Bus<=(15 downto 8 => ‘0’, 7 downto 0 =>’1’);


Signal data_Bus :std_logic_vector (15 downto 0)

data_Bus<=(14 downto 8 => ‘0’, others=>’1’);


Signal data_Bus :std_logic_vector (15 downto 0)

data_Bus<=(others=>’z’);


Type Status_record is record
Code: Integer;
Name: string(1 to 4);
End record;
Variable Status_var: Status_record :=(code=>57, name=>”MOVE”);

4
 Aggregate (II)
signal Z_BUS : bit_vector (3 downto 0);
signal A_BIT, B_BIT, C_BIT, D_BIT : bit;
...
Z_BUS <= (A_BIT, B_BIT, C_BIT, D_BIT);
signal Z_BUS : bit_vector (3 downto 0);
signal A_BIT, B_BIT, C_BIT, D_BIT : bit;
...
Z_BUS <= ( 2=> B_BIT, 1 => C_BIT, 0 => D_BIT, 3
=> A_BIT);
signal B_BIT : bit;
signal BYTE : bit_vector (7 downto 0);
...
BYTE<= (7 => '1', 5 downto 1 => '1', 6 => B_BIT,
others => '0'); type T_PACKET is record
BYTE_ID : std_logic;
PARITY : std_logic;
ADDRESS : integer range 0 to 3;
DATA : std_logic_vector (3 downto 0);
end record
signal TX_DATA : T_PACKET;
...
TX_DATA <= ('1', '0', 2, "0101");

5
Alias
Alias (I)
 Aliases can significantly improve the readability of
VHDL descriptions by using a shorthand notation for
names
 An alias is an alternative name for an existing object
(signal, variable or constant). It does not define a
new object.
 Aliases allow reference to named items in different
ways:
 Example:

Signal Instruction :Bit_vector(15 downto 0);

Alias OpCode : Bit_vector(3 downto 0) is Instruction(15 downto 12);

Alias Source : Bit_vector(1 downto 0) is Instruction(11 downto 10);

Alias design : Bit_vector(1 downto 0) is Instruction(9 downto 8);

Alias Immdata : Bit_vector(7 downto 0) is Instruction(7 downto 0);

7
Alias (II)
alias SIGN : bit is DATA(31);
alias BYTE_ID : bit is NET_DATA_IN(7);

alias OPERAND : bit_vector(1 downto 0)

is CPU_BUFFER(LOW) (4 downto 3);
alias A : bit_vector(3 downto 0)
is CPU_BUFFER(HIGH)(3 downto 0);
alias B : bit_vector(2 downto 0)
is CPU_BUFFER(LOW) (2 downto 0);

signal BUS_A :
std_ulogic_vector(7 downto 0);
alias BIT_REV_A :
std_ulogic_vector(0 to 7) is BUS_A;
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Operators in VHDL

—9
Operators in VHDL
 VHDL provides several kinds of pre-
defined operators:
 Assignment operators
 Logical operators
 Arithmetic operators
 Relational operators
 Shift operators
 Concatenation operators

— 10
Assignment Operators
 <= Used to assign a value to a SIGNAL.
 := Used to assign a value to a VARIABLE,
CONSTANT, or GENERIC.
 Used also for establishing initial values.
 => Used to assign values to individual
vector elements or with OTHERS.
 See an Example

— 11
Assignment Operators (Example)
SIGNAL x : STD_LOGIC;
VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Leftmost bit is MSB
SIGNAL w: STD_LOGIC_VECTOR(0 TO 7); -- Rightmost bit is MSB

x <= '1'; -- '1' is assigned to SIGNAL x using "<=“

y := "0000"; -- "0000" is assigned to VARIABLE y using ":=“

w <= "10000000"; -- LSB is '1', the others are '0‘

w <= (0 =>'1', OTHERS =>'0'); -- LSB is '1', the others are '0'

— 12
Logical Operators
 Used to perform logical operations
 The data must be of type BIT, STD_LOGIC
 NOT
 AND
 OR
 NAND
 NOR
 XOR
 XNOR

— 13
Logical Operators (Example)

y <= NOT a AND b; -- (a'.b)

y <= NOT (a AND b); -- (a.b)‘

y <= a NAND b; -- (a.b)'

— 14
 Arithmetic Operators
 Used to perform arithmetic operations.
 The data can be of type INTEGER, SIGNED, UNSIGNED, or REAL
 + Addition //no synthesis restrictions [binary operator]
 - Subtraction //no synthesis restrictions [binary operator]
 * Multiplication //no synthesis restrictions [binary operator]
 / Division //Only power of two dividers (shift operation) are allowed for synthesis [binary
operator]
 ** Exponentiation //only constant values of base are accepted for synthesis. [binary
operator]
 MOD Modulus //y mod x returns the remainder of y/x with the signof x [binary
operator] [Synthesizable when either y and x be constant or x be power of 2]
 REM Remainder //y rem x returns the remainder of y/x with the signof y [binary
operator] [Synthesizable when either y and x be constant or x be power of 2]
 ABS Absolute value //returns the absolute value. With respect to the last three
operators (mod, rem, abs), [unary operator]

— 15
Arithmetic Operators (Examples)
2 ** 8 = 256
variable A,B :Integer;
3.8 ** 3 = 54.872
variable C : Real;
4 ** (-2) = 1 / (4**2) = 0.0625
C:= 12.34 * ( 234.4 / 43.89 );
A:= B mod 2;

signal INT1, INT2: integer := 0;

signal REAL1, REAL2: real := 6.7;
...
INT1 <= INT1 + 3;
REAL1 <= REAL2 - 2.2;
INT2 <= INT1 * REAL1; --illegal
INT2 <= INT1 * INTEGER(REAL1);
REAL2 <= REAL1 / 42.3;

— 16
 Difference between rem and mod in
VHDL
 mod & rem operate on integers & result is integer
 rem has sign of 1st operand and is defined as:
A rem B = A – (A/B) * B
 mod has sign of 2nd operand and is defined as:
A mod B = A – B * N -- for an integer N
 Note the absolute value of (A mod B) must be less than the
absolute value of B.

5 rem 3 = 2 7 mod 4 = 3
5 mod 3 = 2 -7 mod 4 = 1
7 mod (-4) = –1
(-5) rem 3 = -2
-7 mod (-4) = –3
(-5) mod 3 = 1

(-5) rem (-3)= -2

-7 mod 4 = -7 -4*N  N can only
(-5) mod (-3)= -2
be -2 and mode be 1. The absolute of mod is less than 4.
Also mod has the sign
5 rem (-3)= 2
of second operand
5 mod (-3)= -1 — 17
Comparison Operators
 Used for making comparisons
 The data can be of any of the types
 = Equal to
 /= Not equal to
 < Less than
 > Greater than
 <= Less than or equal to
 >= Greater than or equal to

— 18
Shift Operators
 Used for shifting data
 sll shift left logical (fill value is ‘0’)
 srl shift right logical (fill value is ‘0’)
 sla shift left arithmetic (fill value is right-hand bit)
 sra shift right arithmetic (fill value is left-hand bit)
 rol rotate left
 ror rotate right
 All operators have two operands [ binary operator]:
 <left operand> <shift operation> <right operand>
 left operand is bit_vector to shift/rotate
 right operand is integer for # shifts/rotates
 - integer same as opposite operator with + integer

— 19
Note
 The VHDL arithmetic left shift operator is unusual. Instead of filling
the LSB of the result with zero, it copies the original LSB into the
new LSB. While this is an exact mirror image of the arithmetic right
shift, it is not the conventional definition of the operator, and is not
equivalent to multiplication by a power of 2.

 In the VHDL 2008 standard this strange behavior was left

unchanged (for backward compatibility) for argument types that do
not have forced numeric interpretation (e.g., BIT_VECTOR) but ‘sla'
for unsigned and signed argument types behaves in the expected
way (i.e., rightmost positions are filled with zeros). VHDL's shift left
logical (sll) function does implement the aforementioned 'standard'
arithmetic shift.

— 20
Shift Operators (example)

“1100” sll 1 yields “1000”

“1100” srl 2 yields “0011”
“1100” sla 1 yields “1000”
“1100” sra 2 yields “1111”
“1100” rol 1 yields “1001”
“1100” ror 2 yields “0011”
“1100” ror –1 same as “1100” rol 1

— 21
Check Yourself
SIGNAL a : BIT := '1';
SIGNAL b : BIT_VECTOR (3 DOWNTO 0) := "1100";
SIGNAL c : BIT_VECTOR (3 DOWNTO 0) := "0010";
SIGNAL d : BIT_VECTOR (7 DOWNTO 0);

x1 <= a & c; -> x1“10010”

<=
x2 <= c & b; -> x2“11100”
<=
x3 <= b XOR c; -> x3 “1110”
<=
x4 <= a NOR b(3); -> x4 ‘0’
<=
x5 <= b sll 2; -> x5“0000”
<=
x6 <= b sla 2; -> x6 “0011”
<=
x7 <= b rol 2; -> x7 “0011”
<=
x8 <= a AND NOT b(0) AND NOT c(1); -> x8‘0’ <=
d <= (5=>'0', OTHERS=>'1'); -> d<=
“11011111”
— 22
Attributes

23
Attributes (I)
 Language defined attributes return information
about certain items in VHDL
 Types, subtypes
 Procedures, functions
 Signals, variables, constants
 Entities, architectures, configurations, packages
 Components
 VHDL has several predefined attributes that are
useful to the designer
 Attributes can be user-defined to handle custom
situations (user-defined records, etc.)

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 Attributes (II)
 Signal Attributes
 General form of attribute use is:
<name> ' <attribute_identifier>

 Some examples of signal attributes

X'EVENT -- evaluates TRUE when an event on signal X has just occurred.
X'LAST_VALUE -- Returns the value of X before the last event
X'STABLE -- evaluates TRUE when no event has occurred on signal X
X’ACTIVE -- Returns true if X = ‘1’
X’LAST_ACTIVE --Returns the time elapsed since last X = ‘1’
X’LAST_EVENT --Returns the time elapsed since last event
X’QUIET <time> --Returns true if no event has occurred during the time specified

25
Attributes (III)
 All four assignments shown below are
synthesizable and equivalent

 IF (clk'EVENT AND clk='1')... -- EVENT attribute used with IF

 IF (NOT clk'STABLE AND clk='1')... -- STABLE attribute used with IF
 WAIT UNTIL (clk'EVENT AND clk='1'); -- EVENT attribute used with WAIT
 IF RISING_EDGE(clk)... -- call to a function

— 26
Attributes (IV)
 Value Attributes
'LEFT -- returns the leftmost value of a type

'RIGHT -- returns the rightmost value of a type

'HIGH -- returns the greatest value of a type

'LOW -- returns the lowest value of a type

'LENGTH -- returns the number of elements in a constrained array

'RANGE -- returns the range of an array

d’REVERSE_RANGE: Returns vector range in reverse order

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Attributes (V)
SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0);

d'LOW=0,

d'HIGH=7,

d'LEFT=7,

d'RIGHT=0,

d'LENGTH=8,

d'RANGE=(7 downto 0),

d'REVERSE_RANGE=(0 to 7).

— 28
Attributes (Example)
 SIGNAL x: STD_LOGIC_VECTOR (0 TO 7);
 Then all four LOOP statements below are
synthesizable and equivalent


FOR i IN RANGE (0 TO 7) LOOP ...

FOR i IN x'RANGE LOOP ...

FOR i IN RANGE (x'LOW TO x'HIGH) LOOP ...

FOR i IN RANGE (0 TO x'LENGTH-1) LOOP ...

— 29
 Attributes (VI)
 Example
TYPE count is RANGE 0 TO 127;
TYPE states is (idle, decision,read,write);
TYPE word is ARRAY(15 DOWNTO 0) of bit;

count'left = 0 states'left = idle word'left = 15

count'right = 127 states'right = write word'right = 0
count'high = 127 states'high = write word'high = 15
count'low = 0 states'low = idle word'low = 0
count'length = 128 states'length = 4 word'length = 16

count'range = 0 TO 127
word'range = 15 DOWNTO 0

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Check Yourself
SIGNAL a : BIT := '1';
SIGNAL b : BIT_VECTOR (3 DOWNTO 0) := "1100";
SIGNAL c : BIT_VECTOR (3 DOWNTO 0) := "0010";
SIGNAL d : BIT_VECTOR (7 DOWNTO 0);

c'LOW -> 0
d'HIGH -> 7
c'LEFT ->3
d'RIGHT ->0
c'RANGE ->3 DOWNTO 0
d'LENGTH -> 8
c'REVERSE_RANGE -> 0 TO 3

— 31
 Check Yourself
Verify whether each of the operations below is legal or illegal.
Briefly justify your answers.

b(0) AND a --Legal

a + d(7) --illegal
NOT b XNOR c --Legal
SIGNAL a : BIT := '1'; c + d --illegal
SIGNAL b : BIT_VECTOR (3 DOWNTO 0) := "1100"; e - f --Legal
IF (b<c) ... --Legal
SIGNAL c : BIT_VECTOR (3 DOWNTO 0) := "0010"; IF (b>=a) ...--illegal
SIGNAL d : BIT_VECTOR (7 DOWNTO 0); IF (f/=e) ... --Legal
SIGNAL e : INTEGER RANGE 0 TO 255; IF (e>d) ... --illegal
b sra 1 --Legal
SIGNAL f : INTEGER RANGE -128 TO 127; c srl -2 --Legal
f ror 3--illegal
e*3 --Legal
5**5 --Legal
f/4 --Legal
e/3 --Legal
d <= c --illegal
d(6 DOWNTO 3) := b --illegal
e <= d--illegal
f := 100 --illegal
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