MODULE – 2

Addressing Modes & Instruction Set

Instruction Syntax
• Every instruction of a program has to operate on a data. Every
instruction consists of two parts :- opcode & operand.
• Opcode
It is the operational code which contains all the information about
which operation is to be performed.
Operand
It is a data on which the operation is to be performed.
Source
AGAIN : MOV R1, A ; Copy the contents of A to R1

Label Destination Comment

• The CPU can access data in many ways. The data can be
in register or in memory or as an immediate value or I/O
port.
• The various ways of accessing the data are called
Addressing Modes.
• Different Addressing Modes :-
1) Immediate addressing mode
2) Register addressing mode
3) Direct addressing mode
4) Indirect addressing mode
5) Indexed addressing mode
6) Relative addressing mode
7)Absolute addressing mode
8)Long addressing mode
Immediate Addressing Mode
• The source operand is a constant.
• The immediate data must be preceded by the pound sign “ # ”
• This addressing mode can be used to load information into any
of the registers R0-R7 , A , DPTR and ports.
• EXAMPLES:
MOV A, # 0FFH
MOV R4, #0AH
MOV B, #10H
MOV DPTR, #1234H
MOV DPTR , # 0123H
MOV P1,#55H
Register Addressing Mode
• It involves the use of registers to hold the data .
• The registers A, DPTR , R0 – R7 can be used as source as well as
destination.
• Registers are in any one of the four register banks which are selected
by bits 3 & 4 of PSW (RS1,RS0) . On reset default register Bank 0 is
selected.
• MOV R4, R7 is invalid (Because movement of data between
registers is not allowed)
• EXAMPLES:
MOV A, R0
MOV R2, A
ADD A, R5
MOV R7, DPL
MOV R6, DPH
Direct Addressing Mode
• The data in RAM memory location has address which is given as a part of
the instruction.
• All 128 Bytes of internal RAM & SFRs can be accessed using direct
addressing mode.
• Internal RAM uses addresses 00 h to 7Fh(128 Bytes) to address each byte.
SFR addresses exist from 80h to FFh (128 Bytes) .
• The “ # ” sign distinguishes between immediate & direct addressing modes.
• EXAMPLES :
MOV R0, 40H MOV P1,A
MOV 56H, A OR
MOV R7, 01H MOV 90H, A
PUSH 0E0H
POP 03H
MOV A, 07h
Indirect Addressing Mode
• Register is used to hold address of the data.
• The mnemonic symbol used for indirect addressing mode is “@”.
• R0 & R1 are the only registers used as pointers in this addressing
mode to access any information in the internal RAM.

• EXAMPLES:
MOV A, @R0
MOV @R1,B
MOV @R1,A
MOV 20H, @R1
MOV @R0, 03H
Indexed Addressing Mode
• It is widely used in accessing data elements of look-up table entries
located in the program ROM space.
• Either DPTR or PC can be used as an Indexed register & only program
memory can be accessed in Index Addressing Mode.

• The instructions used for this purpose is

1) MOVC A, @A +DPTR
Add contents of accumulator with the contents of DPTR to form program
code memory location address. Move the contents of this external
memory address to the accumulator.
2) MOVC A, @A+PC
Add contents of accumulator with the contents of PC to form program
code memory location address. Move the contents of this external
memory address to the accumulator.
Relative Addressing Mode
• It is also called as Program Counter Relative Addressing.
• Used only with certain jump and CALL instructions.
• There is offset address (8 bit) + Program Counter address =
Physical address of the memory location
• Example :
• JC OFFSET (Jump if carry flag is set)
• Here the program control is transferred to the memory location
having address PC+ OFFSET
Absolute Addressing Mode
• Used only with two instructions ie., Absolute Call (A CALL) &
Absolute Jump (A JMP)
• These instruction perform branching within the current 2 K
page of program memory.
• Branch Address : 5 bits of PC
3 bits of opcode
Second byte of instruction(operand)
Example:
1) AJMP NEXT; executes the instruction at label NEXT after
execution of the current instruction
2)ACALL SUB1; Calls the subroutines that is started at the label
SUB1
Long Addressing Mode
It is used with only two instructions
1)LCALL add 16
2) LJMP add 16
It requires three bytes : 1st byte for opcode
2nd byte for higher order address
3rd byte for lower order address
Microcontroller can take memory space of 64K bytes of program
memory.
External Data Moves
• MOVX A,@Rp----Copy the contents of external address in
Rp to A
• MOVX A,@DPTR---Copy the contents of external address
in DPTR to A
• MOVX @Rp, A------Copy the data from A to external
address in Rp
• MOVX @DPTR,A----Copy the data from A to the external
address in DPTR

1)All external data moves must involve A register.

2) Rp can address 256 bytes ;DPTR can address 64k
bytes.
3)MOVX is used with external RAM or I/O addresses.
Code Memory Read-Only Data Moves
• MOVC A,@A+DPTR------Copy the code byte found at
external ROM address formed by adding A and DPTR to A
• MOVC A,@A+PC----------Copy the code byte found at the
external ROM address formed by adding A and PC to A.
Example:
MOV DPTR ,#1234H-----Copy the immediate no 1234h to
DPTR
MOV A,#56H----------Copy the immediate no 56h to A
MOVC A,@ A+DPTR----Copy the contents of address 128Ah to
Accumulator
MOVC A,@A+PC------Copy the content of address 4059 to A if
PC contains 4000h & A contains 58h .
PUSH and POP Opcodes
• SP is incremented by 1 before the data is copied to
internal RAM location and stack grows in memory as it is
PUSHed. PUSH opcode copies data from the source
address to the stack.
• POP opcode first copies the data from the stack to the
destination address and then decremented by 1.
EXAMPLE
MOV 81H,#30H ; Copy immediate data 30h to SP
MOV R0,#0ACH ; Copy immediate data ACH to R0
PUSH 00H ;SP=31h,address 31h contains number ACH
PUSH 00H ;SP=32h,address 32h contains number ACH
POP 01H ;Register R1contains number ACH SP=31H
POP 80H ;Port 0 latch contains number ACH SP=30H
Instruction Set

8051 instruction set is classified as :

1) Data transfer instructions

2) Arithmetic instructions
3) Logical instructions
4) Bit manipulation instructions
5) Branch instructions
6) Subroutine instructions
Data Transfer Instructions
Data transfer operation copies the data from source to
destination location.
The content of source is not deleted during the process.

3 types of data transfer instructions

1) MOV
2) PUSH and POP
3) XCH
a) Move the contents of a register Rn to Accumulator
n 0 to 7
MOV A, R2
MOV A, R7
b) Move the contents of A to Rn
MOV R4,A
MOV R1,A
C) Move an immediate 8-bit data to register A , Rn, DPTR or to
memory location (direct or indirect)
MOV A,#45H MOV @R0, #0E8H
MOV R6,#56H MOV DPTR,#0F5A2H
MOV 30H,#44H MOV DPTR,#5467H
d) Move the contents of a memory location to A or A to a
memory location( direct or indirect )
MOV A ,65H MOV 45H,A
MOV A,@R0 MOV @R1,A
e) Move the contents of a memory location to Rn or
Rn to a memory location (direct)
MOV R3,65H
MOV 45H,R2
f) Move the contents of memory location to another memory
location (direct and indirect)
MOV 47H,65H
MOV 45H, @R0
g) Move the contents of an external memory to A or A to an
external memory
MOVX A,@R1 MOVX A,@DPTR
MOVX @R0,A MOVX @DPTR,A

h) Move the contents of program memory to Accumulator

MOVC A,@A+PC
MOVC A,@A+DPTR
PUSH and POP Instructions
 These instructions are related to stack.
Stack is a block of memory location used to store temporary
data.
Push used for storage and POP for retrieving the data.
Exchange Instructions
•Exchange instruction move the data in two directions: from source to
destination & from destination to source.
•All addressing modes except immediate may be used in XCH
instruction.
•Content of source i.e, register, direct memory ,indirect memory will be
exchanged with contents of destination i.e, Accumulator
XCH A,R3 Register
XCH A,@R1 Indirect
XCH A, 54H Direct
•All exchanges are internal to the 8051 microcontroller.
•All exchanges use register A.
•When using instruction XCHD ,the upper nibble of A and the upper
nibble of the address location in Rp do not change. Only the lower
nibbles are changed.
XCHD A,@R1
XCHD A,@R0
Exchange Digit Instruction (XCHD)
Accumulator is 8-bit register A0 to A7
NIBBLE - A group of 4 bits

A0-A3(Lower Nibble) A4-A7(Higher Nibble)

Internal RAM

Indirectly addressed by a register

Arithmetic Instructions
• Arithmetic instructions can perform addition,
subtraction, multiplication, division, increment,
decrement operations on 8-bit numbers.
Incrementing and Decrementing
• Register, Direct, Indirect addressing modes can be
used
• Increment operation (INC) increases the operand by
one and decrement operation (DEC) decreases the
operand by one.
• C,AC,OV Flags are not affected.
• All 8-bit address contents overflow from FFh to
00h.
• The 8-bit address contents underflow from 00h
to FFh.
• DPTR is 16-bit and it overflows from FFFFh to
0000h.
• There is no DEC DPTR as in case of INC
DPTR.
 Mnemonic Operation
•INC A ---- Add 1 to A register
•INC Rr ----- Add 1 to register Rr

•INC add ---- Add 1 to contents of direct memory address

INC @Rp ---Add 1 to the contents of mem. address in Rp
•INC DPTR---Add 1 to 16-bit DPTR

•DEC A---Subtract 1 from register A

•DEC Rr---Subtract 1 from register Rr
•DEC add--Subtract 1 from contents of direct mem address
•DEC @Rp- Subtract 1 from contents of mem. address in Rp
EXAMPLE
MOV A , # 3Ah-------- A=3Ah
Dec A ---------------------A=39h
MOV R0,#15h -----------R0=15h
MOV 15h,#12h -------Internal RAM address 15h=12h
INC @R0 ---------------Internal RAM address 15h=13h
DEC 15h ---------------Internal RAM address 15h=12h
INC R0 ------------------R0=16h
MOV 16h, A -------------Internal RAM address 16h = 39h
INC @R0 ------------------Internal RAM address 16h = 3Ah
MOV DPTR,#12FFh ------DPTR = 12FFh
INC DPTR------------------ DPTR =1300h
DEC 83h ----------------------DPTR =1200h (SFR 83h is DPH
byte)
Addition Operation
Immediate data
Accumulator + Register = Accumulator
Memory location
1)Add the contents of A with immediate data with or without
carry
ADD A, # 45h
ADDC A,#0B4h
2)Add the contents of A with register Rn with or without carry
ADD A,R5
ADDC A, R2
3) Accumulator with memory location
ADD A,51H
ADDC A,75H

ADD A, @R1
ADDC A, @R0

Flags affected during Addition operation

1)CY –CARRY FLAG
2) AC--- AUXILIARY CARRY
3) OV-----OVERFLOW FLAG
Example of ADD and ADDC
• MOV A, #1CH ----------- A=1Ch
• MOV R5, #0A1h------ R5= A1h
• ADD A, R5 -------A=1C+A1= BDh, C=0 , OV=0
• ADD A, R5----A= BD+A1= 5Eh, C=1,OV=1
• ADDC A, # 10h -----A=6Fh,C =0,0V=0
• ADDC A, # 10h ------A= 7Fh,C=0,OV=0
Subtraction Operation
• Register A is the destination location.
• All four addressing modes can be used .
• The commands treat carry flag as borrow and subtract
carry flag as part of the operation.
• Steps to execute SUBB instruction for unsigned
numbers :
1)Take 2’s complement of the subtrahend (source
operand).
2) Add it to the minuend(A).
3) Invert the carry.
1) Contents of A subtracted with immediate data with
or without borrow
SUBB A, #45H
SUBB A, #0BH
2) Subtract the contents of A with register Rn with or
without borrow
SUBB A,R5
SUBB A,R2
3) Subtract the contents of memory location
SUBB A, 51H--------Direct addressing
SUBB A, @R0--------Indirect addressing
Subtraction of unsigned numbers
SUBB (subtract with borrow ) when CY=0
If CY=0 after executing SUBB instruction, the result is
positive.
If CY=1 after executing SUBB instruction, the result is
negative & destination has 2’s complement of the result.

SUBB (subtract with borrow ) when CY=1

This instruction is used for multi byte numbers and takes
care of the borrow of the lower operand.
If CY=1 prior to executing the SUBB instruction, it also
subtracts 1 from the result.
Signed Numbers
In signed byte operands, D7 (MSB) is the sign and
D0 – D6 are for the magnitude of the number.
If D7=0 ,the operand is positive.
If D7=1, the operand is negative.
Positive signed number : 0 to +127
Negative signed number : -1 to -128
Signed number range : -128 to +127
Steps to convert the negative no. (2’s complement
method):-
1)Write the magnitude of the no in 8 bit binary (no sign).
2) Invert each bit.
3)Add 1 to it.
Flags affected:
C flag – is set if borrow is needed into bit 7 and reset
otherwise.
AC flag –is set if borrow is needed into bit 3 and reset
otherwise.
OV flag ---is set if there is borrow into bit 7 and not
bit 6 or if there is borrow into bit 6 and not bit7.
Sometimes OV=1 indicates that the result exceeds the
range -128 to +127.
In any signed number addition OV indicates the result
is valid or not.
If OV=1(result is erroneous); OV=0 (result is valid)
EXAMPLE

MOV 0D0H,#00H ; carry flag =0

MOV A,#3AH ; A=3AH
MOV 45H,#13H ; 45H= 13H
SUBB A,45H ; A=27H,C=0,OV=0
SUBB A,45H ; A=14H,C=0,0V=0
SUBB A,#80H ; A=94H,C=1, OV=1
SUBB A,#22H ; A=71H, C=0,OV=0
SUBB A,#0FFH ; A=72H , C=1,OV=0
Multiplication Operation
• Uses registers A and B as both source and destination
addresses.
• Unsigned number in register A is multiplied with unsigned no.
in register B (Range 0 to 255 in decimal / 00 to FFH)

• OV flag is set if A X B > FFH (255 in decimal )indicates the

number is larger than 8 bits.

• Carry flag is always reset. (C =0)

MUL AB ----Multiply A by B & put the lower byte of product

in A and higher byte in B.
Example

•MOV A,#7BH----------------A=7BH
•MOV 0F0H, #02H-----------B=02H
•MUL AB----------------------AXB =7BH X 02H= 00F6H
A=F6H, B=00H ,OV Flag=0
•MOV B, #0FEH--------------B= FEH
•MUL AB-----------------------AXB=F6H X FEH = F414H
A=14H, B=F4H, OV=1
Division Operation
• Division operation uses registers A and B as both source and
destination.
• Unsigned number in A is divided by unsigned number in B
register.
• DIV AB -----Divide A by B and put integer part of quotient in
register A and integer part of remainder in B register.

• OV, C flag set to zero.

• When division by zero ,the contents of A and B are undefined

& Carry Flag = 0, OV=1
EXAMPLE

MOV A, #0FFH---------------A=0FFH
•MOV 0F0H,#2CH-------------B=02CH
•DIV AB-----------------------A = 05H, B = 23H
•DIV AB--------------------- A=00H, B=05H
•DIV AB------------------------A= 00H, B = 00H
•DIV AB-----------------------A=??, B=??, OV=1
Decimal Arithmetic
• Decimal adjust accumulator for addition ( DA A)

• It is used after addition of BCD numbers to convert

the result back to BCD.

• The data is adjusted in two cases.

1) It adds 6 to the lower nibble (4-bits) of A if it is
greater than 9 or if AC=1
2) It adds 6 to the higher nibble of A if it is greater
than 9 or if C=1
BCD(Binary Coded Decimal) Number
System
• Binary representation of 0 to 9 is called BCD.
Unpacked BCD
 The lower 4 bits of the number represents the BCD
number and the upper 4 bits are zeros.
 Example : 0000 1001 – unpacked BCD value of 9
0000 0101 - unpacked BCD value of 5
Packed BCD
 A single byte has two BCD numbers in it. One in the lower
4 bits and one in the upper 4 bits.
 Example : 0101 1001- Packed BCD value for 59H
EXAMPLE
• MOV A,#42H-------------------A=42 BCD
• ADD A,#13H-------------------A=55H,C=0
• DA A----------------------------A=55H,C=0
• ADD A,#17H-------------------A=6CH,C=0
• DA A--------------------------A=72 BCD,C=0
• ADDC A,#34H----------------A=A6H, C=0
• DA A--------------------------A=06BCD ,C=1
• ADDC A,#11H----------------A=18 BCD, C=0
• DA A---------------------------A=18 BCD, C=0
Logical Instructions
Byte –Level Logical Operations
•Use all four addressing modes for the source of the
data byte.
•A register or direct address in internal RAM is the
destination.
•These operations are done using each individual bit of
the destination & source bytes.
•Since the entire byte is affected these are called
Byte –Level Logical operations.
•No flags are affected unless the direct address is the
PSW.
Logical AND
ANL destination (8 bit), source(8 bit)
ANL A,# Data ANL Direct, A
ANL A , Direct ANL direct, # Data
ANL A , Rn
ANL A, @Rp

Logical OR
ORL destination(8 bit), source(8 bit)
ORL A,# Data ORL Direct, A
ORL A , direct ORL Direct, #Data
ORL A , Rn
ORL A, @Rp
Logical EX-0R
XRL destination, source
XRL A,# Data XRL Direct,#Data
XRL A, Direct XRL Direct, A
XRL A, Rn
XRL A , @Rp

Logical NOT
CPL A ----Complements the operand and stores the result in
operand
CPL A
CPL C
CPL bit address
Example for byte level logical operation
• MOV A,# 0FFH-----------------A=FFH
• MOV R0, #77H-----------------R0=77H
• ANL A, R0------------------------A=77H
• MOV 15H, A----------------------15H=77H
• CPL A-------------------------------A=88H
• ORL 15H,#88H------------------15H=FFH
• XRL A,15H-------------------------A=77H
• XRL A, R0------------------------A=00H
• ANL A,15H-------------------------A=00H
• ORL A,R0--------------------------A=77H
• CLR A-------------------------------A=00H
• XRL 15H,A-------------------------15H=FFH
• XRL A,R0----------------------------A=77H
Bit-Level Logical operations
Internal RAM Bit Addresses
Byte Address(Hex) Bit Address(Hex)
20--------------------------------------------------------------- 00- 07 (8 Bits)
21----------------------------------------------------------------- 08-0F
22----------------------------------------------------------------- 10-17
23---------------------------------------------------------------- 18-1F
24---------------------------------------------------------------- 20-27
25---------------------------------------------------------------- 28-2F
26---------------------------------------------------------------- 30-37
27---------------------------------------------------------------- 38-3F
28---------------------------------------------------------------- 40- 47
29---------------------------------------------------------------- 48-4F
2A---------------------------------------------------------------- 50-57
2B---------------------------------------------------------------- 58-5F
2C---------------------------------------------------------------- 60-67
2D---------------------------------------------------------------- 68-6F
2E---------------------------------------------------------------- 70-77
2F---------------------------------------------------------------- 78-7F
INTERNAL RAM
SFR Bit Addresses

SFR Direct Address (Hex) Bit Addresses(Hex)

A 0EO 0E0 – 0E7
B 0F0 0F0 – 0F7
IE 0A8 0A8 – 0AF
IP 0B8 0B8 – 0BF
P0 80 80 – 87
P1 90 90 – 97
P2 0A0 0A0 – 0A7
P3 0B0 0B0 – 0B7
PSW 0D0 0D0 – 0D7
TCON 88 88 – 8F
SCON 98 98 – 9F
Bit- Level Boolean operations
• These opcodes operate on any addressable RAM or SFR bit.

• Carry flag ( C) in the PSW special function register is the

destination because the flag can be tested .

• The bit instructions that can use a SFR latch bit are:-
CLR, CPL, MOV, SETB
Bit Manipulation Instructions
Mnemonic Operation
 ANL C, b------------AND C & the addressed bit ,put the result in C
ANL C, /b -----------AND C & the complement of the addressed bit, put the
result in C ,the addressed bit is not altered
ORL C, b
ORL C, /b
CPL C--------------Complement the C flag
CPL b---------------Complement the addressed bit
CLR C -----------------Clear the carry flag to zero
CLR b ------------------Clear the addressed bit to zero
MOV C, b----------Copy the addressed bit to the C flag
MOV b, C-----------Copy the C flag to the addressed bit
SETB C------------Set the C flag to 1
SETB b---------------Set the addressed bit to 1
EXAMPLE
SETB 00h----------------Bit 0 of RAM byte 20h=1
MOV C,00h--------------C =1
MOV 7Fh, C -----------Bit 7 of RAM byte 2Fh =1
ANL C, / 00H-------------C=0, bit 0 of RAM byte 20h = 1
ORL C, 00H-------------- C=1( 0+1=1)
CPL 7Fh--------------------Bit 7 of RAM byte 2Fh =0
CLR C----------------------C=0
ORL C, / 7Fh------------C=1 , Bit 7 of RAM byte 2FH=0

(0+1=1)
Rotate & Swap Operations
• RL A--------Rotate Accumulator Left
• RLC A------ Rotate Accumulator Left through Carry
• RR A----------Rotate Accumulator Right
• RRC A----------Rotate Accumulator Right through
Carry

• SWAP A-------Interchange the nibbles of register A

Put the higher nibble in lower nibble position & lower
nibble in higher nibble position
Example
• MOV A, # 0A5H-----------A =10100101b =A5h
• RR A---------------------------A= 11010010b = D2h
• RR A---------------------------A =01101001b = 69h
• RR A---------------------------A=10110100b = B4h
• RR A---------------------------A=01011010b= 5Ah
• SWAP A------------------------A=10100101b= A5h
• CLR C---------------------------C=0,A=10100101= A5h
• RRC A---------------------------C=1, A=01010010b= 52h
• RRC A-------------------------- C=0,A=10101001b= A9h
• RL A-----------------------------A=01010011b=53h
• RL A-----------------------------A=10100110b = A6h
• SWAP A-------------------------C=0,A =01101010b= 6Ah
• RLC A---------------------------C=0, A=11010100b= D4h
• RLC A---------------------------C=1,A=10101000b =A8h
• SWAP A ------------------------C=1, A=10001010b = 8Ah
Branch Instructions
Decision Codes
Some codes that alter the program flow & change the content of PC (Program
Counter) are referred as Decision Codes.
EXAMPLE : JUMP, CALL
RANGE :
Difference in bytes of the new address from the address in the
program where the JUMP & CALL is located.
1) Relative Range
2) Short Absolute Range
3) Long Absolute Range

RELATIVE RANGE
•Jumps that replace the PC contents with a new address that is
greater than the address of the instruction following the jump by
127d or less than the address of the instruction following the
jump by 128d are called RELATIVE JUMPS.
•Here the address that is placed in the PC is relative to the
address where the jump occurs.
RELATIVE
JUMP Address -128
(256 Bytes)
00-FFH
JUMP ADDRESS
PC NEXT INSTRUCTION -1

+127
ADVANTAGES
1) Only 1 byte of data need is specified either in
positive format for jumps ahead in the program or in 2’s
complement negative format for jumps behind.
2) It saves program bytes & speeds up the program
execution.
3) The program written using the relative range can be
located anywhere in the program address space without
reassembling the code to generate absolute address.
DISADVANTAGE
1) The addresses to be jumped should be within the
range -128 d to 127d .
Short Absolute Range

• Program Memory = 64K Bytes 32 Pages

16 bit address 2 K Bytes

1st five bits are Page No.

Next bits are address
PAGE No. ADDRESS(HEX) BINARY VALUE
(Starting Address)
•00 -------------- 0000 – 07FF ------- 0000 0000 0000 0000
•01 --------------- 0800 –0FFF------ 0000 1000 0000 0000
.
.
. (32 pages x 2 K B= 64 KB)
.
.
.
.

•1F ---------------- F800 – FFFF ----- 1111 1000 0000 0000

EXAMPLE

•ACALL < address 11 bit >

•AJMP < address 11 bit >
• 16-bit PC
5-bits 11-bits

•
Page no. Holds Address within the page

•2 Byte instruction = 8bits(1 BYTE) for ACALL or AJMP

+ 8 bits (1 BYTE for 11 bit address)
Long Absolute Range
• Addresses that can access the entire program space from
0000h to FFFFh are referred as LONG ABSOLUTE
RANGE.
0000 h
• 64 KB

FFFFh
LCALL < 16-bit address>------------3 Byte Instruction
LJMP < 16-bit address>------------ 3 Byte Instruction
JMP @ A+ DPTR-----------------------3 Byte Instruction
CONDITIONAL JUMP INSTRUCTIONS
1) Bit Jumps
 JC radd----Jump to relative address if C=1
JNC radd------Jump to relative address if C=0
JB b, radd--Jump to relative address if
addressable bit =1
JNB b, radd--Jump to relative address if
addressable bit =0
JBC b, radd---Jump to relative address if
addressable bit =1 and clear the addressable bit to
0.
2) Byte Jumps
 CJNE A, add, radd----Compare (A) ≠ (add) , jump to radd. Set the carry flag
to 1 (C=1) if A is less than content of direct address otherwise C=0.
CJNE A,#n, radd---Compare (A) ≠ #n , jump to radd. Set the carry flag to 1
(C=1) if A is less than the number otherwise C=0.

CJNE Rr,#n, radd

CJNE @Rp, #n, radd

DJNZ Rr , radd---Decrement register Rr by 1 & jump to relative address if

result is not zero.
DJNZ add, radd------Decrement the direct address by 1 & jump to radd if
the result is not 0. No flags are affected unless the direct address is the PSW.
JZ radd----Jump to relative address if A=0; the flags and A register are not
changed.
JNZ radd-------Jump to relative address if A is not zero ; the flags & A
register are not changed.
Unconditional Jump Instructions
Flags are unaffected

JMP @A +DPTR---Jump to address formed by adding A to

DPTR ; A, DPTR & Flags are unchanged.
 AJMP sadd ---Jump to absolute short range address sadd, no
flags are affected
LJMP ladd ----jump to absolute long range address ladd, no
flags are affected
SJMP radd ----jump to relative address radd, no flags are
affected
NOP ---------NO OPERATION
Limitations of addressing modes
1) Immediate Addressing Mode
The source operand is a constant rather than a variable value
 It is impossible to have immediate value as a destination.
MOV A,#52H ; MOV DPTR,#1234H

2) Register Addressing Mode

 It can move data between accumulator & Rn register
(n from 0 to 7) but movement of data between Rn registers is invalid
Ex: MOV R4, R7 -------- Invalid
MOV A, R5 ------------- Valid
MOV R6, A------------- Valid
MOV R7, DPH ; MOV R6,DPL------Valid
Advantage: Instruction length is small ie., single byte
instruction
Ex: MOV A,R3
ADD A ,R4
3) Direct Addressing Mode
Looping is not possible.
It can access only on-chip RAM & SFRs but can not
access external memory address.
The MSB of the address decides whether it is on-chip
RAM location (MSB=0) or SFR (MSB=1).
4) Indirect Addressing Mode
R0, R1, DPTR are the only registers used as pointers.
Ex: MOV A,@R0 ; ADD A,@R1 ; MOVX A,@DPTR