Unit 5:Pipline and

Vector Processing
By Vishva Gandhi
What is parallel processing?
• Parallel processing in pipelining refers to the concurrent execution of multiple instructions or
tasks within a pipeline. It involves dividing the work among multiple pipeline stages or multiple
independent pipelinesto achieve increased throughput and performance.
• Basic Pipeline Stages:
 Instruction Fetch (IF): Fetches the next instruction from memory.
 Instruction Decode (ID): Decodes the fetched instruction and reads operands.
 Execution (EX): Executes the instruction or computes the result.
 Memory Access (MEM): Accesses memory if needed (e.g., load/store operations).

 Single Instruction Multiple Data (SIMD):

 In SIMD parallel processing, multiple data elements are processed simultaneously
using the same instruction across different pipeline stages.
 For example, in a vector processing unit, multiple data elements are fetched,
decoded, executed, and written back simultaneously in each pipeline stage.
• Multiple Instruction Single Data (MISD):
 In MISD parallel processing, different instructions are executed simultaneously on the
same data in different pipeline stages.
 This approach is less common in traditional pipelined processors but can be found in
specialized architectures for specific applications.
What is pipline?
• In Computer Organization and Architecture (COA), pipelining refers to a technique used in
the design of modern CPUs to improve performance by executing multiple instructions
simultaneously in an overlapped fashion. It breaks down the execution of instructions into
discrete stages, allowing several instructions to be in different stages of execution at the
same time.
• Here’s how pipelining works Stages of an Instruction Cycle:
1. Fetch (IF - Instruction Fetch): The instruction is fetched from memory.
2. Decode (ID - Instruction Decode): The fetched instruction is decoded to understand
what needs to be done.
3. Execute (EX - Execute): The CPU performs the operation specified by the instruction.
4. Memory (MEM - Memory Access): Memory is accessed if needed, for read/write
operations.
5. Write Back (WB - Write Back): The result of the operation is written back to a register
Explain Arithmetic pipeline?

 An arithmetic pipeline divides an arithmetic problem into various subproblems for

execution in various pipeline arguments.
 It is used for floating operation, multiplexers, and various other complications.
 Floating point addition using arithmetic pipeline: -
1. To align the mantissa (to check the bits after the radix point).
2. Comparing the exponent (as if the exponents are different then operation cannot be
performed).
3. Find the difference of both exponents and after that, the difference will be added to the
base number having the least exponent.
4. Operation will be performed.
5. The number before the radix point should be 0 or less than 0, it cannot be greater than 0
(Normalization of the result).
Cont..
Explain Instruction pipeline?
 It can fetch instructions from memory.
 It can decode instructions.
 It can calculate effective addresses.
 It can fetch operands from memory.
 It can execute the instruction.
 It can save the result in a suitable place.
• Segment 1:The instruction fetch segment can be executed using a first-in, first-out (FIFO) buffer.
• Segment 2:The instruction fetched from memory is decoded in the second segment. The
effective address is computed in an independent arithmetic circuit.
• Segment 3:An operand from memory is fetched in the third segment.
• Segment 4:The instructions are finally implemented in the final segment of the pipeline
organization.
Cont…
Cont…
RISC pipeline vector processing.

• RISC stands for Reduced Instruction Set Computers. It was introduced to execute as fast as
one instruction per clock cycle. This RISC pipeline helps to simplify the computer
architecture’s design.
• Principles of RISCs Pipeline
 Keep the most frequently accessed operands in CPU registers.
 It can minimize the register-to-memory operations.

 It can use a high number of registers to enhance operand referencing and decrease the
processor memory traffic.
 It can optimize the design of instruction pipelines such that minimum compiler code
generation can be achieved.
Cont..
• It can use a simplified instruction set and leave out those complex and unnecessary
instructions.
 RISC (Reduced Instruction Set Computer) pipelining is a technique used in RISC-
based processor architectures to improve instruction throughput and overall
performance.
 In RISC architectures, instructions are typically designed to execute in a fixed
number of clock cycles, simplifying the instruction decoding and execution process.
 Pipelining in RISC architectures involves breaking down the execution of instructions
into multiple stages, each performed by a separate pipeline stage. Here's how RISC
pipelining works:
Cont…
Complex Instruction Set Architecture (CISC)

• The main idea is that a single instruction will do all

loading, evaluating, and storing operations just like a
multiplication command will do stuff like loading data,
evaluating, and storing it, hence it’s complex.
• Characteristics of CISC Processor
Following are the main characteristics of the RISC processor:
1. The length of the code is shorts, so it requires very little RAM.
2. CISC or complex instructions may take longer than a single clock cycle to execute the
code.
3. Less instruction is needed to write an application.
4. It provides easier programming in assembly language.
5. Support for complex data structure and easy compilation of high-level languages.
6. It is composed of fewer registers and more addressing nodes, typically 5 to 20.
7. Instructions can be larger than a single word.
8. It emphasizes the building of instruction on hardware because it is faster to create than
the software.
CISC Processors Architecture
• The CISC architecture helps reduce
program code by embedding multiple
operations on each program
instruction, which makes the CISC
processor more complex.
• The CISC architecture-based computer
is designed to decrease memory costs
because large programs or instruction
required large memory space to store
the data, thus increasing the memory
requirement, and a large collection of
memory increases the memory cost,
which makes them more expensive
• Advantages of CISC Processors • Disadvantages of CISC Processors
1. The compiler requires little effort to translate 1. CISC chips are slower than RSIC chips to
high-level programs or statement languages into
assembly or machine language in CISC
execute per instruction cycle on each
processors. program.
2. The code length is quite short, which minimizes 2. The performance of the machine
the memory requirement. decreases due to the slowness of the
3. To store the instruction on each CISC, it requires clock speed.
very less RAM. 3. Executing the pipeline in the CISC
4. Execution of a single instruction requires several processor makes it complicated to use.
low-level tasks.
5. CISC creates a process to manage power usage
4. The CISC chips require more transistors
that adjusts clock speed and voltage. as compared to RISC design.
6. It uses fewer instructions set to perform the 5. In CISC it uses only 20% of existing
same instruction as the RISC. instructions in a programming event.
Difference between RISC AND CISC
RISC CISC

Focus on software Focus on hardware

Uses only Hardwired control unit Uses both hardwired and microprogrammed control unit

Transistors are used for storing complex

Transistors are used for more registers Instructions

Fixed sized instructions Variable sized instructions

Can perform only Register to Register Arithmetic operations Can perform REG to REG or REG to MEM or MEM to MEM

Requires more number of registers Requires less number of registers

Code size is large Code size is small

An instruction executed in a single clock cycle Instruction takes more than one clock cycle
Array processors with example.
• An array processor has an architecture mainly designed for processing arrays of numbers.
• This processor architecture contains a number of processors that works simultaneously.
• each handling one array element, so that a single operation is applied to all the array
elements in parallel.
• To get the same effect within a conventional processor, the operation should be applied to
every array element sequentially and much more slowly.
 Array processors perform computation on large amounts of data.
 It has mainly two types: -
1. Attached Array Processor
2. SIMD Processor
 Attached array processors are generally used for handling numerical computations on host
computer which is used to perform operations onauxiliary memory.
 Attached array processors have two interfaces: general purpose computerhas main memory
interface and attached array processor has cache.
Cont…
 Cache memory interconnects the main memory.
 A host computer is general purpose computer, and the attached array processoris a backend
machine which is controlled by a host computer.
 The array processor is connected through input/output interface or acontroller to the
computer and a computer treats it as an external interface.
Cache
Memory
Thank you