Data Transfer Modes

Programmed I/O, Interrupt-initiated I/O

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Direct memory access (DMA)
 Data Transfer Modes
• Data transfer between the central computer and I/O
devices may be handled in a variety of modes.
1) Programmed I/O
2) Interrupt-initiated I/O
3) Direct memory access (DMA)
 Programmed I/O
• In the programmed I/O method, the I/O device does
not have direct access to memory.
• Each data item transfer is initiated by an instruction
in the program.
• Usually, the transfer is to and from a CPU register and
peripheral.
• Transferring data under program control requires
constant monitoring of the peripheral by the CPU.
• Once a data transfer is initiated, the CPU is required
to monitor the interface to see when a transfer can
again be made.
 Programmed I/O
• The device transfers bytes of data one at a time as
they are available.
• When a byte of data is available, the device places it
in the I/O bus and enables its data valid line.
• The interface accepts the byte into its data register
and enables the data accepted line.
• The interface sets a bit in the status register that we
will refer to as an F or "flag" bit.

Fig: Data transfer from I/O device to CPU

 Programmed I/O
• The I/O device can now disable the data valid line,
but it will not transfer another byte until the data
accepted line is disabled by the interface.
• CPU checks the flag in the status register to
determine if a byte has been placed in the data
register by the I/O device.
• This is done by reading the status register into a CPU
register and checking the value of the flag bit.

Fig: Data transfer from I/O device to CPU

 Programmed I/O
• If the flag is equal to 1, the CPU reads the data from
the data register.
• When the flag is cleared, the interface disables the
data accepted line and the device can then transfer
the next data byte.
• The programmed I/O method is particularly useful in
small low-speed computers or in systems that are
dedicated to monitor a device continuously.

Fig: Data transfer from I/O device to CPU

 Programmed I/O
• The transfer of each byte
requires three instructions:
1.Read the status register.
2.Check the status of the flag
bit and branch to step 1 if
not set or to step 3 if set.
3.Read the data register
• Each byte is read into a CPU
register and then transferred
to memory with a store
instructions.

Fig: Flowchart for CPU program to input data

 Programmed I/O
• This type of transfer is inefficient because of the
difference in information transfer rate between the
CPU and the I/O device.
• CPU stays in a program loop until the I/O unit
indicates that it is ready for data transfer.
• This is a time-consuming process since it keeps the
processor busy needlessly.
 Interrupt-initiated I/O
• Interrupt-initiated I/O can overcome the limitations
of Programmed I/O.
• It uses an interrupt facility and special commands to
inform the interface to issue an interrupt request
signal when the data are available from the device.
• In the meantime the CPU can proceed to execute
another program.
• The interface meanwhile keeps monitoring the
device.
• When the interface determines that the device is
ready for data transfer, it generates an interrupt
request to the CPU.
 Direct Memory Access
• Transfer of data under programmed I/O is between
CPU and peripheral.
• In direct memory access (DMA), the interface
transfers data into and out of the memory unit
through the memory bus.
• The transfer of data between a fast storage device
such as magnetic disk and memory is often limited
by the speed of the CPU.
• Removing the CPU from the path and letting the
peripheral device manage the memory buses
directly would improve the speed of transfer.
 Direct Memory Access
• During the DMA transfer, the CPU is idle and has no
control of the memory buses.
• A DMA Controller takes over the buses to manage
the transfer directly between the I/O device and
memory.
• Two control signals in the CPU that facilitates the
DMA transfer.
• The Bus Request (BR) input is used by the DMA
controller to request the CPU.
 Direct Memory Access
• When BR input is active, the CPU terminates the
execution of the current instruction and places the
address bus, data bus and read write lines into a
high Impedance state.
• High Impedance state means that the output is
disconnected.

Fig: CPU bus signals for DMA transfer

 Direct Memory Access
• The CPU activates the Bus Grant (BG) output to inform the
external DMA that the Bus Request (BR) can now take
control of the buses to conduct memory transfer without
processor.
• When the DMA terminates the transfer, it disables the Bus
Request (BR) line.
• The CPU disables the Bus Grant (BG), takes control of the
buses and return to its normal operation.

Fig: CPU bus signals for DMA transfer

 Direct Memory Access
The transfer can be made in several ways that are:
i. DMA Burst
ii. Cycle Stealing
i) DMA Burst :- In DMA Burst transfer, a block sequence
consisting of a number of memory words is
transferred in continuous burst while the DMA
controller is master of the memory buses.
ii) Cycle Stealing :- Cycle stealing allows the DMA
controller to transfer one data word at a time, after
which it must returns control of the buses to the
CPU.
 Direct Memory Access Controller
• The DMA controller has three registers:
i. Address Register: contains an address to specify the
desired location in memory.
ii. Word Count Register: holds the number of words to
be transferred. The register is increment/decrement
by one after each word transfer and internally tested
for zero.
iii. Control Register: specifies the mode of transfer
• When the BG (Bus Grant) input is 0, the CPU can
communicate with the DMA registers through the
data bus to read from or write to the DMA registers.
• When BG =1, the DMA can communicate directly with
the memory by specifying an address in the address
 Direct Memory Access Controller
• The CPU communicates with the DMA through the
address and data buses as with any interface unit.
The DMA has its own address, which activates the DS
and RS lines.

Fig: Block diagram of DMA Controller

 Direct Memory Access Controller
• The CPU initializes the DMA through the data bus.
• Once the DMA receives the start control command, it
can transfer between the peripheral and the memory.

Fig: Block diagram of DMA Controller