Computer Organization

and Architecture
Carl Hamacher, Zvonko Vranesic, Safwat
Zaky,
Computer Organization, 5th
Edition,
Tata McGraw Hill, 2002.
 Module-5
BASIC PROCESSING UNIT
Overview
 InstructionSet Processor (ISP) –
executes machine instructions and
coordinates the activities of other
cells.
 Also called Central Processing Unit (CPU)
A typical computing task consists of a
series of steps specified by a
sequence of machine instructions
that constitute a program.
 An instruction is executed by carrying
Some Fundamental
Concepts
Fundamental Concepts
 Processor fetches one instruction at a
time and performs the operation
specified.
 Instructions are fetched from successive
memory locations until a branch or a jump
instruction is encountered.
 Processor keeps track of the address of the
memory location containing the next
instruction to be fetched using Program
Counter (PC).
 After fetching an instruction, the contents of
the PC are updated to point to the next
Steps in Executing an
Instruction
 Fetch the contents of the memory location
pointed to by the PC. The contents of this
location are loaded into the instruction
register IR (fetch phase).
IR ← [[PC]]
 Assuming that the memory is byte
addressable, increment the contents of the
PC by 4 (fetch phase).
PC ← [PC] + 4
 Carry out the actions specified by the
instruction in the IR (execution phase).
Processor Organization Internal processor
bus

C
o
PC n
t
r
o Instruction
Address l decoder and
lines
MAR control logic
MDR HAS s
Memory i
TWO INPUTS bus g
AND TWO n
MDR a
OUTPUTS Data l
lines s IR

Datapat
Y

Constant 4 R0 h
Select MUX

Add
A B
ALU Sub R  n - 1
control ALU
lines
Carry-in
XOR TEMP

Textbook Page
413
Processor Organization..
 Figure 7.1 shows an organization in which
the ALU and all the registers are
interconnected via a single common bus.
 This bus is internal to the processor.

 The data and address lines of the

external memory bus are connected to

the internal processor bus via the
memory data register, MDR, and the
memory address register, MAR,
respectively.
 Register MDR has two inputs and two
Processor Organization..
 Data may be loaded into MDR either from
the memory bus or from the internal
processor bus.
 The data stored in MDR may be placed on
either bus.
 The input of MAR is connected to the
internal bus, and its output is connected to
the external bus.
 The control lines of the memory bus are
connected to the instruction decoder and
control logic block.
 This unit is responsible for issuing the signals that
Processor Organization..
 The number and use of the processor
registers R0 through R(n - 1) vary
considerably from one processor to another.
 Registers may be provided for general-
purpose use by the programmer.
 Some may be dedicated as special-purpose
registers, such as index registers or stack pointers.
 The registers, Y, Z, and TEMP are used by the
processor for temporary storage during
execution of some instructions.
 These registers are never used for storing data
generated
by one instruction for later use by another
Processor Organization..
 The multiplexer MUX selects either the
output of register Y or a constant value 4
to be provided as input A of the ALU.
 The constant 4 is used to increment the
contents of the
program counter.
 We will refer to the two possible values of
the MUX control input Select as Select4 and
SelectY for selecting the constant 4 or
register Y, respectively.
Processor Organization..
 As instruction execution progresses, data are
transferred from one register to another,
often passing through the ALU to perform
some arithmetic or logic operation.
 The instruction decoder and control logic
unit is responsible for implementing the
actions specified by the instruction loaded
in the IR register.
 The decoder generates the control signals
needed to select the registers involved and
direct the transfer of data.
 The registers, the ALU, and the
Sequence of Steps in
Executing an Instruction
 Transfer a word of data from one
processor register to another or to the
ALU.
 Perform an arithmetic or a logic
operation and store the result in a
processor register.
 Fetch the contents of a given
memory location and load them
into a processor register.
 Store a word of data from a
processor register into a given
Register Transfers
 Instruction execution involves a
sequence of steps in which data are
transferred from one register to
another.
 For each register, two control signals are
used to place the contents of that register
on the bus or to load the data on the bus
into the register.
 This is represented symbolically in Figure

7.2.
 The input and output of register Ri are
connected to the bus via switches
Register Transfers..
 When Riin is set to 1, the data on the
bus are loaded into Ri.
 Similarly, when Ri
out is set to 1, the
contents of register Ri are placed on the
bus.
 While Ri is equal to 0, the bus can be
out
used for transferring data from other
registers.
Register Transfers.. R iin
Internal processor
bus

Ri

Riout

Y in

Constant 4

Select MUX

A B
ALU

Z in

Z out

Figure 7.2. Input and output gating for the registers in Figure 7.1.
Register Transfers..
 Suppose that we wish to transfer the
contents of register R1 to register R4.
 This can be accomplished as follows:
 Enable the output of register R1 by setting
R1out to 1. This places the contents of R1 on
the processor bus.
 Enable the input of register R4 by setting R4in
to 1. This loads data from the processor bus
into register R4.
 All operations and data transfers within
the processor take place within time
periods defined by the processor clock.
Register Transfers..
 An implementation for one bit of
register Ri is shown in Figure 7.3 as an
example.
 A two-input multiplexer is used to select

the data applied to the input of an edge-

triggered D flip- flop.
 When the control input Ri is equal to
in
1, the multiplexer selects the data on
the bus.
 This data will be loaded into the flip-flop at
the rising edge of the clock.
Register Transfers..
 The Q output of the flip-flop is connected
to the bus via a tri-state gate.
 When Ri is equal to 0, the gate's output
out
is in the high-impedance (electrically
disconnected) state.
 This corresponds to the open-circuit state of
a switch.
 When Riout = 1, the gate drives the bus to
0 or 1, depending on the value of Q.
Register Transfers..
Bus

D Q
1
Q
Riiout
Riin
Clock

Figure 7.3. Input and output gating for one register bit.
Performing an Arithmetic or
Logic Operation
 The ALU is a combinational circuit that
has no internal storage.
 It performs arithmetic and logic operations on
the two operands applied to its A and B inputs.
 ALU gets the two operands from MUX and
bus. The result is temporarily stored in
register Z.
 The sequence of operations to add the
contents of register R1 to those of R2 and
1 store the result in R3.
. R1out, Yin
2. R2out, SelectY, Add,
Zin
3
. Zout, R3in
Performing an Arithmetic or
Logic Operation..
 The signals whose names are given in
any step are activated for the duration of
the clock cycle corresponding to that
step.
 All other signals are inactive.
 In step 1, the output of register R1 and
the input of register Y are enabled,
causing the contents of RI to be
transferred over the bus to Y.
Performing an Arithmetic or
Logic Operation..
 In step 2, the multiplexer's Select signal is
set to SelectY, causing the multiplexer to
gate the contents of register Y to input A
of the ALU.
 At the same time, the contents of register R2
are gated
onto the bus and, hence, to input B.
 The Add line is set to 1, causing the output of the
ALU to be the sum of the two numbers at inputs
A and B.
 This sum is loaded into register Z because its
input
control signal is activated.
Fetching a Word from
Memory
 To fetch a word of information from
memory, the processor has to specify the
address of the memory location where
this information is stored and request a
Read operation.
 The information to be fetched may be an
instruction in a program or an operand
specified by an instruction.
 The processor transfers the required
address to the MAR, whose output is
connected to the address lines of the
Fetching a Word from
Memory..
 At the same time, the processor uses the
control lines of the memory bus to
indicate that a Read operation is needed.
 When the requested data are received
from the memory they are stored in
register MDR,
 From MDR, they can be transferred to
other registers in the processor.
Fetching a Word from
Memory..

Memory-bus Internal processor

data lines bus
MDRout
MDRoutE

MDR

MDRinE MDRin

Figure 7.4. Connection and control signals for register MDR.

Fetching a Word from
Memory..
 The connections for register MDR
are illustrated in Figure 7.4.
 It has four control signals:
 MDRin and MDRout control the
connection to the
internal bus.
 MDRinE and MDRoutE control the connection
to the external bus.
Fetching a Word from
Memory..
 During memory Read and Write
operations, the timing of internal
processor operations must be
coordinated with the response of the
addressed device on the memory
bus.
 The processor completes one internal
data transfer in one clock cycle.
Fetching a Word from
Memory..
 The response time of each memory access
varies (based on cache miss, memory-
mapped I/O, etc).
 To accommodate this, the processor waits until
it receives an indication that the requested
operation has been completed.
 A control signal called Memory-Function-
Completed (MFC) is used for this purpose.
 The addressed device sets this signal to 1 to
indicate that the contents of the specified
location have been read and are available on
the data lines of the memory bus.
Fetching a Word from
Memory..
 Consider the instruction Move (R1), R2
 The actions needed to execute this

instruction are:
1. MAR ← [R1]

2. Start a Read operation on the memory

bus
3. Wait for the MFC response from the
memory
4. Load MDR from the memory bus

5. R2 ← [MDR]
Fetching a Word from
Memory..
 The memory read operation requires
three steps, which can be described by
the signals being activated as follows:
1. R1out, MARin, Read

2. MDRinE, WMFC
3. MDRout, R2in
 Step 1 2 3

Timing Clock

MAR in MAR ← [R1]

Assume MAR
is always Address
available on the
address lines of Start a Read operation on the
Read
the memory bus. memory bus
MR

MDR inE

Data

Wait for the MFC response from the

memory MFC

MDR out
Load MDR from the memory
bus
R2 ←
[MDR]

Figure 7.5. T iming of a memory Read operation.

Storing a Word in Memory
 The desired address is loaded into MAR.
 The data to be written are loaded into

MDR and a Write command is issued.

 Executing the instruction Move R2,(R1)

requires the following sequence:

1. R1out, MARin

2. R2out, MDRin, Write

3. MDRoutE,WMFC
Execution of a Complete
Instruction
 Consider the instruction Add (R3), R1
 Executing this instruction

requires the following actions:

1. Fetch the instruction

2. Fetch the first operand (the contents

of the memory location pointed to by
R3)
3. Perform the addition

4. Load the result into R1

Execution of a Complete
Instruction..
Add (R3),
R1
Execution of a Complete
Instruction..
 Figure 7.6 gives the sequence of control
steps required to perform these
operations for the single-bus
architecture of Figure 7.1.
 Steps 1 through 3 constitute the
instruction fetch phase,
 This is the same for all instructions.

 The instruction decoding circuit

interprets the contents of the IR at the
beginning of step 4.
 This enables the control circuitry to

activate the control signals for steps 4

Execution of Branch
Instructions
 A branch instruction replaces the contents
of PC with the branch target address
 This address is usually obtained by

adding an offset X given in the

branch instruction, to the updated
value of the PC.
Execution of Branch
Instructions..
Execution of Branch
Instructions..
 Figure 7.7 gives a control sequence that
implements an
unconditional branch instruction.
 Processing starts with the fetch phase.
 This phase ends when the instruction is loaded
into the
IR in step 3.
 The offset value is extracted from the IR by the
instruction decoding circuit, which will also
perform sign extension if required.
 Since the value of the updated PC is already
available in register Y, the offset X is gated onto
the bus in step 4, and an addition operation is
performed.
Execution of Branch
Instructions..
 The offset X is usually the difference
between the branch target address and
the address immediately following the
branch instruction.
 For example, if the branch instruction is at
location 2000 and if the branch target
address is 2050, the value of X must be 46.
Execution of Branch
Instructions..
 Consider now a conditional branch.
 In this case, we need to check the status of
the condition codes before loading a new
value into the PC.
 For example, for a Branch-on-negative
(Branch <0) instruction, step 4 in Figure 7.7
is replaced with

 Thus, if N = 0 the processor returns to

step 1 immediately after step 4.
 If N = 1, step 5 is performed to load a new
value into the PC, thus performing the branch
Multiple-Bus Organization
 To reduce the number of steps needed,
most commercial processors provide
multiple internal paths that enable several
transfers to take place in parallel.
 Figure 7.8 depicts a three-bus structure

used to connect the registers and the ALU

of a processor.
Multiple-Bus Organization..
Bus A Bus B
Bus C
Incrementer

PC

Register
file

Constant 4

MUX
ALU R
B

Instruction
decoder

IR

MDR

MAR

Memory b us Address
data lines lines
Multiple-Bus Organization..
 All general-purpose registers are
combined into a single block called the
register file.
 Implemented in the form of an array of
memory cells.
 The register file in Figure 7.8 is said to
have three ports.
 There are two outputs, allowing the contents
of two different registers to be accessed
simultaneously and have their contents
placed on buses A and B.
 The third port allows the data on bus C to be
Multiple-Bus Organization..
 Buses A and B are used to transfer the
source operands to the A and B inputs
of the ALU, where an arithmetic or logic
operation may be performed.
 The result is transferred to the
destination over bus C.
 If needed, the ALU may simply pass one

of its two input operands unmodified to

bus C.
 We will call the ALU control signals for
such an operation R=A or R=B.
Multiple-Bus Organization..
 The Incrementer unit is used to
increment the PC by 4.
 Using the Incrementer eliminates the need to
add 4 to the PC using the main ALU.
 The source for the constant 4 at the ALU
input multiplexer is still useful.
 It can be used to increment other addresses,
such as the memory addresses in
LoadMultiple and StoreMultiple instructions.
Multiple-Bus Organization..
 Consider the three-operand instruction Add R4,
R5, R6
Multiple-Bus Organization..
 In step 1, the contents of the PC are
passed through the ALU, using the R=B
control signal, and loaded into the MAR to
start a memory read operation.
 At the same time the PC is incremented by 4.
 In step 2, the processor waits for MFC and
loads the data received into MDR,
then transfers them to IR in step 3.
 Finally, the execution phase of the
instruction requires only one control step
to complete, step 4.
Hardwired Control
Overview
 Toexecute instructions, the processor
must have some means of
generating the control signals
needed in the proper sequence.
 Two categories:
 Hardwired control
 Microprogrammed control
 Hardwired system can operate at high
speed; but with little flexibility.
Hardwired Control – Control
Unit Organization
 Consider the sequence of control
signals given in Figure 7.6.
 Each step in this sequence is
completed in one clock period.
 A counter may be used to keep track

of the control steps, as shown in

Figure 7.10.
 Each state, or count, of this

counter corresponds to one

control step.
Control Unit Organization
CLK Control step
Clock counter

External
inputs
Decoder/
IR
encoder
Condition
codes

Control signals
Figure 7.10. Control unit organization.
Control Unit Organization..
 The required control signals are
determined by the following
information:
 Contents of the control step counter
 Contents of the instruction register
 Contents of the condition code flags
 External input signals, such as MFC and
interrupt requests
Control Unit Organization..
 The decoder/encoder block in Figure
7.10 is a combinational circuit that
generates the required control
outputs, depending on the state of all
its inputs.
 By separating the decoding and
encoding functions, we obtain the
more detailed block diagram in Figure
7.11.
Control Unit Organization -
Detailed Block Description
CLK
Clock Control step Reset
counter

Step decoder

T 1 T2 T
n

INS 1

INS External
2 inputs
Instruction
IR decoder Encoder
Condition
codes
INS m

Run End

Control signals

Figure 7.11. Separation of the decoding and encoding functions.

Control Unit Organization..
 The step decoder provides a separate signal
line for each step, or time slot, in the control
sequence.
 Similarly, the output of the instruction
decoder consists of a separate line for
each machine instruction.
 For any instruction loaded in the IR, one of
the output lines INS1 through INSm is set to
1, and all other lines are set to 0.
 The input signals to the encoder block are
combined to generate the individual control
signals Yin, PCout, Add, End, and so on.
Generating Zin
Zin = T1 + T6 • ADD + T4 • BR
+…

This signal is asserted

during time slot T1 for
all instructions, during
T6 for an Add
instruction, during T4
for an unconditional
branch instruction,
and so on.
Generating End
 End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) •
BRN +…

The End signal starts a

new instruction fetch
cycle by resetting the
control step counter to
its starting value.
Control Unit Organization..
 Figure 7.11 contains another control signal
called RUN.
 When set to 1, RUN causes the counter to be
incremented by one at the end of every
clock cycle.
 When RUN is equal to 0, the counter
stops counting.
 This is needed whenever the WMFC signal
is issued, to
cause the processor to wait for the reply
from the memory.
Control Unit Organization..
 The control hardware shown in Figure 7.10
or 7.11 can be viewed as a state machine
that changes from one state to another in
every clock cycle,
 Depends on the contents of the instruction
register, the
condition codes, and the external inputs.
 The outputs of the state machine are the control
signals.
 The sequence of operations carried out
by this machine is determined by the
wiring of the logic elements, hence the
name "hardwired.“
A
Complete
Processor
A Complete Processor

Instruction Integer Floating-point

unit unit unit

Instruction Data
cache cache

Bus interface
Processor

System bus

Main Input/
memory Output

Figure 7.14. Block diagram of a complete processo.

A Complete Processor..
A complete processor can be designed
using the structure shown in Figure
7.14.
 This structure has an instruction unit

that fetches instructions from an

instruction cache or from the main
memory when the desired instructions
are not already in the cache.
 It has separate processing units to

deal with integer data and floating-

A Complete Processor..
A single cache can be used to store
both instructions and data or separate
caches can be used for instructions and
data.
 The processor is connected to the

system bus and, hence, to the rest of

the computer, by means of a bus
interface.
 A processor may include several

integer or floating-point units to

Microprogrammed
Control
Overview
 Control signals are generated by a
program similar to machine language
programs.
 A control word (CW) is a word whose

individual bits represent the various

control signals.
 A sequence of CWs corresponding to the

control sequence of a machine instruction

constitutes the microroutine for that
instruction.
 The individual control words in this
Microprogrammed Control
 Each of the control steps in the
control sequence of an instruction
defines a unique combination of 1s
and 0s in the CW.
 The CWs corresponding to the 7

steps of Figure 7.6 are shown in

Figure 7.15.
 We have assumed that SelectY is

represented by Select=0 and

Select4 by Select=1.
Microprogrammed Control..

MDRout

WMFC
MAR in
Micro -

Select
PCout

Read

R1out

R3out
instruction

Zout

End
Add

R1in
PCin

IRin

Yin

Zin
1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

Figure 7.15 An e xample of microinstructions for Figure 7.6.

Microprogrammed Control..
 The microroutines for all instructions
in the instruction set of a computer
are stored in a special memory called
the control store.
 The control unit can generate the

control signals for any instruction

by sequentially reading the CWs of
the corresponding microroutine
from the control store.
 Figure 7.16 shows the basic
Microprogrammed Control..
Microprogrammed Control..
 To read the control words sequentially
from the control store, a microprogram
counter (µPC) is used.
 Every time a new instruction is loaded into
the IR, the output of the block labeled
"starting address generator'' is loaded into
the µPC.
 The µPC is then automatically incremented
by the clock, causing successive
microinstructions to be read from the
control store.
 Hence, the control signals are delivered to
Microprogrammed Control..
 The previous organization cannot handle the situation
when the control unit is required to check the status of the
condition codes or external inputs to choose between
alternative courses of action.
 Can be handled by using conditional branch microinstruction.
Microprogrammed Control..
 The instruction Branch<0 can be implemented by a
microroutine
such as that shown in Figure 7.17.
 After loading this instruction into IR, a branch
microinstruction transfers control to the
corresponding microroutine, which is assumed to
start at location 25 in the control store.
 This address is the output of the starting address
generator block in
Figure 7.16.
 The microinstruction at location 25 tests the N bit of the
condition codes.
 If this bit is equal to 0, a branch takes place to location 0 to
fetch a new machine instruction.
 Otherwise, the microinstruction at location 26 is executed
to put the branch target address into register Z.
Microprogrammed Control..
Microprogrammed Control..
 To support microprogram branching, the
organization of the control unit should be
modified as shown in Figure 7.18.
 The starting address generator block of Figure
7.16 becomes the starting and branch
address generator.
 This block loads a new address into the µPC
when a microinstruction instructs it to do so.
 To allow implementation of a conditional
branch, inputs to this block consist of the
external inputs and condition codes as well as
the contents of the instruction register.
Microprogrammed Control..
 In this control unit, the µPC is incremented
every time a new microinstruction is fetched
from the microprogram memory, except in the
following situations:
1. When a new instruction is loaded into the IR, the
µPC is loaded with the starting address of the
microroutine for that instruction.
2. When a Branch microinstruction is
encountered and the branch condition is
satisfied, the µPC is loaded with the branch
address.
3. When an End microinstruction is encountered,
the µPC is loaded with the address of the first