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Delay Calculation

Delay calculation in STA

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39 views

Delay Calculation

Delay calculation in STA

Uploaded by

mbalaji00000
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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DELAY CALCULATION

BASICS
• For the purposes of simplicity, the contributions from the
interconnect are not considered in this section those are
described in the later sections.
• Without considering the
interconnect parasitics, the
internal net NET0 has a net
capacitance which is
comprised of the input pin
capacitances from the UAND1
and UNOR2 cells.
• The output O1 has the pin capacitance of the UNOR2 cell
plus any capacitive loading for the output of the logic block.
• Inputs I1 and I2 have pin capacitances corresponding
to the UAND1 and UINV0 cells.
• As described in Chapter 3, the cell library contains
NLDM timing models for various timing arcs.
• Thus, if the input transition time (or slew) is specified
at the inputs of the logic block, the output transition
time and delays through the timing arcs of the UINV0
cell and UAND1 cell (for the input I1) can be obtained
from the library cell descriptions.
• For a multi-input cell (such as UAND1), different input
pins can provide different values of output transition
times. The choice of transition time used for the
fanout net depends upon the slew merge.
Delay Calculation with Interconnect
Pre-layout Timing
• The interconnect parasitics are estimated using wireload
models during the pre-layout timing verification.
• In cases where the wireload models include the effect of the
resistance of the interconnect, the NLDM models are used
with the total net capacitance for the delay through the cell.
Post-layout Timing
• The parasitics of the metal traces
map into an RC network between
driver and destination cells.
• The output load of the inverter
cell UINV0 is comprised of an RC
structure.
• The resistive load at the output pin implies that the NLDM
• Instead of using NLDM directly, an “effective”
capacitance approach is employed to handle the
effect of resistance.
• This equivalent single
capacitance is termed as
effective capacitance.
• In relation to the PI-equivalent
representation, the effective
capacitance can be expressed as:
Ceff = C1 + k * C2, 0 <= k <= 1
• The effective capacitance Ceff is selected so that the delay (as
measured at the midpoint of the transition) at the output of
the cell in Figure 5-4(c) is the same as the delay in Figure 5-
4(a).
• The waveforms at the output of the cell with total
capacitance, effective capacitance and the waveform
with the actual RC interconnect.
Interconnect
Delay
• The interconnect parasitics of a net are normally represented by an
RC circuit.
• The RC interconnect can be pre-layout or post-layout.
• While the post-layout parasitic interconnect can include coupling to
neighboring nets, the basic delay calculation treats all capacitances
(including coupling capacitances) as capacitances to ground
• The interconnect delay for the best-case tree type is thus equal to
zero.
• The interconnect delay for the typical-case tree and worst-case tree
are handled just like for the post-layout RC interconnect.

• ELMORE DELAY :
• Elmore delays are applicable for RC trees. What is an RC tree? An RC
tree meets the following three conditions:

• Has a single input (source) node.


• Does not have any resistive loops.
• All capacitances are between a node and ground
Td1 = C1 * R1;
Td2 = C1 * R1 + C2 * (R1 + R2);
...
Tdn = S(i=1,N) Ci (S (j=1,i) Rj);
• Rwire * (Cwire / 2 + Cload)

• Using a balanced tree model

• net delay = (Rwire / N) * (Cwire / (2 * N) + Cpin)

• In the worst-case tree model

• Net delay = Rwire * (Cwire / 2 + Cpins)


Net delay = Rwire * (Cwire /2 + Cpins)
= 0.3 * (0.5 + 2.3) = 0.84
If we use the balanced tree model, we get the following delays for the two
branches of the net N1:
Net delay to NOR2 input pin = (0.3/2) * (0.5/2 + 1.3)
= 0.2325
Net delay to BUF input pin= (0.3/2) * (0.5/2 + 1.0) = 0.1875
SLEW MERGING
• when multiple slews arrive at a common point, such as in the case of
a multi-input cell or a multi-driven net.
• Such a common point is referred to as a slew merge point.
• There are two possibilities when doing max • There are two possibilities when doing min
path analysis path analysis
• Worst slew propagation: • Best slew propagation:
• This mode selects the worst slew at the • This mode selects the best slew at the
merge point to propagate.For a timing path merge point to propagate. For a timing path
that goes through pins A->Z, this selection is that goes through pins B->Z, this selection is
exact exact, but the selection is smaller for any
timing path that goes through pins A->Z.

• Worst arrival propagation: • Best arrival propagation:


• This mode selects the worst arrival time at • This mode selects the best arrival time at
the merge point to propagate. The slew the merge point to propagate.The slew
chosen in this case is exact for a timing path chosen in this case is exact for a timing path
that goes through pins B->Z that goes through pins A->Z but the selection
is larger than the actual values for a timing
path that goes through pins B->Z
Path Delay Calculation

• Once all the delays for each timing arc are available, the timing through the
cells in the design can be represented as a timing graph. .
Combinational path delay
•Consider the three inverters in series as shown in Figure While considering paths from net N0 to net
N3, we consider both rising edge and falling edge paths.

Tn0 Ta Tn1 Tb Tn2 Tc Tn3

N0 N1 N2 N3
AZ AZ AZ

UINVa UINVb UINVc Cload

•The above analysis assumed a rising edge at net N0. Similar analysis can be carried out for the case of
a falling edge on net N0. Thus, in this simple example, there are two timing paths with the following
delays:

•Tfall =Tn0rise +Tafall +Tn1fall +Tbrise +Tn2rise +

•Tcfall + Tn3fall
• Trise = Tn0fall + Tarise + Tn1rise + Tbfall + Tn2fall + Tcrise + Tn3rise
path to a fliflop
We need to consider both rising edge and falling
edge paths. For the case of a rising edge on input
SDT, the data path delay is:

Tn1rise + Tafall +Tn2fall + Tbuf1fall + Tn3fall


+Tbrise +Tn4rise
Similarly, for a falling edge on input SDT, the data
path delay is:

Tn1fall + Tarise + Tn2rise + Tbuf1rise +

Tn3rise + Tbfall +Tn4fall The capture clock path

delay for a rising edge on input MCLK is:


Tn5rise + Tbuf2rise + Tn6rise
Flipflop to flipflop path
An example of a data path between two flip-
flops and corresponding clock paths is shown in
Figure
The data path delay for a rising edge on UFF0/Q
is:

Tck2qrise + Tn1rise + Tafall +

Tn2fall + Tbfall + Tn3fall The launch

clock path delay for a rising edge on input

PCLK is:
Tn4rise + T5rise + Tn5arise
The capture clock path delay for a rising edge
on input PCLK is:

Tn4rise + T5rise + Tn5brise + T6rise +


Tn6rise
Multiple path

Between any two points, there can be many paths.


The longest path is the one that takes the longest
time; this is also called the worst path, a late path
or a max path. The shortest path is the one that
takes the shortest time; this is also called the best
path, an early path or a min path.
See the logic and the delays through the timing
arcs in Figure . The longest path between the two
flip-flops is through the cells UBUF1, UNOR2, and
UNAND3. The shortest path between the two flip-
flops is through the cell UNAND3.
slack
Slack is the difference between the required time and the time that a signal arrives.
the data is required to be stable at time 7ns for the setup requirement to be met.
However data becomes stable at 1ns. Thus, the slack is 6ns (= 7ns - 1ns).
•Assuming that the data required time is obtained from the setup time of a capture flip-
flop,

•Slack = Required_time- Arrival_time


•Required_time = Tperiod - Tsetup(capture_flip_flop)
Data
•= 10 - 3 = 7ns CLK
required

0 1 5 7 10ns
•Arrival_time = 1ns Slack

•Slack = 7 - 1= 6ns DATA

Data
arrives

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