VLSI Design

Circuits & Layout

Outline
 CMOS Gate Design  Pass Transistors  CMOS Latches & Flip-Flops  Standard Cell Layouts  Stick Diagrams

CMOS Gate Design

 A 4-input CMOS NOR gate

A B C D Y

Complementary CMOS
 Complementary CMOS logic gates  nMOS pull-down network  pMOS pull-up network  a.k.a. static CMOS inputs

pMOS pull-up network

output
nMOS pull-down network

Pull-up OFF Pull-down OFF Pull-down ON Z (float) 0

Pull-up ON 1 X (crowbar)

Series and Parallel

a g1 g2 b (a) 0 0 b OFF a 0 0 b (b) b ON 0 1 b OFF a 0 1 b OFF a 1 0 b OFF a 1 0 b OFF a 1 1 b OFF a 1 1 b ON a a

 nMOS: 1 = ON  pMOS: 0 = ON  Series: both must be ON  Parallel: either can be ON

a g1 g2

a g1 b (c) g2 0

a 0 b OFF 0

a 1 b ON 1

a 0 b ON 1

a 1 b ON

a g1 b (d) g2 0

a 0 b ON 0

a 1 b ON 1

a 0 b ON 1

a 1 b OFF

Conduction Complement
 Complementary CMOS gates always produce 0 or 1  Ex: NAND gate
  

Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires parallel pMOS

Y A B

 Rule of Conduction Complements

 

Pull-up network is complement of pull-down Parallel -> series, series -> parallel

Compound Gates
 Compound gates can do any inverting function
 Ex: AND-AND-OR-INV

(AOI22)

Y ! ( A y B )  (C y D)
A B (b) C A (d) D B C D

A B (a)

C D

A (c) C A A B (e)

B C

D B Y C D (f) A B C D Y

Example: O3AI


Y ! ( A  B  C) y D

Example: O3AI


Y ! ( A  B  C) y D
A B C D Y D A B C

Pass Transistors
 Transistors can be used as switches
g s d

g s d

Pass Transistors
 Transistors can be used as switches
g s d s g=1 s g s d s g=1 s d g=0 d d 1 Input 0 g=0 g=0 g=0 d Input g = 1 Output 0 strong 0 g=1 degraded 1 Output degraded 0 strong 1

Signal Strength
 Strength of signal


How close it approximates ideal voltage source

 VDD and GND rails are strongest 1 and 0  nMOS pass strong 0


But degraded or weak 1 But degraded or weak 0

 pMOS pass strong 1



 Thus NMOS are best for pull-down network  Thus PMOS are best for pull-up network

Transmission Gates
 Pass transistors produce degraded outputs  Transmission gates pass both 0 and 1 well

Transmission Gates
 Pass transistors produce degraded outputs  Transmission gates pass both 0 and 1 well
Input g a gb g a gb b a gb g b a gb b g = 0, gb = 1 a b g = 1, gb = 0 a b g b Output

g = 1, gb = 0 0 strong 0 g = 1, gb = 0 strong 1 1

Tristates
 Tristate buffer produces Z when not enabled
EN
EN 0 0 1 1 A 0 1 0 1 Y Z Z 0 1

A EN A EN

Nonrestoring Tristate
 Transmission gate acts as tristate buffer  Only two transistors  But nonrestoring  Noise on A is passed on to Y (after several stages, the noise may degrade the signal beyond recognition)

EN A EN Y

Tristate Inverter
 Tristate inverter produces restored output  Note however that the Tristate buffer


ignores the conduction complement rule because we want a Z output

A EN Y EN

Tristate Inverter
 Tristate inverter produces restored output  Note however that the Tristate buffer


ignores the conduction complement rule because we want a Z output

A A EN Y EN Y

A Y

EN = 0 Y = 'Z'

EN = 1 Y=A

Multiplexers
 2:1 multiplexer chooses between two inputs
S D0 D1 0 Y 1

S 0 0 1 1

D1 X X 0 1

D0 0 1 X X

Multiplexers
 2:1 multiplexer chooses between two inputs
S D0 D1 0 Y 1

S 0 0 1 1

D1 X X 0 1

D0 0 1 X X

Y 0 1 0 1

Gate-Level Mux Design

 Y ! SD1  SD0 (too many transistors)  How many transistors are needed?

Gate-Level Mux Design

 Y ! SD1  SD0 (too many transistors)  How many transistors are needed? 20

D1 S D0

D1 S D0

4 2 4

2 4 2 2

Transmission Gate Mux

 Nonrestoring mux uses two transmission

gates

Transmission Gate Mux

 Nonrestoring mux uses two transmission

gates


Only 4 transistors

S D0 S D1 S Y

Inverting Mux
 Inverting multiplexer
  

Use compound AOI22 Or pair of tristate inverters Essentially the same thing

 Noninverting multiplexer adds an inverter

D0 S S S D1 Y S S S D1 D0 S D1 S Y D0 0 1 Y S

4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two

selects

4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two

selects
 

Two levels of 2:1 muxes Or four tristates

D0 S0 D0 D1 D2 D3 0 D1 1 0 1 D3 0 Y 1 D2 S1

S1S0 S1S0 S1S0 S1S0

D Latch
 When CLK = 1, latch is transparent  Q follows D (a buffer with a Delay)  When CLK = 0, the latch is opaque  Q holds its last value independent of D  a.k.a. transparent latch or level-sensitive latch

CLK D Latch Q

CLK D Q

D Latch Design
 Multiplexer chooses D or old Q

CLK D 1 0 Q Q D

CLK

Q Q

CLK

CLK

Old Q

CLK

D Latch Operation
Q D CLK = 1 Q D CLK = 0 Q Q

CLK D Q

D Flip-flop
 When CLK rises, D is copied to Q  At all other times, Q holds its value  a.k.a. positive edge-triggered flip-flop, master-

slave flip-flop
CLK

CLK
D

Flop

Q
Q

D Flip-flop Design
 Built from master and slave D latches
CLK CLK CLK Latch QM Latch QM D CLK Q CLK
A negative level-sensitive latch

CLK Q CLK CLK

CLK

CLK
A positive level-sensitive latch

D Flip-flop Operation
Inverted version of D

QM

CLK = 0
Holds the last value of NOT(D)

QM

Q
Q -> NOT(NOT(QM))

CLK = 1

CLK D Q

Race Condition
 Back-to-back flops can

malfunction from clock skew

 

Second flip-flop fires Early Sees first flip-flop change and captures its result Called hold-time failure or race condition

Nonoverlapping Clocks
 Nonoverlapping clocks can prevent races


As long as nonoverlap exceeds clock skew

 Good for safe design



Industry manages skew more carefully instead

J2 QM D J2 J2 J1 J1 J1 Q

J2 J1 J2

J1

Gate Layout
 Layout can be very time consuming
  

Design gates to fit together nicely Build a library of standard cells Must follow a technology rule

 Standard cell design methodology

   

VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts

Example: Inverter

Layout using Electric

Inverter, contd..

Example: NAND3
 Horizontal N-diffusion and p-diffusion strips  Vertical polysilicon gates  Metal1 VDD rail at top  Metal1 GND rail at bottom  32 P by 40 P

NAND3 (using Electric), contd.

Stick Diagrams
 Stick diagrams help plan layout quickly
 

Need not be to scale Draw with color pencils or dry-erase markers

Stick Diagrams
 Stick diagrams help plan layout quickly
 

Need not be to scale Draw with color pencils or dry-erase markers

VDD

Vin

Vout

GND

Wiring Tracks
 A wiring track is the space required for a wire


4 P width, 4 P spacing from neighbor = 8 P pitch

 Transistors also consume one wiring track

Well spacing
 Wells must surround transistors by 6 P
 

Implies 12 P between opposite transistor flavors Leaves room for one wire track

Area Estimation
 Estimate area by counting wiring tracks


Multiply by 8 to express in P

Example: O3AI
 Sketch a stick diagram for O3AI and estimate area


Y ! ( A  B  C) y D

Example: O3AI
 Sketch a stick diagram for O3AI and estimate area


Y ! ( A  B  C) y D

Example: O3AI
 Sketch a stick diagram for O3AI and estimate area


Y ! ( A  B  C) y D