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Programming the 8051 Microcontroller

The 8051 Instruction Set

 An Instruction consists of two parts namely
 Opcode
 Operand (s)
 The Opcode tells the processor what to do on executing an instruction
 Operand(s) is the parameter(s) required by an opcode to complete the action
 Instruction Set refers to the set of instructions supported by a
processor/controller architecture
 The instruction set of 8051 family microcontroller is broadly classified into
five categories namely
 Data transfer instructions
 Arithmetic Instructions
 Logical instructions
 Boolean Instructions
 Program Control Transfer Instructions
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Programming the 8051 Microcontroller

Addressing Modes Supported By 8051

 ‘Addressing Mode’ refers to “How the operand is specified in an

instruction” along with the opcode
 The operand may be - memory location(s), contents of memory location(s),
register(s), or constant data
 Depending on the type of operand, the addressing mode supported by 8051
falls into:
 Direct Addressing
 Indirect Addressing
 Register Addressing
 Register Instructions
 Register Specific Instructions
 Immediate Addressing
 Indexed Addressing

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Programming the 8051 Microcontroller

Addressing Modes Supported By 8051 – Direct Addressing

 The operand is specified as an 8bit memory address

 For 8051 processor, only the lower 128 byte internal data memory and the
SFRs are directly addressable
 E.g. MOV A, 07H (Moves the content of memory location 07H to
Accumulator. 07H refers to the address of data memory at location 7

Registers Data Memory

A Memory
Address
B
R0
07H 255 (FFH)

R7
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Programming the 8051 Microcontroller

Addressing Modes Supported By 8051 – Indirect Addressing

 The operand is specified indirectly using an indirect addressing register

 Indirect operations are performed using @register technique
 For 8bit internal data memory operations, register R0 or R1 is used as the
indirect addressing register

E.g. MOV R0, #55H ; Load R0 with 55H, The address of mem loc
MOV A,@R0 ; Load Accumulator with the contents of the memory location pointed by R0

Registers Data Memory

A Memory
Address
B
R0 55H
55H 255 (FFH)

R7
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Programming the 8051 Microcontroller

Addressing Modes Supported By 8051 – Indirect Addressing
 Among the scratchpad registers R0 to R7, only R0 and R1 can be used for indirect
addressing
 For 16bit external data memory/memory mapped register operations, 16bit register
DPTR is used as the indirect addressing register
 The whole 64K bytes of the external memory (if present physically on chip) can be
accessed by indirect addressing
E.g. MOV DPTR, #0055H ; Load DPTR register with 0055H, The address of the memory location
MOVX A,@DPTR ; Load Accumulator with the contents of the memory location pointed by DPTR

Registers External Data Memory

A Memory
Address
B
DPH 00H
DPL 55H 0055H 255 (FFH)
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Register Addressing Mode

• Use registers to hold the data to be manipulated

• The source and destination registers must match in size

– MOV DPTR,A will give an error

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Register Addressing Mode (cont.)

• The movement of data between Rn registers is not allowed

– MOV R4, R7 is invalid

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Programming the 8051 Microcontroller

Addressing Modes Supported By 8051 – Immediate Addressing
 Specifies a constant data as operand
 An immediate constant is represented with a leading ‘#’ symbol in the Assembly code
 A leading ‘#’ tells the assembler that the operand is a constant

E.g. MOV A, #09

Addressing Modes Supported By 8051 – Indexed Addressing
 Operand is specified using an base pointer register and an offset register
 The register Data Pointer (DPTR) or Program Counter (PC) is used as the base
pointer register
 Accumulator register is used as the offset register
 Normally used for code memory access like ‘look up tables’ stored in code memory

E.g. MOV DPTR, #2008H

MOV A, #00
MOVC A, @A+DPTR
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Programming the 8051 Microcontroller

The 8051 Instruction Set – Data Transfer Instructions
 Transfers data between a source and destination
 The source can be an internal data memory, a register, external data memory,
code memory or immediate data. Destination may be an internal data memory,
external data memory or a register

Internal Data transfer Operations

 perform the movement of data between, register, memory location, Accumulator
and stack.
 MOV instruction is used for data transfer between register, memory location and
accumulator
E.g. MOV A, #50H
MOV A, R0
MOV A, 50H
MOV A, @R0
MOV DPTR, #2000H
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Programming the 8051 Microcontroller

The 8051 Instruction Set – Data Transfer Instructions
Data Exchange Instructions
 Exchanges data between a memory location and the accumulator register
 Data exchange Instructions modifies both memory location and Accumulator
Register
 8051 supports two data exchange instructions namely XCH A, <memloc> and
XCHD A, @Ri.
 The XCH A,<memloc> instruction performs the exchange of the data at
memory location ‘memloc’ with Accumulator
 The XCHD A,@Ri (where i=0 or 1) instruction exchanges the low nibbles
between the Accumulator and the data memory pointed by the indirect memory
register R0 or R1
 Both XCH and XCHD are Accumulator specific instructions.

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Programming the 8051 Microcontroller

The 8051 Instruction Set – Data Transfer Instructions
External Data memory Instructions
 Transfers data between external memory and processor
 Data Pointer (DPTR) or the Indirect addressing Register R0/R1 and the
Accumulator are the registers involved in external data memory operations
 Only indirect addressing works on external data memory operations
 16bit register DPTR is used for holding the 16bit address to function as the external
memory pointer for 16bit external data memory operations. During 16bit external
data memory operations Port-0 emits the content of DPL register (Lower order 8bit
address) and Port-2 emits the content of DPH register (Higher order 8bit address)
 If the external data memory is only 8bit wide, either the DPTR or the Indirect
Address register R0 or R1 can be used for holding the 8bit address to function as the
external memory pointer. If R0 or R1 is used as the memory pointer register, Port-0
emits the contents of R0 or R1 register (Lower order 8bit address) and Port-2 emits
the contents of Port 2 SFR
 MOVX is the Instruction opcode for external data memory operation
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Programming the 8051 Microcontroller

The 8051 Instruction Set – Data Transfer Instructions : External Data memory Instructions

8bit External Data memory Operation

; Method-1
; Using Indirect register R0
MOV R0, #055H ; Let 55H be the external data memory address
MOVX A,@R0 ; Reads the content of 55H to Accumulator
MOV A, #00H ; Clear Accumulator
MOVX @R0, A ; Writes 0 to external memory 55H

; Method-2
; Using Data Pointer (DPTR) Register
MOV DPTR, #55H ; Let 55H be the external data memory address
MOVX A,@DPTR ; Reads the content of 55H to Accumulator
MOV A, #00H ; Clear Accumulator
MOVX @DPTR, A ; Writes 0 to external memory 55H

16bit External Data memory Operation

MOV DPTR, #2055H ; Let 2055H be the external data memory address
MOVX A,@DPTR ; Reads the content of 2055H to Accumulator
MOV A, #01H ; Load Accumulator with 1
MOVX @DPTR, A ; Writes 1 to external memory 2055H 13
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Programming the 8051 Microcontroller

The 8051 Instruction Set – Arithmetic Instructions
Addition Instructions
 The instructions ADD A,<loc> and ADDC A,<loc> implements addition operations. The
result of addition is stored in Accumulator
 <loc> can be registers B, R0,R1, …R7 or any SFR or an immediate constant or an internal
data memory or an internal data memory pointed indirectly by indirect addressing register
R0 or R1 and @
 The ADD A,<loc> implements normal addition and the carry flag gets modified
accordingly on executing this instruction
 If the addition results in an output greater than FFH, the carry flag is set and the
accumulator content will be final result – FFH + carry. The carry flag is reset when the
result of an addition is less than or equal to FFH
 The ADDC A,<loc> instruction operates in the same way as that of ADD A,<loc>
instruction except that it adds the carry flag with A and <loc>
 The changes to the carry flag on executing ADDC instruction remains the same as that of
executing the ADD A, <loc> instruction.
 Executing ADD and ADDC instructions modify the content of Accumulator only and
<loc> remains unchanged 14
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Programming the 8051 Microcontroller

The 8051 Instruction Set – Arithmetic Instructions
Subtraction Instruction
 The instructions SUBB A, <loc> implements subtraction operation. The result of
subtraction is stored in Accumulator
 <loc> can be registers B, R0,R1, …R7 or any SFR or an immediate constant or an
internal data memory or an internal data memory pointed indirectly by indirect
addressing register R0 or R1 and @
 The carry flag acts as the borrow indicator in the subtraction operation. The SUBB A,
<loc> instruction subtracts the borrow flag and the contents pointed by <loc> from
accumulator and modifies the accumulator with the result
 The content of <loc> remains unchanged
 For performing a normal subtraction operation, first clear the carry flag and then call the
SUBB A, <loc> instruction
 The carry (borrow) flag gets modified accordingly on executing this instruction
 If the subtraction results in a –ve number (A less than (<loc> + Carry)), the borrow
(carry) flag is set and the accumulator content will be the 2’s complement representation
of the result 15
2’s complement of a number = 1’s complement of the number + 1
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Programming the 8051 Microcontroller

The 8051 Instruction Set – Arithmetic Instructions
Multiplication and Division Instruction
 The instruction MUL AB multiplies two 8bit unsigned numbers and stores the 16bit result in
the register pair A, B
 Accumulator stores the lower order 8bits of the result and B register stores the higher order
8bits of the result
 The overflow flag (OV) is set when the product is greater than 0FFH and cleared otherwise
 The carry flag becomes cleared state irrespective of the product
 The DIV AB instruction divides the content of accumulator register with the content of B
register and stores the integer part of the quotient (A/B) in accumulator and the modulus (A
%B) in B register
 8051 does not have a divide by zero interrupt mechanism to indicate a divide by zero error.
the divide by zero condition is indicated by setting the overflow flag (OV) in the Program
Status Word (PSW) register. The values returned in A and B are undefined for a divide-by-
zero operation
 The Overflow flag (OV) and carry flag (CY) are cleared for normal division operation
 MUL and DIV instructions are Accumulator and Register B specific instructions. They work
only with these two registers 16
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Programming the 8051 Microcontroller

The 8051 Instruction Set – Arithmetic Instructions
Increment Instruction
 The increment instruction (INC) increments the content of the location pointed by the
operand
 The INC A instruction is an accumulator specific instruction which increments the
content of accumulator. Executing the instruction INC A will not modify the carry flag
 The INC <loc> instruction increments the content pointed by <loc>
 <loc> can be registers B, R0,R1, …R7 or any SFR or an immediate constant or an
internal data memory or an internal data memory pointed indirectly by indirect
addressing register R0 or R1 and @
 If the content pointed by the operand of INC instruction is FFH, on executing the INC
instruction, the content simply rolls over to 00H. None of the status bits are modified to
indicate this rollover
 INC DPTR instruction is DPTR register specific instruction and it increments the
content of 16bit DPTR register by one

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Programming the 8051 Microcontroller

The 8051 Instruction Set – Arithmetic Instructions
Increment Instruction

MOV 00H,#80H ; Load Data memory location 00H (R0) with 80H
MOV A,#0FFH ; Load Accumulator with FFH
MOV DPTR,#00FFH ; Load DPTR with 00FFH
INC 00H ; Increment the contents of Data memory-
; location 00H. It becomes 81H
INC A ; Increment the content of Accumulator. It-
; becomes 00H
INC DPTR ; Increment the content of DPTR Register. It-
; becomes 0100H

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Programming the 8051 Microcontroller

The 8051 Instruction Set – Arithmetic Instructions
Decrement Instruction
 The decrement instruction (DEC) decrements the content of the location pointed by the
operand
 The DEC A instruction is an accumulator specific instruction which decrements the
content of accumulator
 Executing the instruction DEC A will not modify the carry flag
 The DEC <loc> instruction decrements the content pointed by <loc>
 <loc> can be registers B, R0,R1, …R7 or any SFR or an immediate constant or an
internal data memory or an internal data memory pointed indirectly by indirect
addressing register R0 or R1 and @
 If the content pointed by the operand of DEC instruction is 00H, executing the DEC
instruction simply rolls over it to FFH
 None of the status bits of PSW are modified

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Programming the 8051 Microcontroller

The 8051 Instruction Set – Arithmetic Instructions
Decrement Instruction

MOV 00H,#80H ; Load Data memory location 00H (R0) with 80H
MOV A,#0FFH ; Load Accumulator with FFH
DEC 00H ; Decrement the contents of Data memory-
; location 00H. It becomes 7FH
DEC A ; Decrement the content of Accumulator. It-
; becomes FEH

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Programming the 8051 Microcontroller

The 8051 Instruction Set – Logical Instructions
INSTRUCTION ACTION COMMENTS
MNEMONIC
Perform bitwise logical OR the content of Accumulator with the content of
ORL A,<loc> A = A|<loc> <loc> and stores the result in Accumulator. <loc> can be registers B, R0,R1, …
R7, or any SFR, an immediate constant, an internal data memory or an internal
data memory pointed indirectly by indirect addressing register R0 or R1 and @

Bitwise logical OR the content of Accumulator with the content of <loc> and
ORL <loc>,A <loc> = A|<loc> stores the result in memory location <loc>. <loc> can be any SFR or an internal
data memory
Bitwise logical OR the content of <loc> with an immediate constant and stores
ORL <loc>, <loc> = <loc>|const the result in memory location <loc>. <loc> can be any SFR or an internal data
#const memory
Bitwise logical AND the content of Accumulator with the content of <loc> and
ANL A,<loc> A=A&<loc> stores the result in Accumulator. <loc> can be B, R0,R1, …R7, or any SFR, an
internal data memory or an immediate constant or an internal data memory
pointed indirectly by indirect addressing register R0 or R1 and @
Bitwise logical AND the content of Accumulator with the content of <loc> and
ANL <loc>,A <loc> = A&<loc> stores the result in memory location <loc>. <loc> can be any SFR or an internal
data memory
Bitwise logical AND the content of <loc> with an immediate constant and
ANL <loc>, <loc> = <loc>&const stores the result in memory location <loc>. <loc> can be any SFR or an internal
#const data memory
Bitwise logical XOR the content of Accumulator with the content of <loc> and
XRL A,<loc> A = A^<loc> stores the result in Accumulator. <loc> can be B, R0,R1, …R7, or any SFR, an
internal data memory or an immediate constant or an internal data memory
pointed indirectly by indirect addressing register R0 or R1 and @ 21
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Programming the 8051 Microcontroller

The 8051 Instruction Set – Logical Instructions

INSTRUCTION ACTION COMMENTS

MNEMONIC
Logical XOR the content of Accumulator with the content of <loc> and stores
XRL <loc>,A <loc> = A^<loc> the result in memory location <loc>. <loc> can be any SFR or an internal data
memory
Logical XOR the content of <loc> with an immediate constant and stores the
XRL <loc> = <loc> ^ const result in memory location <loc>. <loc> can be any SFR or an internal data
<loc>,#const memory
Clear the content of Accumulator (Loads 0 to Accumulator)
CLR A A = 00H
Complement the content of Accumulator. 1s are replaced by 0s and 0s by 1s.
CPL A A = ~A
Rotate the Accumulator content 1 bit to the left. The MSB of the Accumulator
RL A A= A<1 is shifted out to the LSB position of the Accumulator
Rotate the Accumulator content 1 bit to the left through carry bit. The MSB of
RLC A A= A<1 the Accumulator is shifted out to carry bit and content of carry bit enters at the
LSB position of the Accumulator
Rotate the Accumulator content 1 bit to the right. The LSB of the Accumulator
RR A A= A>1 is shifted out to the MSB position of the Accumulator
Rotate the Accumulator content 1 bit to the right through carry bit. The LSB of
RRC A A= A>1 the Accumulator is shifted out to carry bit and content of carry bit enters at the
MSB position of the Accumulator
Before swap A=Nib2 Nib1 Exchanges between the low nibble and high nibble of Accumulator.
SWAP A After swap
A=Nib1 Nib2
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Programming the 8051 Microcontroller

The 8051 Instruction Set – Boolean Instructions

INSTRUCTION ACTION COMMENTS

MNEMONIC
Bit manipulation & transfer Instructions
MOV C, Bit C = Bit Moves Bit to carry flag
MOV Bit, C Bit = C Moves carry flag to Bit
CLR C C=0 Clears carry flag
CLR Bit Bit = 0 Clears specified Bit
SETB C C=1 Sets carry flag
SETB Bit Bit = 1 Sets specified Bit
Logical Operations on Bits
ANL C, Bit C= C & Bit Logical AND Carry flag with Bit and store the result in Carry flag
Logical AND the complemented value of Bit with Carry flag and
ANL C, /Bit C = C & (.NOT. Bit†) store the result in carry flag
Logical OR Carry flag with Bit and store the result in Carry flag
ORL C, Bit C= C | Bit
Logical OR the complemented value of Bit with Carry flag. Result
ORL C, /Bit C= C | (.NOT. Bit )
††
in carry flag
CPL C C=.NOT.C Complements the carry flag
CPL Bit C=.NOT. Bit Complements Bit

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Programming the 8051 Microcontroller

The 8051 Instruction Set – Boolean Instructions
INSTRUCTION ACTION COMMENTS
MNEMONIC
Program Control transfer based on Bit status

JC rel If (C) Jump to the relative address ‘rel’ if Carry flag is 1

Jump to rel
If (!C) Jump to the relative address ‘rel’ if Carry flag is 0
JNC rel Jump to rel
If (Bit) Jump to the relative address ‘rel’ if the specified Bit is 1
JB Bit, rel Jump to rel
If (!Bit) Jump to the relative address ‘rel’ if the specified Bit is 0
JNB Bit, rel Jump to rel
If (Bit)
JBC Bit, rel { If the specified Bit is 1, clear the bit and jump to the
Clear Bit; relative address ‘rel’
Jump to rel;
}

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Programming the 8051 Microcontroller

The 8051 Instruction Set – Unconditional program control transfer instructions
INSTRUCTION COMMENTS
MNEMONIC
JMP address Jump to the specified address
JMP @A+DPTR Jump to the address (A+DPTR)
CALL address Call subroutine located at the code memory ‘address’
RET Return from a subroutine
RETI Return from an Interrupt routine
NOP No operation (Do nothing)
 The instruction JMP represents three type of Jumps; namely SJMP, LJMP and AJMP and they are used in
appropriate contexts
 SJMP instruction stands for Short Jump. The destination address is given as an offset to the current address held
by the Program Counter (PC). The jump distance for the SJMP instruction is limited to the range of -128 to +127
bytes relative to the instruction following the jump
 LJMP instruction stands for Long Jump. The destination address for LJMP is given as the real physical address
(16bit wide) of the code memory location to which the jump is intended
 AJMP stands for absolute jump. The AJMP instruction encodes the destination address as 11 bit constant. The
instruction is two byte long consisting of the opcode, which itself contains higher 3 bits of the 11 bit constant
 AJMP implements jumps within a memory block of 2K
 If the programmer is not interested in analyzing the contexts, he/she can simply use the JMP instruction.
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Programming the 8051 Microcontroller

The 8051 Instruction Set – Unconditional program control transfer instructions
 The subroutine calling instruction CALL is of two types; namely LCALL and ACALL.
 LCALL is a three byte instruction of which the first byte represents the opcode and the
second and third bytes hold the physical address of the program memory where the
subroutine, which is to be executed, is located.
 ACALL is similar to AJMP. ACALL is a two byte instruction of which the first byte holds
the opcode as well as the higher 3 bits of the 11 bit address of the location where the
subroutine is located. The second byte holds the remaining 8 bits of the address location.
 ACALL implements subroutine calls within a memory block of 2K
 RET instruction performs return from a subroutine call. Executing the RET instruction
brings the program flow back to the instruction following the CALL to the subroutine
 RETI performs the return from an interrupt routine. RETI instruction is similar to the
RET instruction in all respect except that the RETI informs the interrupt system that the
interrupt in progress is serviced
 The NOP instruction does not perform anything specific. It simply forces the CPU to
wait for one machine

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Programming the 8051 Microcontroller

The 8051 Instruction Set – Conditional program control transfer instructions

INSTRUCTIO ACTION COMMENTS

N
MNEMONIC
If (A == 0) Jump to the relative address ‘rel’ if Accumulator content is zero
JZ rel Jump to ‘rel’
If (A != 0) Jump to the relative address ‘rel’ if Accumulator content is non zero
JNZ rel Jump to ‘rel’
Decrement the contents of <loc> and jumps to the relative address ‘rel’ if
DJNZ <loc>, <loc>=<loc>-1 content of <loc> is non zero
rel If(<loc>!=0) <loc> can be a direct memory or scratch pad registers R0 through R7 or
Jump to ‘rel’ any SFR
Compares the content of Accumulator with the content of <loc> and
CJNE A, <loc>, If (A!=<loc>) jumps to the relative address ‘rel’ if both are not equal. <loc> can be a
rel Jump to ‘rel’ direct memory or an immediate constant.
Compares the content of <loc> with an immediate constant and jumps to
CJNE <loc>, If (<loc>!= #data) the relative address ‘rel’ if both are not equal. <loc> can be a memory
#data, rel Jump to ‘rel’ pointed indirectly or register R0 through R7 or Accumulator.
 All the conditional branching instructions specify the destination address by relative offset method and so the
jump locations are limited to -128 to +127 bytes from the instruction following the conditional jump instruction
 Unlike the 8085 and 8086 CPU architecture, there is no Zero flag for 8051. The instructions JZ and JNZ
instructions implement the zero flag check functionality by checking the Accumulator content for zero
 DJNZ instruction is used for setting up loop control and generating delays
 CJNE instruction compares two variables and check whether they are equal
 CJNE instruction in combination with the Carry flag can be used for testing the conditions ‘greater than’, ‘greater
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than or equal’ and ‘less than