MOSFET

Dr. S L Pinjare
[email protected]

9/27/2020

1
 Introduction
• Mosfet is a 4 terminal device Source, Drain, Gate and Body

Vgs = 0 Vgd
+ g +
- -
s d
n+ n+

p-type body
b

2
• When transistor is on , It passes a finite amount of current
– The current depends on the terminal voltages

• Derive current-voltage (I-V) relationships

3
 MOS Capacitor
• Transistor gate, source, drain all
have capacitance
– Capacitance and current Vg < 0
polysilicon gate
silicon dioxide insulator

determine speed +
- p-type body

– I = C (DV/Dt) -> Dt = (C/I)

(a)

DV
• Gate and body form MOS
0 < Vg < V t
depletion region
+
-
capacitor
• Operating modes (b)

– Accumulation Vg > Vt
inversion region

– Depletion
+
- depletion region

– Inversion (c)

Slide 4
3: CMOS Transistor Theory 4
 Terminal Voltages
• Mode of operation depends on the terminal voltages V g, Vd, Vs
– Vgs = Vg – Vs
– Vgd = Vg – Vd Vg

– Vds = Vd – Vs = Vgs - Vgd +

Vgs
+
Vgd
• Source and drain are symmetric diffusion terminals - -
– By convention, source terminal is at lower voltage Vs
- +
Vd
Vds
– Hence Vds  0
• nMOS body is grounded. First assume source is 0 too.
• Three regions of operation
– Cutoff
– Linear
– Saturation

Slide 5
3: CMOS Transistor Theory 5
 nMOS Cutoff
• No channel
• Vgs = 0 , Vgs <vth
• Ids = 0

Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b

Slide 6
3: CMOS Transistor Theory 6
 nMOS Linear
• As Vgs increases , the Channel forms when Vgs > Vth the
threshold voltage and Vds< Vgs-Vth,
• Current flows from d to s V > V
gs t V =V
g
– e- from s to d + + gd gs

- -
s
• Ids increases with Vds d
V =0
n+ n+ ds

• Similar to linear resistor

p-type body
b

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b

7
 nMOS Saturation
• As Vgs increases beyond Vth, the Channel is pinched off if
Vds>Vgs-Vth forms when Vgs > Vth the threshold voltage
– Ids independent of Vds
• We say current saturates and the transistor acts like a
constant current source.
Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

3: CMOS Transistor Theory 8

 I-V Characteristics
• In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?

Slide 9
3: CMOS Transistor Theory 9
 Channel Charge
• MOS structure looks like parallel plate capacitor while
operating in inversion
– Gate – oxide – channel
• Qchannel =

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

Slide 10
3: CMOS Transistor Theory 10
 Channel Charge
• MOS structure looks like parallel plate capacitor while
operating in inversion
– Gate – oxide – channel
• Qchannel = CV
• C=

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

Slide 11
3: CMOS Transistor Theory 11
 Channel Charge
• MOS structure looks like parallel plate capacitor while
operating in inversion
– Gate – oxide – channel
• Qchannel = CV
• C = Cg = eoxWL/tox = CoxWL Cox = eox / tox
• V=

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

Slide 12
3: CMOS Transistor Theory 12
 Channel Charge
• MOS structure looks like parallel plate capacitor while
operating in inversion
V = Vgc – Vt = Vg –Vc –Vt
– Gate – oxide – channel
=Vg-(Vd+Vs)/2 -Vt
• Qchannel = CV =Vg-Vs+Vs-Vs/2-vd/2-Vt
=vgs-(Vd/2-Vs/2)-Vt
• C = Cg = eoxWL/tox = CoxWL =(V – V /2) – V gs ds Cox = et ox / tox
• V = Vgc – Vt = (Vgs – Vds/2) – Vt

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

Slide 13
3: CMOS Transistor Theory 13
 Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to lateral E-field between
source and drain
• v=

Slide 14
3: CMOS Transistor Theory 14
 Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to lateral E-field between
source and drain
• v = mE m called mobility
• E=

Slide 15
3: CMOS Transistor Theory 15
 Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to lateral E-field between
source and drain
• v = mE m called mobility
• E = Vds/L
• Time for carrier to cross channel:
– t=

Slide 16
3: CMOS Transistor Theory 16
 Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to lateral E-field between
source and drain
• v = mE m called mobility
• E = Vds/L
• Time for carrier to cross channel:
– t =L/ v
– = L/uE =L L/(u Vds)

Slide 17
3: CMOS Transistor Theory 17
 nMOS Linear I-V
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross

I ds 

Slide 18
3: CMOS Transistor Theory 18
 nMOS Linear I-V
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross

Qchannel
I ds 
t

– Q=CV=CoxWL (Vgs-Vds/2-Vth)
– t=L2/Vds

Slide 19
3: CMOS Transistor Theory 19
 nMOS Linear I-V
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross

– Qchannel = Cox W L(Vgs-Vth-Vds/2)/(L L/(uVds))

I ds 
– t =
W  V  V  Vds V
Cox  gs  ds
L 
t 2 
V W
  Vgs  Vt  ds  Vds  = Cox
 2 L

Slide 20
3: CMOS Transistor Theory 20
 nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current

I ds 

Slide 21
3: CMOS Transistor Theory 21
 nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current
• I  u Cox (W/L)(vgs-Vth-(vgs-Vth)/2)(Vgs-Vth)
ds

V
I ds   Vgs  Vt  dsat V
 dsat
 2 

W
 = Cox
L

Slide 22
3: CMOS Transistor Theory 22
 nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current

V
I ds   Vgs  Vt  dsat V
 dsat
 2 

  Vt 
2
 V gs
2
W
 = Cox
L

Slide 23
3: CMOS Transistor Theory 23
 nMOS I-V Summary
• Shockley 1st order transistor models

 0 Vgs  Vt cutoff

  V V V  V
I ds    Vgs  Vt  ds  ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2
W
 = Cox
L

Slide 24
3: CMOS Transistor Theory 24
 Example
• 0.6 mm process (Example)
– From AMI Semiconductor
– tox = 100 Å
– m = 350 cm2/V*s 2.5
Vgs = 5
– Vt = 0.7 V 2

• Plot Ids vs. Vds 1.5 Vgs = 4

Ids (mA)
– Vgs = 0, 1, 2, 3, 4, 5 1
Vgs = 3
– Use W/L = 4/2 l 0.5
Vgs = 2
Vgs = 1
0
0 1 2 3 4 5
W  3.9  8.85 10 14   W  W Vds
 Cox 350   8   120  A /V 2
L  100 10  L  L

Slide 25
3: CMOS Transistor Theory 25
 pMOS I-V
• All dopings and voltages are inverted for pMOS
• Mobility mp is determined by holes
– Typically 2-3x lower than that of electrons mn
– 120 cm2/V*s in AMI 0.6 mm process
• Thus pMOS must be wider to provide same current
– assume mn / mp = 2

Slide 26
3: CMOS Transistor Theory 26
MOSFET Characterstics

27
 MOS Characterstics
• Setup model library
• Tsmc180nm.lib

28
Tsmc018.lib

29
Tsmc018.lib

30
NMOS Characterstics
idsVs Vgs

31
NMOS Characterstics
idsVs Vgs

32
NMOS Characterstics
idsVs Vds

33
34
Ids vs vgs

35
36
• Measure Vth = .46 V
• Lambda= gds/Id = 1.81e-5/3.86e-4=.047
• W/L= 600/180

37
NMOS Characterstics
.op

38
 NMOS Characterstics
.op
• Ids Vs Vgs
• Ids vs Vds

39
NMOS Characterstics
.op

40
NMOS Characterstics
.op

41
 NMOS Characterstics
.op
• Vth= .388
• Gds=8.86e-6
• Id=1.73e-4
• Lambda=gds/Id=.005
• Gm= 1.29e-4
• Vdsat=.42
• Kp=Ucox = gm/vdsat= 307 uA/V2

42
pmos characterstics

43
 PMOS Characterstics
• W=1275nm
• L=180nm

44
45
46
Ids vs vds

47
Ids Vs Vgs

48
PMOS Characterstics
.op

49
PMOS Characterstics
.op

50
• Vth= .39
• Gds=5.19e-6
• Id=8.47e-5
• Lambda=gds/Id=.061
• Gm= 1.02e-4
• Vdsat=.891
• Kp=Ucox = gm/vdsat= 114 uA/V2

51
• 1 Shichman-Hodges
• 2 MOS2(see A. Vladimirescu and S. Liu, The Simulation of
MOS Integrated Circuits Using SPICE2, ERL Memo No.
M80/7, Electronics Research Laboratory University of
California, Berkeley, October 1980)
• 3 MOS3, a semi-empirical model(see reference for level 2)
• 4 BSIM (see B. J. Sheu, D. L. Scharfetter, and P. K. Ko,
SPICE2 Implementation of BSIM. ERL Memo No. ERL
M85/42, Electronics Research Laboratory University of
California, Berkeley, May 1985)
• 5 BSIM2 (see Min-Chie Jeng, Design and Modeling of Deep-
Submicrometer MOSFETs ERL Memo Nos. ERL M90/90,
Electronics Research Laboratory University of California,
Berkeley, October 1990)
52
• 6 MOS6 (see T. Sakurai and A. R. Newton, A Simple
MOSFET Model for Circuit Analysis and its application to
CMOS gate delay analysis and series-connected MOSFET
Structure, ERL Memo No. ERL M90/19, Electronics Research
Laboratory, University of California, Berkeley, March 1990)
• 8 BSIM3v3.3.0 from University of California, Berkeley as of
July 29, 2005
• 9 BSIMSOI3.2 (Silicon on insulator) from the BSIM
Research Group of the University of California, Berkeley,
February 2004.

53
• 12 EKV 2.6 based on code from Ecole Polytechnique
Federale de Lausanne. See http://legwww.epfl.ch/ekv and
"The EPFL-EKV MOSFET Model Equations for Simulation,
Version 2.6", M. Bucher, C. Lallement, F. Theodoloz, C. Enz,
F. Krummenacher, EPFL-DE-LEG, June 1997.
• 14 BSIM4.6.1 from the University of California, Berkeley
BSIM Research Group, May 18, 2007.
• 73 HiSIMHV version 1.2 from the Hiroshima University and
STARC.

54
 ucox
• From the TSMC.lib file
• Un = 273.809 cm2V/S up = 115.689cm2 V/s
• Tox = 4.1e-9 εox = 3.9εo = 3.9(8.854x10–12 F/m)

• Un/up = 2.366

• Cox =8.422 fF/um2

• Uncox = 230.6uA/v2
• Upcox = 97.43uA/v2

55
• W = 180n
• L = 180n

• Plot sqrt of Id vs Vgs and from slope determine the value of

ucox

56
57
58
• From maximum value nmos
• 21.6346ma^1/2 /V2
• Ucox = 468.07uA/V2
• W=L=180nm

• W=L=1u
• 15.40088ma^1/2 /V2
• Ucox = 237.2uA/v2

59
60
61
• From maximum value pmos
• 9.6555ma^1/2 /V2
• Ucox = 93.25uA/V2
• W=L=180nm

• W=L=1u
• 7.40665ma^1/2 /V2
• Ucox = 54.858uA/v2

62
• Determine Cin by simulation
• Determine Channel resistance in saturation region.

63
 Input Capacitance
• Delay = .69RC
• R= 1449 ohm
• C = delay/1449*.69= ~delay/1000 = (delay in ps ) fF

64
Input capacitance

65
• R= 1449 ohm
• Tdn = 6.79ps Cin = 6.8 fF
• Tdp = 6.15 ps Cin = 6.2 fF
• 1 micron gate length and width

66
Input capacitance

67
• W=L =180nm
• R =1449 Ohm
• Tdn = 0.459ps Cin = 0.459 fF
• Tdp = 0.350ps Cin = 0.350 fF

68
Gate Capacitance

69
• Gate Capacitance
• R= 1449 Ohm
• W=L=1um
• Tdn=7.62ps
• Tdp=4.71ps
• Cgbn =7.62fF
• Cgbp =4.71 fF

70