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Unipolar Logic Family (2

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36 views17 pages

Unipolar Logic Family (2

Uploaded by

shaunakchakraborty38
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Unipolar

logic family
Presented by kajal kumari
What is logic family?????
• Digital circuits are basically constructed with integrated circuits . An
integrated circuits is small silicon semiconductor crystal contains
electronics &electrical components such as
diode ,transistor ,resistor,&capacitors.the integrated circuit in short
can also termed as MONOLITHIC CHIP. The digital circuits operate
with binary singnals and made up of interconnected digital gates .
A “logic family” may also refer as a collection of different ICs that have
similar input, output and internal circuit characteristics i.e. group of
compatible ICs with same logic levels and supply voltages but perform
different logic functions

• (Classification of Logical Families)


• Depletion Type MOSFET: The transistor requires the Gate-Source voltage, (VGS) to
switch the device OFF. The depletion mode MOSFET is equivalent to a Normally Closed
switch. It is abbreviated as DE-MOSFET
• Enhancement Type MOSFET: The transistor requires a Gate-Source voltage, (VGS) to
switch the device ON. The enhancement mode MOSFET is equivalent to a Normally
Open switch. It is abbreviated as E-MOSFET.
Symbol of Mosfet
PMOS ,NMOS,CMOS
• In digital circuits, MOSFETs are categorized into 3 types:
• 1) PMOS: Uses ONLY P-Channel Enhancement MOSFET
• 2) NMOS: Uses ONLY N-Channel Enhancement MOSFET &
• 3) CMOS: Uses both P-Channel & N-Channel Enhancement
MOSFETs. CMOS stands for “Complementary MOSFET”.
PMOS,(INVERTER,NAND GATE OR NOR
GATE)
PMOS Inverter Gate PMOS NAND GATE:

𝐀 𝐁 𝐘 = 𝐀𝐁̅̅̅̅
Inputs ↓ MOSFET Operation ↓ Outputs ↓
Q1 Q2 Q3
Vin Q1 Q2 Vout 0 0 OFF ON ON 1
0 1 OFF ON OFF 1
0 OFF ON 1 1 0 OFF OFF ON 1

1 ON OFF 0 1 1 ON OFF OFF 0


PMOS NOR Gate

𝐀 𝐁 𝐘 = 𝐀+𝐁̅̅̅̅̅̅̅̅
Inputs ↓ MOSFET Operation ↓ Outputs ↓
Q1 Q2 Q3
0 0 OFF ON ON 1
0 1 ON ON OFF 0
1 0 ON OFF ON 0
1 1 ON OFF OFF 0
ADVANTAGE AND
DISADVANTAGE
•
• ADVANTAGES OF PMOS FAMILY:
• i. PMOS are economical.
• ii. PMOS can be implemented in LSI level due to inner circuit complexity.

• DISADVANTAGES OF PMOS FAMILY:


• i. PMOS based logic gates suffer from Static Power Dissipation. This means that they consume power at static
input conditions (i.e. inputs are NOT changing).
• ii. PMOS Fabrication is NOT preferred in VLSI & ULSI designs.
• iii. PMOS based logic circuits work at LESS operating speed, as the majority current carries in the PMOS are
Holes.
NMOS INVERTER, NAND & NOR GATESNMOS INVERTER GATE:
Vin Q1 Q2 Vout
0 ON OFF 1
1 ON ON 0

NMOS NAND GATE:

𝐀 𝐁 𝐘 = 𝐀+𝐁̅̅̅̅̅̅̅̅
Inputs ↓ MOSFET Operation ↓ Outputs ↓
Q1 Q2 Q3
0 0 OFF OFF OFF 1
0 1 ON OFF ON 0
1 0 ON ON OFF 0
1 1 ON ON ON 0
NMOS NOR GATE:

Inputs ↓ MOSFET Operation ↓ Outputs ↓


𝐀 𝐁 Q1 Q2 Q3 𝐘 = 𝐀+𝐁̅̅̅̅̅̅̅̅

0 0 OFF OFF OFF 1


0 1 ON OFF ON 0
1 0 ON ON OFF 0
1 1 ON ON ON 0
the advantages and disadvantages of NMOS
gates
Advantage.
•.number of duffision steps required is the lowest Hence pr gate is lowest.
• NMOS is also Quicker then PMOS
• Power suppy can be varied from 5v to 15 v possible
• Very low pawer dissipation.

• Disadvantage
• MOS transistors are also capacitors. Hence, speed of operation is lowest due to
very high capacitive loading.
• 2. Large propagation delay per gate.
• 3. Higher power dissipation than CMOS gates.
• 4. This technology has not acquired as much popularity as the CMOS technology.
CMOS, because of its lower power dissipation and higher speed of operation has
replaced NMOS almost completely.
CMOS FAMILY(CMO INVERTER )

Vin Q1 Q2 Vout
0 ON OFF 1
1 OFF ON
CMOS NAND
Gate Inputs Operating Regions Gate Output
A B Q1 Q2 Q3 Q4
Y
0 0 Saturation
Q1 = ON Saturation
Q2 = ON Cut-off
Q3= OFF Cut-off
Q4 = OFF 1
0 1 Saturation
Q1 = ON Cut-off
Q2 = OFF Cut-off
Q3= OFF Saturation
Q4 = ON 1
1 0 Cut-off
Q1 = OFF Saturation
Q2 = ON Saturation
Q3= ON Cut-off
Q4 = OFF 1
Inputs Operating Regions Gate Output
CMOS NOR GATE
A
Y
B Q1 Q2 Q3 Q4

0 0 Saturation
Q1 = ON Saturation
Q2 = ON Cut-off
Q3= OFF Cut-off
Q4 = OFF 1
0 1 Saturation
Q1 = ON Cut-off
Q2 = OFF Cut-off
Q3= OFF Saturation
Q4 = ON 0
1 0 Cut-off
Q1 = OFF Saturation
Q2 = ON Saturation
Q3= ON Cut-off
Q4 = OFF 0
1 1 Cut-off
Q1 = OFF Cut-off
Q2 = OFF Saturation
Q3= ON Saturation
Q4 = ON 0
Advantage
• Simple structure,
• Low power consumption
• Large noise tolerance
• Strong temperature stability
• Lower propagation delay then Nmos
• Higher speed than NMOS

• Disadvantage
1) Operating Speed: The main disadvantage of CMOS logic
family is their slow speed of operation.
2) Propagation Delay: The propagation delay time for
CMOS logic family is around 50 ns to 120 ns whereas for
TTL logic family it is 4 to 12 ns
CMOS APPLICATIONS

• The CMOS has been used for the following digital IC


designs:
• 1) Computer memories, CPUs
• 2) Microprocessor designs
• 3) Flash memory chip designing
• 4) Used to design application-specific integrated circuits
(ASICs

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