Digital Design

Chapter 4:
Datapath Components
Slides to accompany the textbook Digital Design, First Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2007.
http://www.ddvahid.com

Copyright © 2007 Frank Vahid

Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities,
Digital
subject to keeping Design
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Frank Vahid
may obtain PowerPoint source or obtain special use permissions from Wiley – see http://www.ddvahid.com for information.
 4.1

Introduction
• Chapters 2 & 3: Introduced increasingly complex digital building
blocks
– Gates, multiplexors, decoders, basic registers, and controllers
• Controllers good for systems with control inputs/outputs
– Control input: Single bit (or just a few), representing environment event or
state
• e.g., 1 bit representing button pressed
– Data input: Multiple bits collectively representing single entity
• e.g., 7 bits representing temperature in binary
• Need building blocks for data si
ansis
– Datapath components, aka register-transfer-level (RTL) components,
store/transform data
ez
• Put datapath components together to form a datapath
• This chapter introduces numerous datapath components, and simple
datapaths
– Next chapter will combine controllers and datapaths into “processors”
Digital Design
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Frank Vahid Note: Slides with animation are denoted with a small red "a" near the animated items
 4.2

Registers
b x
• Can store data, very common in datapaths Combinational n1
logic
• Basic register of Ch 3: Loaded every cycle n0
s1 s0
– Useful for implementing FSM -- stores encoded state clk State register
– For other uses, may want to load only on certain
cycles
a
I3 I2 I1 I0
load 4-bit register
I3 I2 I1 I0
D D D D
reg(4)
Q Q Q Q
si
ansisQ3 Q2 Q1 Q0
clk

Q3 Q2 Q1 Q0
ez
Basic register loads on every clock cycle
How extend to only load on certain cycles?

Digital Design
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Frank Vahid
 Register with Parallel Load
• Add 2x1 mux to front of each flip-flop
• Register’s load input selects mux input to pass
– Either existing flip-flop value, or new value to load

I3 I2 I1 I0

1 0 1 0 1 0 1 0
load 2× 1 I3 I2 I1 I0
load
D D D D
Q3 Q2 Q1 Q0
Q Q Q Q

Q3 Q2 Q1 Q0
(a) (c)

I3 I2 I1 I0 I3 I2 I1 I0
load = 0

load = 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

D D D D D D D D

Q Q Q Q Q Q Q Q
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
Digital Design (b)
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Frank Vahid
 Basic Example Using Registers
a3 a2 a1 a0

1 ld I3 I2 I1 I0
• This example will show how clk R0
registers load simultaneously Q3 Q2 Q1 Q0

on clock cycles
– Notice that all load inputs set to
1 in this example -- just for
demonstration purposes
1 ld I3 I2 I1 I0 1 ld I3 I2 I1 I0
R1 R2
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

Digital Design
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Frank Vahid
 Basic Example Using Registers
clk
1 2 3 4 5
given

(a)
a3..a0 1111 0001 1010

R0 ???? 1111 0001 1010 1010 1010

R1 ???? ???? 1111 0001 1010 1010

R2 ???? ???? 0000 1110 0101 0101

–>1111 1111–>0001 0001–>1010 1010 1010 1010
a3 a2 a1 a0

1 ld I3 I2 I1 I0
R0
???? R0 1111 R0 0001 R0 1010 R0 1010 R0 1010 R0
clk
Q3 Q2 Q1 Q0 (b)

???? ???? ???? ???? 1111 0000 0001 1110 1010 0101 1010 0101
R1 R2 R1 R2 R1 R2 R1 R2 R1 R2 R1 R2
1 ld I3 I2 I1 I0 1 ld I3 I2 I1 I0
R1 R2
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

Digital Design
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Frank Vahid
 Register Example using the Load Input:
Weight Sampler
• Scale has two displays
– Present weight
– Saved weight Scale Weight Sampler
– Useful to compare 0010
1
present item with previous
item Save
b 1 I3 I2 I1 I0 a
23 pounds load
• Use register to store clk
0011
Present weight Q3 Q2 Q1 Q0
weight
– Pressing button causes
present weight to be 3 pounds
stored in register Saved weight
• Register contents
always displayed as
“Saved weight,” even
when new present
weight appears
Digital Design
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Frank Vahid
 Register Example: Temperature History Display
• Recall Chpt 3 example
– Timer pulse every hour
– Previously used as clock. Better design only connects oscillator to
clock inputs -- use registers with load input, connect to timer pulse.

a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
I4 Q4 I4 Q4 I4 Q4
t4 I4 Q4 I4 Q4 I4 Q4
x4 I3 Q3 I3 Q3 I3 Q3
t3 I3 Q3 I3 Q3 I3 Q3
x3 I2 Q2 I2 Q2 I2 Q2
t2 I2 Ra Q2 I2 Rb Q2 I2 RcQ2
x2 I1 Q1 I1 Q1 I1 Q1
t1 I1 Q1 I1 Q1 I1 Q1
x1 I0 Q0 I0 Q0 I0 Q0
t0 I0 Q0 I0 Q0 I0 Q0
x0
ld ld ld
Clk Ra Rb Rc
osc C
C TemperatureHistoryStorage
a timer new line TemperatureHistoryStorage

Digital Design
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Frank Vahid
 Register Example: Above-Mirror Display
8

Shorthand notation
a

0001010
C 8 Loaded on clock edge
ert d0 load reg0 T

ompuc 2 4 i0
o mi
theT ab
om the al
rtcar's 1
8
r
8-bit or displ
• Ch2 example: Four r n
F ec 0
a0
d1 load reg1 A 4× 1
0001010
ay o
simultaneous values from i0
car’s computer 1 8
i1 ve
i1
a1 d D
• To reduce wires: Computer d2 load reg2 I 8
writes only 1 value at a time, i2
loads into one of four 8
registers d3 load reg3 M
e
– Was: 8+8+8+8 = 32 wires 1
load i3 s1 s0
– Now: 8 +2+1 = 11 wires 8
Digital Design
x y
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Frank Vahid
 Register Example: Computerized Checkerboard
LED
• Each register lit LED

holds values for 1

one column of 0
lights 1
– 1 lights light
0
• Microprocessor
0
loads one
0
register at a time
– Occurs fast 1

enough that 0
user sees Q
R7 R6 R5 R4 R3 R2 R1 R0 R0 10100010
entire board I load
change at once d7 d6 d5 d4 d3 d2 d1 d0
8 e i2 i1 i0 3× 8 decoder from from
microprocessor decoder
D (b)
microprocessor
Digital Design (a)
Copyright © 2006 10
Frank Vahid
Register Example: Computerized Checkerboard
LED

lit LED

R7 R6 R5 R4 R3 R2 R1 R0
10100010 10100010 10100010 10100010
01000101 01000101 01000101 01000101

D 10100010 010000101 10100010 010000101 10100010 010000101 10100010 010000101

i2,i1,i0 000 (R0) 001 (R1) 010 (R2) 011 (R3) 100 (R4) 101 (R5) 110 (R6) 111 (R7)

e
clk

Digital Design
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Frank Vahid
 Shift Register
Register contents
1 1 0 1
before shift right
• Shift right 0
a

– Move each bit one position right 0 1 1 0

Register contents
after shift right
– Shift in 0 to leftmost bit

Q: Do four right shifts on 1001, showing value after each shift

a

A: 1001 (original)
0100
• Implementation: Connect flip-flop
0010 output to next flip-flop’s input
0001 a
shr_in
0000

Digital Design
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Frank Vahid
 Shift Register
• To allow register to either shift or retain, use 2x1 muxes
– shr: 0 means retain, 1 shift
– shr_in: value to shift in
• May be 0, or 1
• Note: Can easily design shift register that shifts left instead
shr_in

shr=1
shr 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
2× 1 2× 1
D D D D
D D D D
Q Q Q Q
Q Q Q Q
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0 (b)
(a)
shr_in
shr

Q3 Q2 Q1 Q0
Digital Design
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Frank Vahid
 Rotate Register

Register contents
1 1 0 1
before shift right
• Rotate right: Like shift right,
Register contents
but leftmost bit comes from 1 1 1 0
after shift right

rightmost bit

Digital Design
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Frank Vahid
 Shift Register Example: Above-Mirror Display

From the car's

es
ter
C

centralcompu
8

• Earlier example: 8 d0 load

wir
reg0 T

mi
To the ab
2× 4 i0

rror displ
8

+2+1 = 11wires from a0

d1 load reg1 A
8-bit
4× 1

ove
11
i0

ay
i1

car’s computer to a1
i1
d2 load reg2 I
8
d
8
D

above-mirror display’s
i2
8
d3 load reg3 M
e

four registers load

8
i3 s1 s0

x y

– Better than 32 wires,

Note: this line is 1 bit, rather than 8 bits like before
but 11 still a lot -- x y
c
want fewer for shr_in
d0 shr reg0 T
smaller wire bundles s1 s0
2 4 i0
• Use shift registers shr_in
8
4×1
shr reg1
– Wires: 1+2+1=4 d1 A
a0 i0
i1
– Computer sends one a1 i1 8
shr_in
value at a time, one d2 shr reg2
d
8
D
I
bit per clock cycle i2
8
shr_in
shr reg3
e d3 M
Digital Design shift i3
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Frank Vahid
 Multifunction Registers
• Many registers have multiple functions
– Load, shift, clear (load all 0s)
– And retain present value, of course Functions:
• Easily designed using muxes s1 s0 Operation
0 0 Maintain present value
– Just connect each mux input to achieve 0 1 Parallel load
desired function 1 0 Shift right
1 1 (unused - let's load 0s)
shr_in I3 I2 I1 I0
0 0 0 0
s1 3 2 1 0 321 0 321 0 321 0
s0 4× 1 shr_in I3 I2 I1 I0
s1
D D D D s0
Q3 Q2 Q1 Q0
Q Q Q Q

(b)
Q3 Q2 Q1 Q0
(a)
Digital Design
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Frank Vahid
 Multifunction Registers

s1 s0 Operation
0 0 Maintain present value
0 1 Parallel load
1 0 Shift right
1 1 Shift left

I3 I2 I1 I0

shr_in
shl_in

321 0 321 0 321 0 321 0

shl_in I3 I2 I1 I0
shr_in
D D D D s1
s0

Q Q Q Q Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0
(a) (b)
Digital Design
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Frank Vahid
 Multifunction Registers with Separate Control
Inputs
ld shr shl Operation
0 0 0 Maintain present value
0 0 1 Shift left
0 1 0 Shift right
0 1 1 Shift right – shr has priority over shl
1 0 0 Parallel load
1 0 1 Parallel load – ld has priority I3 I2 I1 I0
1 1 0 Parallel load – ld has priority shr_in
1 1 1 Parallel load – ld has priority I3 I2 I1 I0
ld shr_in
s1 shl_in

?
combi- shl_in
shr national s0
Truth table for combinational circuit circuit Q3 Q2 Q1 Q0
shl
Inputs Outputs Note
ld shr shl s1 s0 Operation Q3 Q2 Q1 Q0
0 0 0 0 0 Maintain value
0 0 1 1 1 Shift left a
0 1 0 1 0 Shift right
0 1 1 1 0 Shift right
1 0 0 0 1 Parallel load s1 = ld’*shr’*shl + ld’*shr*shl’ + ld’*shr*shl
1 0 1 0 1 Parallel load
1 1 0 0 1 Parallel load s0 = ld’*shr’*shl + ld a
1 1 1 0 1 Parallel load

a
Digital Design
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Frank Vahid
 Register Operation Table
• Register operations typically shown using compact version of table
– X means same operation whether value is 0 or 1
• One X expands to two rows
• Two Xs expand to four rows
– Put highest priority control input on left to make reduced table simple

Inputs Outputs Note

ld shr shl s1 s0 Operation ld shr shl Operation
0 0 0 0 0 Maintain value 0 0 0 Maintain value
0 0 1 1 1 Shift left 0 0 1 Shift left
0 1 0 1 0 Shift right 0 1 X Shift right
0 1 1 1 0 Shift right 1 X X Parallel load
1 0 0 0 1 Parallel load
1 0 1 0 1 Parallel load
1 1 0 0 1 Parallel load
1 1 1 0 1 Parallel load

Digital Design
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Frank Vahid
 Register Design Process
• Can design register with desired operations using simple
four-step process

Digital Design
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Frank Vahid
 Register Design Example
s2 s1 s0 Operation
• Desired register operations 0 0 0 Maintain present value
0 0 1 Parallel load
– Load, shift left, synchronous clear, 0 1 0 Shift left
synchronous set 0 1 1 Synchronous clear
1 0 0 Synchronous set
1 0 1 Maintain present value
Step 1: Determine mux size 1 1 0 Maintain present value
1 1 1 Maintain present value
5 operations: above, plus maintain In
1 0 from
a present value (don’t forget this one!) Qn-1
--> Use 8x1 mux s2
s1 7 6 5 4 3 2 1 0
s0
Step 2: Create mux operation table
D
Step 3: Connect mux inputs Q

Qn
Step 4: Map control lines Inputs Outputs
s2 = clr’*set clr set ld shl s2 s1 s0 Operation
0 0 0 0 0 0 0 Maintain present value
s1 = clr’*set’*ld’*shl + clr
0 0 0 1 0 1 0 Shift left
s0 = clr’*set’*ld + clr 0 0 1 X 0 0 1 Parallel load
0 1 X X 1 0 0 Set to all 1s
Digital Design 1 X X X 0 1 1 Clear to all 0s
Copyright © 2006 21
a
Frank Vahid
 Register Design Example

I3 I2 I1 I0

shl I3 I2 I1 I0
s2
s1 shl_in
ld combi- s0 shl_in
national
set
circuit Q3 Q2 Q1 Q0
clr
Q3 Q2 Q1 Q0

Step 4: Map control lines Inputs Outputs

s2 = clr’*set clr set ld shl s2 s1 s0 Operation
0 0 0 0 0 0 0 Maintain present value
s1 = clr’*set’*ld’*shl + clr
0 0 0 1 0 1 0 Shift left
s0 = clr’*set’*ld + clr 0 0 1 X 0 0 1 Parallel load
0 1 X X 1 0 0 Set to all 1s
Digital Design 1 X X X 0 1 1 Clear to all 0s
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Frank Vahid
 4.3

Adders
• Adds two N-bit binary numbers Inputs Outputs
a1 a0 b1 b0 c s1 s0
– 2-bit adder: adds two 2-bit numbers, 0 0 0 0 0 0 0
0 0 0 1 0 0 1
outputs 3-bit result 0 0 1 0 0 1 0
– e.g., 01 + 11 = 100 (1 + 3 = 4) 0
0
0
1
1
0
1
0
0
0
1
0
1
1
• Can design using combinational 0
0
1
1
0
1
1
0
0
0
1
1
0
1
design process of Ch 2, but doesn’t 0
1
1
0
1
0
1
0
1
0
0
1
0
0
work well for reasonable-size N 1 0 0 1 0 1 1
1 0 1 0 1 0 0
– Why not? 1 0 1 1 1 0 1
1 1 0 0 0 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 1
1 1 1 1 1 1 0

Digital Design
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Frank Vahid
 Why Adders Aren’t Built Using Standard 4.3

Combinational Design Process

• Truth table too big Inputs Outputs
– 2-bit adder’s truth table shown a1 a0 b1 b0 c s1 s0
0 0 0 0 0 0 0
• Has 2(2+2) = 16 rows 0 0 0 1 0 0 1
– 8-bit adder: 2(8+8) = 65,536 rows 0 0 1 0 0 1 0
0 0 1 1 0 1 1
– 16-bit adder: 2(16+16) = ~4 billion rows 0 1 0 0 0 0 1
0 1 0 1 0 1 0
– 32-bit adder: ... 0 1 1 0 0 1 1
0 1 1 1 1 0 0
• Big truth table with numerous 1s/0s yields big logic 1 0 0 0 0 1 0
1 0 0 1 0 1 1
– Plot shows number of transistors for N-bit adders, using 1 0 1 0 1 0 0
state-of-the-art automated combinational design tool 1 0 1 1 1 0 1
1 1 0 0 0 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 1
1 1 1 1 1 1 0
10000

8000
Q: Predict number of transistors for 16-bit

Transistors
6000
adder
A: 1000 transistors for N=5, doubles for each ors
t 4000
increase of N. So transistors = 1000*2 . Thus,
(N-5)
a
ansis
r 2000
for N=16, transistors = 1000*2(16-5) = 1000*2048 = T
2,048,000. Way too many! 0
1 2 3 4 5 6 7 8
N
Digital Design
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Frank Vahid
 Alternative Method to Design an Adder: Imitate
Adding by Hand
• Alternative adder
design: mimic 0 1 0 1 1 1

how people do A: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
a
B: + 0 1 1 0 + 0 1 1 0 + 0 1 1 0 + 0 1 1 0
addition by hand
• One column at a
time 1 0 1 1 0 1 1 0 1 0 1
– Compute sum,
add carry to next
column

Digital Design
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Frank Vahid
 Alternative Method to Design an Adder: Imitate
Adding by Hand
• Create 1 1 0
component for A: 1 1 1 1
B: + 0 1 1 0
each column
– Adds that a
column’s bits, 1 0 1 0 1
generates sum
1 1 0
and carry bits
A: 1 1 1 1

+ B: 0 1 1 0

b a ci b a ci b a ci b a
co s co s co s co s
1
0 1 0 1 SUM

Digital Design
Full-adders Half-adder
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Frank Vahid
 Half-Adder
1 1 0
• Half-adder: Adds 2 bits, generates sum and carry
• Design using combinational design process from Ch A: 1 1 1 1
2
+ B: 0 1 1 0

b a ci b a ci b a ci b a
Inputs Outputs
co s co s co s co s
a b co s 1
0 0 0 0 0 1 0 1 SUM
Step 1: Capture the function 0 1 0 1
1 0 0 1
1 1 1 0

Step 2: Convert to equations

co = ab
s = a’b + ab’ (same as s = a xor b) a b

a b

Step 3: Create the circuit Half-adder

co s
Digital Design
Copyright © 2006 co s 27
Frank Vahid
 Full-Adder
1 1 0
• Full-adder: Adds 3 bits, generates sum and carry
• Design using combinational design process from Ch A: 1 1 1 1
2
+ B: 0 1 1 0

b a ci b a ci b a ci b a
co s co s co s co s
1
0 1 0 1 SUM
Step 1: Capture the function
Step 2: Convert to Step 3: Create the circuit
Inputs Outputs a b ci
a b ci co s coequations
= a’bc + ab’c + abc’ + abc
0 0 0 0 0 co = a’bc +abc +ab’c +abc +abc’ +abc
0 0 1 0 1 co = (a’+a)bc + (b’+b)ac + (c’+c)ab
0 1 0 0 1 co = bc + ac + ab
0 1 1 1 0
1 0 0 0 1 s = a’b’c + a’bc’ + ab’c’ + abc
1 0 1 1 0 s = a’(b’c + bc’) + a(b’c’ + bc)
1 1 0 1 0 s = a’(b xor c)’ + a(b xor c)
1 1 1 1 1
Full
s = a xor b xor c adder
Digital Design co s
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Frank Vahid
 Carry-Ripple Adder
• Using half-adder and full-adders, we can build adder that adds like we would by hand
• Called a carry-ripple adder
– 4-bit adder shown: Adds two 4-bit numbers, generates 5-bit output
• 5-bit output can be considered 4-bit “sum” plus 1-bit “carry out”
– Can easily build any size adder

a3 b3 a2 b2 a1 b1 a0 b0

a b ci a b ci a b ci a b
a3 a2 a1 a0 b3 b2 b1 b0
FA FA FA HA
4-bit adder
co s co s co s co s
co s3 s2 s1 s0

co s3 s2 s1 s0
(a)
(b)

Digital Design
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Frank Vahid
 Carry-Ripple Adder
• Using full-adder instead of half-adder for first bit, we can
include a “carry in” bit in the addition
– Will be useful later when we connect smaller adders to form bigger
adders

a3 b3 a2 b2 a1 b1 a0 b0 ci

a b ci a b ci a b ci a b ci a3 a2 a1 a0 b3 b2 b1 b0
FA FA FA FA 4-bit adder ci
co s co s co s co s co s3 s2 s1 s0

co s3 s2 s1 s0
(a) (b)

Digital Design
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Frank Vahid
 Carry-Ripple Adder’s Behavior
0 0 0 0 0 0 0 0 0 0 0
0

a b ci a b ci a b ci a b ci
FA FA FA FA Assume all inputs initially 0
co s co s co s co s
0 0 0
0 0 0 0 0

0 0 0 1 0 0 1 0 0 1 1 0111+0001
0
(answer should be 01000)
a b ci a b ci a b ci a b ci
a
FA FA FA FA
co s co s co s co s
0 0 10
co2 co1 co0
0 0 1 1 0 Output a fter 2 ns (1 FA delay)

Digital Design Wrong answer -- something wrong? No -- just need more time
Copyright © 2006 for carry to ripple through the chain of full adders. 31
Frank Vahid
 Carry-Ripple Adder’s Behavior
0 0 0 1 0 0 1 0 1 1 1
0 0111+0001
(answer should be 01000)
a b ci a b ci a b ci a b ci
FA FA FA FA
co s co s co s co s
0 1 1
co1 Outputs after 4ns (2 FA delays)
0 0 1 0 0
(b)
0 0 0 1 0 10 1 0 1 1 1
0

a b ci a b ci a b ci a b ci
FA FA FA FA
co s co s co s co s
1 1 1 a
co2 Outputs after 6ns (3 FA delays)
0 0 0 0 0
(c)
0 0 01 1 0 1 1 0 1 1 1
0

a b ci a b ci a b ci a b ci
FA FA FA FA
co s co s co s co s
1 1 1
0 1 0 0 0 Output after 8ns (4 FA delays)
Digital Design (d)
Copyright © 2006 Correct answer appears after 4 FA delays 32
Frank Vahid
 Cascading Adders

a7 a6 a5 a4 b7b6b5 b4 a3 a2 a1 a0 b3b2 b1b0

a3 a2 a1 a0 b3 b2b1 b0 a3 a2 a1 a0 b3 b2 b1b0 a7.. a0 b7.. b0

4-bit adder ci 4-bit adder ci 8-bit adder ci

co s3 s2 s1 s0 co s3 s2 s1 s0 co s7.. s0

co s7 s6 s5 s4 s3 s2 s1 s0
(a) (b)

Digital Design
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Frank Vahid
 Adder Example: DIP-Switch-Based Adding Calculator
• Goal: Create calculator that adds two 8-bit binary numbers, specified using DIP switches
– DIP switch: Dual-inline package switch, move each switch up or down
– Solution: Use 8-bit adder

DIP switches

1
0

a7..a0 b7..b0
a
8-bit carry-ripple adder ci 0

co s7..s0

CALC

LEDs
Digital Design
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Frank Vahid
 Adder Example: DIP-Switch-Based Adding Calculator
• To prevent spurious values from appearing at output, can place register at output
– Actually, the light flickers from spurious values would be too fast for humans to detect -- but the principle of registering
outputs to avoid spurious values being read by external devices (which normally aren’t humans) applies here.

DIP switches

1
0

a7..a0 b7..b0

8-bit adder ci 0

co s7..s0

e
ld
8-bit register
clk
CALC
Digital Design
Copyright © 2006 LEDs 35
Frank Vahid
 Adder Example: Compensating Weight Scale
• Weight scale with compensation amount of 0-7
– To compensate for inaccurate sensor due to physical wear
– Use 8-bit adder
0
weight 7 1
sensor 6 2
5 3
4
01000010 000
0 0 0 0 0 010

a7..a0 b7..b0
a
8-bit adder ci 0

co s7..s0

1 ld
clk
01000010
01000100
display register Weight
Adjuster

Digital Design
Copyright © 2006 to display 36
Frank Vahid
 4.4

Shifters
• Shifting (e.g., left shifting 0011 yields 0110) useful for:
– Manipulating bits
– Converting serial data to parallel (remember earlier above-mirror display example with shift registers)
– Shift left once is same as multiplying by 2 (0011 (3) becomes 0110 (6))
• Why? Essentially appending a 0 -- Note that multiplying decimal number by 10 accomplished just be appending 0, i.e., by shifting left (55 becomes 550)
– Shift right once same as dividing by 2

i3 i2 i1 i0

i3 i2 i1 i0 inR
i3 i2 i1 i0 inL

in 201 201 201 201

shL s0
01 01 01 01 shR s1
in
sh
a

<<1 q3 q2 q1 q0
q3 q2 q1 q0
Symbol Left shifter q3 q2 q1 q0
Shifter with left
shift, right shift,
Shifter with left and no shift
Digital Design
Copyright © 2006 shift or no shift 37
Frank Vahid(a)
 Shifter Example: Approximate Celsius to Fahrenheit
Converter
• Convert 8-bit Celsius input to 8-bit Fahrenheit output
– F = C * 9/5 + 32
– Approximate: F = C*2 + 32
– Use left shift: F = left_shift(C) + 32

C
00001100 (12) 8 *2

<<1 0 (shift in 0)
a
00100000 (32)
00011000 (24) 8
8
8-bit adder
8
00111000 (56)
F

Digital Design
Copyright © 2006 38
Frank Vahid
 Shifter Example: Temperature Averager
• Four registers storing a
0000111 (7) 001000 (8) 001100 (12) 001111 (15)
history of temperatures T
Ra Rb Rc Rd
• Want to output the clk
average of those ld
ld

temperatures + +

• Add, then divide by four +

– Same as shift right by 2 shift in 0 0101010 (42) divide by 4
– Use three adders, and right 0 >>2
shift by two 0001010 (10)
a
Ravg
ld

Tavg

Digital Design
Copyright © 2006 39
Frank Vahid
 Barrel Shifter i3 i2 i1 i0
in
• A shifter that can shift by any amount 01 01 01 01
sh
– 4-bit barrel left shift can shift left by 0,
1, 2, or 3 positions
– 8-bit barrel left shifter can shift left by q3 q2 q1 q0
0, 1, 2, 3, 4, 5, 6, or 7 positions Shift by 1 shifter uses 2x1 muxes. 8x1
• (Shifting an 8-bit number by 8 positions mux solution for 8-bit barrel shifter: too
is pointless -- you just lose all the bits) many wires.
• Could design using 8x1 muxes and Q: xyz=??? to
I
shift by 5? 8 00000110
lots of wires 1
– Too many wires x sh <<4 in 0
• More elegant design
8 01100000 (by 4)
– Chain three shifters: 4, 2, and 1 0 a

– Can achieve any shift of 0..7 by y sh <<2 in 0

enabling the correct combination of
those three shifters, i.e., shifts should 8 01100000
1
sum to desired amount
z sh <<1 in 0
Digital Design Net result: shift by 5:8 11000000 (by 1)
Copyright © 2006 Q 40
Frank Vahid
 4.5

Comparators
• N-bit equality comparator: Outputs 1 if two N-bit numbers are equal
– 4-bit equality comparator with inputs A and B
• a3 must equal b3, a2 = b2, a1 = b1, a0 = b0
– Two bits are equal if both 1, or both 0
– eq = (a3b3 + a3’b3’) * (a2b2 + a2’b2’) * (a1b1 + a1’b1’) * (a0b0 + a0’b0’)
• Recall that XNOR outputs 1 if its two input bits are the same
– eq = (a3 xnor b3) * (a2 xnor b2) * (a1 xnor b1) * (a0 xnor b0)

a3 b3 a2 b2 a1 b1 a0 b0
0110 = 0111 ? 0 0 1 1 1 1 0 1

a3 a2 a1 a0 b3 b2 b1 b0 a
1 1 1 0
4-bit equality comparator
eq

(b)
0 eq
(a)
Digital Design
Copyright © 2006 41
Frank Vahid
 Magnitude Comparator
• N-bit magnitude comparator:
A=1011 B=1001
Indicates whether A>B, A=B, or
A<B, for its two N-bit inputs A and 1011 1001 Equal
B 1011 1001 Equal
– How design? Consider how compare
1011 1001 Unequal
by hand. First compare a3 and b3. If
equal, compare a2 and b2. And so on. So A > B
Stop if comparison not equal --
whichever’s bit is 1 is greater. If never
see unequal bit pair, A=B. a

Digital Design
Copyright © 2006 42
Frank Vahid
 Magnitude Comparator
• By-hand example leads to idea for design
– Start at left, compare each bit pair, pass results to the right
– Each bit pair called a stage
– Each stage has 3 inputs indicating results of higher stage, passes results to
lower stage
a3 b3 a2 b2 a1 b1 a0 b0

a b a b a b a b
Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt AgtB
Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB
Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB

Stage 3 Stage 2 Stage 1 Stage 0

(a)

0 Igt a3 a2 a1 a0 b3 b2 b1 b0
AgtB
1 Ieq 4-bit magnitude comparator AeqB
Digital Design 0 Ilt AltB
Copyright © 2006 43
Frank Vahid
(b)
 Magnitude Comparator
a3 b3 a2 b2 a1 b1 a0 b0

a b a b a b a b
Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt AgtB
Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB
Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB

Stage 3 Stage 2 Stage 1 Stage 0

• Each stage:
– out_gt = in_gt + (in_eq * a * b’)
• A>B (so far) if already determined in higher stage, or if higher stages equal but in
this stage a=1 and b=0
– out_lt = in_lt + (in_eq * a’ * b)
• A<B (so far) if already determined in higher stage, or if higher stages equal but in
this stage a=0 and b=1
– out_eq = in_eq * (a XNOR b)
• A=B (so far) if already determined in higher stage and in this stage a=b too
– Simple circuit inside each stage, just a few gates (not shown)
Digital Design
Copyright © 2006 44
Frank Vahid
 Magnitude Comparator
• How does it 1011 = 1001 ?
1 = 1
work? a3 b3
0
a2
0
b2
1
a1
0
b1
1
a0
1
b0

a b a b a b a b
0 0
Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt AgtB
Ieq=1 causes this 1 1
Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB
0 0
stage to compare Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB

Stage3 Stage2 Stage1 Stage0

(a)
a

1 1 0 = 0 1 0 1 1
a3 b3 a2 b2 a1 b1 a0 b0

a b a b a b a b
0 0
Igt in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt AgtB
1 1
Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB
0 0
Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB

Stage3 Stage2 Stage1 Stage0

Digital Design (b)
Copyright © 2006 45
Frank Vahid
 Magnitude Comparator
1 1 0 0 1 > 0 1 1
1011 = 1001 ? a3 b3 a2 b2 a1 b1 a0 b0 • Final answer
appears on the
a b a b a b a b right
0 1
AgtB•
Igt
1
in_gt out_gt in_gt out_gt in_gt out_gt
0
in_gt out_gt
Takes time for
Ieq in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq AeqB
0 0 answer to
Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB
“ripple” from left
Stage3 Stage2 Stage1 Stage0 to right
(c) • Thus called
a 1 1 0 0 1 0 1 1 “carry-ripple
a3 b3 a2 b2 a1 b1 a0 b0 style” after the
carry-ripple
a b a b a b a b adder
0 1
Igt
1
in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt
0
AgtB – Even though
Ieq
0
in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq
0
AeqB there’s no
Ilt in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt AltB “carry”
involved
Stage3 Stage2 Stage1 Stage0
Digital Design (d)
Copyright © 2006 46
Frank Vahid
 Magnitude Comparator Example:
Minimum of Two Numbers
• Design a combinational component that computes the
minimum of two 8-bit numbers
– Solution: Use 8-bit magnitude comparator and 8-bit 2x1 mux
• If A<B, pass A through mux. Else, pass B.

11000000 01111111
MIN A B 8 8

8 8 8 8
a A B

0 Igt
A B
AgtB
1 s
I1 I0 Min
C
1 Ieq 8-bit magnitude comparator AeqB 0 8-bit
0 Ilt AltB 2x1 mux 8
0
8 (b)
C
(a)
01111111

Digital Design
Copyright © 2006 47
Frank Vahid
 4.6

Counters
• N-bit up-counter: N-bit register
01
that can increment (add 1) to its cnt 4-bit up-counter
a

own value on each clock cycle tc C

4
– 0000, 0001, 0010, 0011, ...., 1110,
010 0000
0101
0100
0011
0010
0001
0000
1111
1110
0001
...
1111, 0000
– Note how count “rolls over” from 1111
to 0000
4-bit up-counter
• Terminal (last) count, tc, equals1
during value just before rollover cnt
ld
4-bit register
• Internal design
a
– Register, incrementer, and N-input 4 4
AND gate to detect terminal count 4 +1
4
tc C

Digital Design
Copyright © 2006 48
Frank Vahid
 Incrementer
• Counter design used incrementer
• Incrementer design
– Could use carry-ripple adder with B input set to 00...001
• But when adding 00...001 to another number, the leading 0’s
obviously don’t need to be considered -- so just two bits being
added per column
– Use half-adders (adds two bits) rather than full-adders (adds
three bits)
a3 a2 a1 a0 1
carries: 011
a
b a b a b a b a3 a2 a1 a0
0011
unused HA HA HA HA +1
+ 1
co s co s co s co s nt co s3 s2 s1 s0
0 010 0
co s3 s2 s1 s0
r
I (b)
Digital Design (a)
Copyright © 2006 49
Frank Vahid
 Incrementer
Inputs Outputs
• Can build faster incrementer a3 a2 a1 a0 c0 s3 s2 s1 s0
using combinational logic 0 0 0 0 0 0 0 0 1
0 0 0 1 0 0 0 1 0
design process 0 0 1 0 0 0 0 1 1
– Capture truth table 0 0 1 1 0 0 1 0 0
0 1 0 0 0 0 1 0 1
– Derive equation for each output 0 1 0 1 0 0 1 1 0
• c0 = a3a2a1a0 0 1 1 0 0 0 1 1 1
0 1 1 1 0 1 0 0 0
• ...
1 0 0 0 0 1 0 0 1
• s0 = a0’ 1 0 0 1 0 1 0 1 0
1 0 1 0 0 1 0 1 1
– Results in small and fast circuit
1 0 1 1 0 1 1 0 0
– Note: works for small N -- larger 1 1 0 0 0 1 1 0 1
N leads to exponential growth, 1 1 0 1 0 1 1 1 0
1 1 1 0 0 1 1 1 1
like for N-bit adder 1 1 1 1 1 0 0 0 0

Digital Design
Copyright © 2006 50
Frank Vahid
 Counter Example: Mode in Above-Mirror Display
• Recall above-mirror display example from Chapter 2
– Assumed component that incremented xy input each time button
pressed: 00, 01, 10, 11, 00, 01, 10, 11, 00, ...
– Can use 2-bit up-counter
• Assumes mode=1 for just one clock cycle during each button press
– Recall “Button press synchronizer” example from Chapter 3

mode
cnt 2-bit up counter
tc c1c0
clk

x y

Digital Design
Copyright © 2006 51
Frank Vahid
Counter Example: 1 Hz Pulse Generator Using 256 Hz
Oscillator
• Suppose have 256 Hz
oscillator, but want 1 Hz
pulse
– 1 Hz is 1 pulse per second
-- useful for keeping time
1
– Design using 8-bit up- cnt 8-bit up-counter
counter, use tc output as osc
tc C
pulse (256 Hz) 8
• Counts from 0 to 255 (256 p (unused)
counts), so pulses tc every (1 Hz)
256 cycles

Digital Design
Copyright © 2006 52
Frank Vahid
 Down-Counter
• 4-bit down-counter
4-bit down-counter
– 1111, 1110, 1101, 1100,
…, 0011, 0010, 0001, cnt
0000, 1111, … ld
4-bit register
– Terminal count is 0000
• Use NOR gate to detect
– Need decrementer (-1) – 4 4
design like designed 4 –1
incrementer
tc C 4

Digital Design
Copyright © 2006 53
Frank Vahid
 Up/Down-Counter
• Can count either up 4-bit up/down counter
or down
– Includes both dir
1 4-bit 2 x 1 0
incrementer and 4
decrementer
clr clr
– Use dir input to cnt ld 4-bit register
select, using 2x1:
dir=0 means up
– Likewise, dir selects 4 4 4 4
appropriate terminal –1 +1
4
count value
4 4
1 2x 1 0
tc C

Digital Design
Copyright © 2006 54
Frank Vahid
 Counter Example: Light Sequencer
• Illuminate 8 lights from right
to left, one at a time, one per 1 cnt 3-bit u p -cou nter
second clk tc c2 c1 c0
• Use 3-bit up-counter to (1 Hz)
0 10 010
counter from 0 to 7 unused

• Use 3x8 decoder to 3 x 8 d cd i2 i1 i0

illuminate appropriate light d7 d6 d5 d4 d3 d2 d1 d0
• Note: Used 3-bit counter a

with 3x8 decoder lights

– NOT an 8-bit counter – why
not?

Digital Design
Copyright © 2006 55
Frank Vahid
 Counter with Parallel Load
• Up-counter that can be
L 4
loaded with external
ld
value 1 4-bit 2 x 1 0
– Designed using 2x1 mux 4
– ld input selects cnt ld
incremented value or 4-bit register
external value
– Load the internal register
4 4
when loading external +1
4
value or when counting
tc C

Digital Design
Copyright © 2006 56
Frank Vahid
 Counter with Parallel Load
• Useful to create pulses at 1000
specific multiples of clock 4

– Not just at N-bit counter’s natural

wrap-around of 2N ld L
• Example: Pulse every 9 clock 1
cnt 4-bit down-counter
cycles
– Use 4-bit down-counter with clk
tc C
parallel load 4
– Set parallel load input to 8 (1000)
– Use terminal count to reload
• When count reaches 0, next cycle
loads 8.
– Why load 8 and not 9? Because 0
is included in count sequence:
• 8, 7, 6, 5, 4, 3, 2, 1, 0  9 counts
Digital Design
Copyright © 2006 57
Frank Vahid
 Counter Example:
New Year’s Eve Countdown Display
• Chapter 2 example previously used microprocessor to counter from 59
down to 0 in binary
• Can use 8-bit (or 7- or 6-bit) down-counter instead, initially loaded with
59
Happy
0 New
d0
59 8 L c0 i0 Year
d1
c1 i1 1
c2 i2 d2 2
ld c3 i3 d3 3
reset c4 i4
c5 i5 d58
c6 d59
cnt
c7
countdown d60
d61 58
clk 8-bit d62 59 fireworks
(1 Hz) down- tc 6x64
counter dcd d63
Digital Design
Copyright © 2006 58
Frank Vahid
 Counter Example:
1 Hz Pulse Generator from 60 Hz Clock
• U.S. electricity standard
uses 60 Hz signal clr
– Device may convert that to 1 cnt 6-bit up counter
1 Hz signal to count osc tc C
seconds (60 Hz)
• Use 6-bit up-counter p
– Can count from 0 to 63
– Create simple logic to
detect 59 (for 60 counts)
• Use to clear the counter
(1 Hz)
back to 0 (or to load 0)

Digital Design
Copyright © 2006 59
Frank Vahid
 Timer
• A type of counter used to measure time
– If we know the counter’s clock frequency and the count, we know the time that’s been counted
• Example: Compute car’s speed using two sensors
– First sensor (a) clears and starts timer
– Second sensor (b) stops timer
– Assuming clock of 1kHz, timer output represents time to travel between sensors. Knowing the
distance, we can compute speed

Digital Design
Copyright © 2006 60
Frank Vahid
 4.7

Multiplier – Array Style

• Can build multiplier that mimics multiplication by hand
– Notice that multiplying multiplicand by 1 is same as ANDing with 1

Digital Design
Copyright © 2006 61
Frank Vahid
 Multiplier – Array Style
• Generalized representation of multiplication by hand

Digital Design
Copyright © 2006 62
Frank Vahid
 Multiplier – Array Style
• Multiplier design – array of
AND gates
a3 a2 a1 a0

b0

pp1
b1

pp2
0 0

b2
+ (5-bit)

pp3
00
A B
b3
+ (6-bit) *
P

pp4
0 00

+ (7-bit) Block symbol

Digital Design
Copyright © 2006 p7..p0 63
Frank Vahid
 4.8

Subtractor
• Can build subtractor as we built carry-ripple adder
– Mimic subtraction by hand
– Compute borrows from columns on left
• Use full-subtractor component:
– wi is borrow by column on right, wo borrow from column on left
1st column 2nd column 3rd column 4th column
0 0 1 10 0 1 0
1 0 1 10 1 10 1 0 1 10 1 0 1 0 1 0
- 0 1 1 1 - 0 1 1 1 - 0 1 1 1 - 0 1 1 1
1 1 1 0 1 1 0 0 1 1

a3 b3 a2 b2 a1 b1 a0 b0 wi

a b wi a b wi a b wi a b wi a3 a2 a1 a0 b3 b2 b1 b0
FS FS FS FS 4-bit subtractor wi a

wo s wo s wo s wo s wo s3 s2 s1 s0

wo s3 s2 s1 s0
(b) (c)
Digital Design
Copyright © 2006 64
Frank Vahid
 Subtractor Example: DIP-Switch Based
Adding/Subtracting Calculator
• Extend earlier DIP switches
calculator example 1
– Switch f indicates 0

whether want to
8 8 8 8
add (f=0) or 0 0
subtract (f=1) A B ci A B wi
8-bit adder 8-bit subtractor
– Use subtractor and co S wo S
2x1 mux
1 f 8 8
0 2x 1 1
0
8
e
ld
8-bit register
clk
CALC
8

LEDs
Digital Design
Copyright © 2006 65
Frank Vahid
 Subtractor Example:
Color Space Converter – RGB to CMYK
• Color
– Often represented as weights
of three colors: red, green, and
blue (RGB)
• Perhaps 8 bits each, so
specific color is 24 bits
– White: R=11111111,
G=11111111, B=11111111
– Black: R=00000000,
G=00000000, B=00000000
– Other colors: values in
between, e.g., R=00111111,
G=00000000, B=00001111 • Printers use opposite color scheme
would be a reddish purple – Because inks absorb light
– Good for computer monitors, – Use complementary colors of RGB:
which mix red, green, and blue Cyan (absorbs red), reflects green
lights to form all colors and blue, Magenta (absorbs green),
and Yellow (absorbs blue)
Digital Design
Copyright © 2006 66
Frank Vahid
 Subtractor Example:
Color Space Converter – RGB to CMYK

R G B
• Printers must quickly convert 255 255 255
8 8 8
RGB to CMY 8 8 8

– C=255-R, M=255-G, Y=255-B

– Use subtractors as shown o CMY - - -
t
GB
R 8 8 8
C M Y

Digital Design
Copyright © 2006 67
Frank Vahid
 Subtractor Example:
Color Space Converter – RGB to CMYK

• Try to save colored inks

– Expensive
– Imperfect – mixing C, M, Y doesn’t
yield good-looking black
• Solution: Factor out the black or
gray from the color, print that part
using black ink
– e.g., CMY of (250,200,200)=
(200,200,200) + (50,0,0).
• (200,200,200) is a dark gray – use
black ink

Digital Design
Copyright © 2006 68
Frank Vahid
 Subtractor Example:
Color Space Converter – RGB to CMYK
• Call black part K
R G B
8 8 8
– (200,200,200): K=200 K
– (Letter “B” already used for blue)
R G B
Y
• Compute minimum of C, R GB t o CMY o CM
t
M, Y values C M Y
GB
R
– Use MIN component 8 8 8 8
designed earlier, using C M Y
comparator and mux, to MIN
compute K 8
– Output resulting K value,
and subtract K value from MIN
C, M, and Y values 8
K
– Ex: Input of (250,200,200)
yields output of
- - -
(50,0,0,200)
8 8 8 8
C2 M2 Y2 K
Digital Design
Copyright © 2006 69
Frank Vahid
 Representing Negative Numbers: Two’s
Complement
• Negative numbers common
– How represent in binary?
• Signed-magnitude
– Use leftmost bit for sign bit
• So -5 would be:
1101 using four bits
10000101 using eight bits
• Better way: Two’s complement
– Big advantage: Allows us to perform subtraction using addition
– Thus, only need adder component, no need for separate
subtractor component!

Digital Design
Copyright © 2006 70
Frank Vahid
 Ten’s Complement
1 9

2 8
• Before introducing two’s complement, let’s
3 7
consider ten’s complement
4 6
– But, be aware that computers DO NOT USE TEN’S
5 5
COMPLEMENT. Introduced for intuition only.
6 4
– Complements for each base ten number shown to
right – Complement is the number that when added 7 3
results in 10 8 2

9 1

Digital Design
Copyright © 2006 71
Frank Vahid
 Ten’s Complement
• Nice feature of ten’s complement
– Instead of subtracting a number, adding its complement results in answer exactly 10 too
much
– So just drop the 1 – results in subtracting using addition only

complements
1 9 10
2 8 4 6

3 7 7
4 6
0 10 20
5 5
3
-Ð4 +6
13
6 4
13
7 3
3
8 2
-
7Ð4=3 7+6=13 3
9 1 Adding the complement results in an answer
exactly 10 too much – dropping the tens column gives
0 10 the right answer.
Digital Design
Copyright © 2006 72
Frank Vahid
 Two’s Complement is Easy to Compute:
Just Invert Bits and Add 1
• Hold on!
– Sure, adding the ten’s complement achieves subtraction using addition
only
– But don’t we have to perform subtraction to have determined the
complement in the first place? e.g., we only know that the complement of 4
is 6 by subtracting 10-4=6 in the first place.
• True – but in binary, it turns out that the two’s complement can be
computed easily
– Two’s complement of 011 is 101, because 011 + 101 is 1000
– Could compute complement of 011 as 1000 – 011 = 101
– Easier method: Just invert all the bits, and add 1
– The complement of 011 is 100+1 = 101 -- it works!

Q: What is the two’s complement of 0101? A: 1010+1=1011 a

(check: 0101+1011=10000)
Q: What is the two’s complement of 0011? A: 1100+1=1101
Digital Design
Copyright © 2006 73
Frank Vahid
Two’s Complement Subtractor Built with an Adder
• Using two’s complement
A B
A – B = A + (-B)
= A + (two’s complement of B) N-bit
= A + invert_bits(B) + 1
• So build subtractor using A B 1
Adder cin
adder by inverting B’s bits,
and setting carry in to 1
S

Digital Design
Copyright © 2006 74
Frank Vahid
 Adder/Subtractor

• Adder/subtractor: control
input determines whether
add or subtract
– Can use 2x1 mux – sub input
passes either B or inverted B
– Alternatively, can use XOR
gates – if sub input is 0, B’s
bits pass through; if sub input
is 1, XORs invert B’s bits

Digital Design
Copyright © 2006 75
Frank Vahid
 Adder/Subtractor Example: Calculator
• Previous calculator DIP switches

used separate 1
0
adder and
8 8
subtractor
1 f A B
• Improve by using 0
sub 8-bit adder/subtractor
S
adder/subtractor, 8
e
and two’s ld
8-bit register
clk
complement 8
CALC

numbers 1
DIP switches

0
LEDs
8 8 8 8
A B ci 0 A B wi 0
8-bit adder 8-bit subtractor
co S wo S

1 f 8 8
0 2x1 1
0
8
e ld 8-bit register
clk CALC
8
Digital Design
Copyright © 2006 LEDs 76
Frank Vahid
 Overflow
• Sometimes result can’t be represented with given number
of bits
– Either too large magnitude of positive or negative
– e.g., 4-bit two’s complement addition of 0111+0001 (7+1=8). But 4-
bit two’s complement can’t represent number >7
• 0111+0001 = 1000 WRONG answer, 1000 in two’s complement is -8,
not +8
– Adder/subtractor should indicate when overflow has occurred, so
result can be discarded

Digital Design
Copyright © 2006 77
Frank Vahid
 Detecting Overflow: Method 1
• Assuming 4-bit two’s complement numbers, can detect overflow by detecting when the two numbers’ sign bits are the same but are different from the result’s sign bit
– If the two numbers’ sign bits are different, overflow is impossible
• Adding a positive and negative can’t exceed largest magnitude positive or negative
• Simple circuit
– overflow = a3’b3’s3 + a3b3s3’
– Include “overflow” output bit on adder/subtractor

sign bits

0 1 1 1 1 1 1 1 1 0 0 0

+0 0 0 1 +1 0 0 0 +0 1 1 1

1 0 0 0 0 1 1 1 1 1 1 1
overflow overflow no overflow
(a) (b) (c)
If the numbers’ sign bits have the same value, which
Digital Design
differs from the result’s sign bit, overflow has occurred.
Copyright © 2006 78
Frank Vahid
 Detecting Overflow: Method 2
• Even simpler method: Detect difference between carry-in to sign bit and carry-out from sign bit
• Yields simpler circuit: overflow = c3 xor c4

1 1 1 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 0 0 0

+0 0 0 1 +1 0 0 0 +0 1 1 1

0 1 0 0 0 1 0 1 1 1 0 1 1 1 1
overflow overflow no overflow
(a) (b) (c)

If the carry into the sign bit column differs from the
carry out of that column, overflow has occurred.

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 4.9

Arithmetic-Logic Unit: ALU

• ALU: Component that
can perform any of
various arithmetic (add,
subtract, increment,
etc.) and logic (AND,
OR, etc.) operations,
based on control inputs
• Motivation:
– Suppose want multi-
function calculator that
not only adds and
subtracts, but also
increments, ANDs, ORs,
XORs, etc.

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Frank Vahid
 Multifunction Calculator without an ALU
• Can build multifunction
calculator using separate
components for each 1
DIP switches

operation, and muxes 0

8 8
– But too many wires, and
A B
wasted power computing
all those operations when + Ð +1 AND OR XOR NOT
Wasted
power
8
at any time you only use 8 8
8
one of the results 8 8 8
8
1 0 A lot of wires
0 1 2 3 4 5 6 7
x
s2
y 8-bit 8  1
s1
z s0
8
e
Id
8-bit regist er
clk
CALC
8

Digital Design LEDs

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Frank Vahid
 ALU
• More efficient design uses ALU
– ALU design not just separate components multiplexed (same problem as previous
slide!),
– Instead, ALU design uses single adder, plus logic in front of adder’s A and B inputs
• Logic in front is called an arithmetic-logic extender
– Extender modifies the A and B inputs such that desired operation will appear at output
of the adder

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Frank Vahid
 Arithmetic-Logic Extender in Front of ALU

• xyz=000: Want S=A+B – just pass a to ia, b to ib, and set cin=0
• xyz=001: Want S=A-B – pass a to ia, b’ to ib, and set cin=1
• xyz=010: Want S=A+1 – pass a to ia, set ib=0, and set cin=1
• xyz=011: Want S=A – pass a to ia, set ib=0, and set cin=0
• xyz=1000: Want S=A AND B – set ia=a*b, b=0, and cin=0
• others: likewise
• Based on above, create logic for ia(x,y,z,a,b) and ib(x,y,z,a,b) for each abext, and
create logic for cin(x,y,z), to complete design of the AL-extender component
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Frank Vahid
 ALU Example: Multifunction Calculator
DIP swi tches
1
0
8 8

A B

+ Ð +1 Was t ed
AND OR XOR NOT p o w er
8
8 8
8
8 8 8
DIP switches
8
1 0 0 1 2 3 4 5 6 7 A lot of wi re s.
x
y
z
s2
s1
s0
8-bit 8  1
1 1
8

clk
e
Id
8-bit re g ist er 0 0
CALC
8

LEDs
8 8
A B
A B
• Design using ALU is x
y x
ALU
y
elegant and efficient z z S
8
– No mass of wires
e
ld
– No big waste of power clk
8-bit register

8 CALC

LEDs

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Frank Vahid
 4.10

Register Files
• MxN register file
component provides 32
er C C
efficient access to M N- er 8 a

bit-wide registers s t
ompu t d0 d0 loadload
reg0
reg0 T huge mux
32 o the ab
– If we have many om the ompu
c
car 4 162  4 i0 i0
ormidispl
o mi
theT
om thecr al
rtcar's
too much 8
T r
8-bitor disp
32-bit
registers but only need al n 16 41× 1 r
fanout
r
tF
r ne ce 4 a0
d1 load reg1 A x
access one or two at a F i0
o
c i1
o a
y ve
time, a register file is a ve- D D
i1
i3-i0 8
a1
load reg2 d dy
more efficient d2 I 32 8
– Ex: Above-mirror display 8
i2
congestion
(earlier example), but this d3 load reg3 M
d15
e load reg15
time having 16 32-bit e
registers load i15i3 s1 s0
load 32 8
s3-s0
• Too many wires, and x y
big mux is too slow

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 Register File
• Instead, want component that has one data input and one data output,
and allows us to specify which internal register to write and which to read

32 32
W_data R_data a

4 4
W_addr R_addr

W_en R_en
16×32
register file

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Frank Vahid
 Register File Timing Diagram
• Can write one clk
cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6

register and read 1 2 3 4 5 6

one register each W_data 9 22 X X 177 555

clock cycle W_addr 3 1 X X 2 3

– May be same
W_en
register
R_data Z Z Z 9 Z 22 9 555

R_addr X X 3 X 1 3

R_en

0: ? 0: ? 0: ? 0: ? 0: ? 0: ? 0: ?
32 32
W_data R_data
1: ? 1: ? 1: 22 1: 22 1: 22 1: 22 1: 22
2: ? 2: ? 2: ? 2: ? 2: ? 2: 177 2: 177
2 2
W_addr R_addr 3: ? 3: 9 3: 9 3: 9 3: 9 3: 9 3: 555

W_en R_en
4x32
register file

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 Register-File Example: Above-Mirror Display
• 16 32-bit registers that
can be written by car’s 32
OLD design
C
computer, and d0 load reg0
a

huge mux
displayed 32
i0
4 16
– Use 16x32 register file

mirror display
To the above-
32too much 32

central computer
C D

From the car′s

W_data
fanout R_data 32-bit
– Simple, elegant design 4 WA 4
16x 1
4
W_addr R_addr
• Register file hides i3-i0
load
W_en R_en d D
complexity internally 16× 32
register file
1 32
RA
– And because only one congestion
register needs to be e
d15 load reg15

written and/or read at a load

i15
32 s3-s0
time, internal design is
simple
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Frank Vahid
 Chapter Summary
• Need datapath components to store and operate on multibit data
– Also known as register-transfer-level (RTL) components
• Components introduced
– Registers
– Shifters
– Adders
– Comparators
– Counters
– Multipliers
– Subtractors
– Arithmetic-Logic Units
– Register Files
• Next, we’ll combine knowledge of combinational logic design,
sequential logic design, and datapath components, to build digital
circuits that can perform general and powerful computations

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