BASIC CIRCUIT CONCEPTS

SHEET RESISTANCE
• Consider a uniform slab of conducting material of resistivity
p, of width W, thickness t, and length between faces L. The
arrangement is shown in Figure
• consider the resistance RAB between two opposite faces.

where
A = cross-section area

Now, consider the case in which L = W, that is, a square of

resistive material, then
where
RS = ohm per square or sheet resistance

Note that Rs is completely independent of the area of the

square

for example, a 1 µm per side square slab of material has

exactly the same resistance as a 1 Cm per side square slab of
the same material if the thickness is the same
• For the MOS processes considered here, typical values of
sheet resistance are given
SHEET RESISTANCE CONCEPT APPLIED TO MOS
TRANSISTORS AND INVERTERS

Consider the transistor structures of Figure 4.2 and note

that the diagrams distinguish the actual diffusion (active)
regions from the channel regions
L= 2ƛ
W= 2ƛ
=

RS=Z*RSn=1*Ω=10KΩ

The simple n-type pass transistor of Figure 4.2(a) has a channel

length L = 2ƛ and a channel width W =2ƛ The channel is,
therefore, square and channel resistance
 The transistor structure of
·Figure 4.2(b) has a channel length L = 8 ƛ.
and width W = 2ƛ . Therefore,
=

Thus, channel resistance

R=Z*RSn=4*Ω=40KΩ

Another way of looking at this is to recognize that this channel

can be regarded as four 2ƛ x 2ƛ. squares in series . thus giving a
resistance of 4RS • This particular way of approaching the
calculation of resistance is often useful, particularly when dealing
with shapes which are not simple rectangles.
Figure 4.3 takes these considerations one step further and shows
how the pull-up to pull-down ratio of an inverter is determined. In
the nMOS case a simple 4: I Zp.u. :Zp.d. ratio obviously applies.
Note, for example, that a 4: I ratio would also be achieved if the
upper channel _(p.u.) length L = 4., and width W = 2. with lower
channel (p.d.) length L = 2., and width W = 4.. For the CMOS case,
note the different value of R5 which applies for the pull-up
transistor. PULL UP TRANSISTOR
=
L=8ƛ
RS=Z*RSn=4*Ω=40KΩ
W = 2ƛ PULL DOWN TRANSISTOR
=
L=2ƛ RS=Z*RSn=1*Ω=10KΩ
W = 2ƛ
ON RESISTANCE FROM VDD TO GND=50KΩ
 PULL UP TRANSISTOR

L=2ƛ =
W=2ƛ
RS=Z*RSP=1*Ω=25KΩ
PULL DOWN TRANSISTOR
L=2ƛ
=
W=2ƛ
RS=Z*RSn=1*Ω=10KΩ

A ratio rule does not apply and there is

no static resistance from VDD to Vss·
 AREA CAPACITANCES OF LAYERS
From the diagrams we have used to illustrate the structure of
transistors, and from discussions of the fabrication processes, it
will be apparent that conducting layers are separated from the
substrate and each other by insulating (dielectric) layers, and thus
parallel plate capacitive effects must be present and must be
allowed for.
For any layer, knowing the dielectric (silicon dioxide) thickness,
we can calculate area capacitance as follows

where
D = thickness of silicon dioxide
A = area of plates
(and it is assumed that ϵ0, A, and D are in compatible units, for
example, ϵ0 in farads/Cm, A in cm2, D in Cm).

ϵins = relative permittivity of Si02 = 4.0

ϵ0 = 8.85 x F/cm (permittivity of free space)
A normal approach is to give layer area capacitances in pF/µ
(where µ m= micron = meter = Cm). The appropriate figure may
be calculated as follows:

(D in Cm, ϵ0 in farads/Cm)
Typical values of area capacitance are set out in Table 4.2 for 5 µm
technology and for Orbit 2 µm and 1.2 µm technologies.
 STANDARD UNIT OF CAPACITANCE
a standard unit of capacitance that can be given a value appropriate
to the technology but can also be used in calculations without
associating it with an absolute value. The unit is denoted and
is defined the gate-to-channel capacitance of a MOS transistor
having W = L = feature size, that is, a 'standard' or 'feature size'
square as
in Figure 4.2(a), for example, for lambda-based rules
may be evaluated for any MOS process. For example,
for 5 µm MOS circuits

Area/standard square = 5 µm x 5 µm = 25
(= area of minimum size transistor)
Capacitance value = 4 x pF/
Thus, standard value = 25 x 4 x pF/ = .01 pF
 for 2 µm MOS circuits

Area/standard square = 2 µm x 2 µm = 4

Gate capacitance value = 8 x pF/

Thus, standard value = 4 x 8 x pF/ = .0032 pF

for 1.2 µm MOS circuits

Area/standard square = 1.2 µm x 1.2 µm =1.44

Gate capacitance value = 16 x pF/

Thus, standard value = 1.44 x 16 x pF/ = .0023 pF
 SOME AREA CAPACITANCE CALCULATIONS
The ratio between the area of interest and the area of standard
(feature size square) gate (2ƛ x 2ƛ. for ƛ based rules) and multiplying
this ratio by the appropriate relative C value from Table 4.2. The
product will give the required capacitance in units.

Consider the area defined in Figure 4.4. First, we must calculate the
area relative to that of a standard gate.
 Relative-area= = 15

Now:

1. Consider the area in metal 1.

Capacitance to substrate = relative area x relative C value

= 15 X 0.07500
= 1.125

That is, the defined area in metal has a capacitance to substrate

1.125 times that of a feature size square gate area.
2. Consider the same area in polysilicon

Capacitance to substrate = 15 X 0.1

=1.5

3. Consider the same area in n-type diffusion.

Capacitance to substrate = 15 X 0.25
=3.75
Calculations of area capacitance values associated with structures
occupying more than one layer, as in Figure 4.5, are equally
straightforward

Consider the metal area (less the contact region where the metal
is connected to polysilicon and shielded from the substrate)
 RATIO= = 100 ƛ ∗3 ƛ
2 ƛ ∗ 2 ƛ = 75

Metal capacitance Cm = 75 x 0.075 = 5.625

Consider the polysilicon area (excluding the gate region)

Polysilicon area = 4 x 4+ 3. x 2 = 22

Therefore 2
22 ƛ
Polysilicon capacitance Cp = 2 ƛ ∗2 ƛ = 5.5

5.5 x 0.1 = 0.55

For the transistor,

Gate capacitance Cg = = 1
Therefore
Total capacitance = +

= 5.625 +¿ 0.55 +¿ 1
= 7.20

In all cases absolute values are readily evaluated by substitution of

the actual value for
It is not unusual to find metal paths of uniform 4 width but when
taking this approach in design it must be borne in mind that,
compared with 3 width paths, the capacitance will be increased by
one-third
For example, if the metal width is increased to 4 in Figure 4.5, the
capacitance Cm is increased to 7.50 and the capacitance of
the complete structure will increase to about 9
 THE DELAY UNIT
We have developed the concept of sheet resistance Rs and standard
gate capacitance unit . If we consider the case of one standard
(feature size square) gate area capacitance being charged through
one feature size square of n channel resistance

Time constant =(1Rs (n channel) x 1 ) seconds

This can be evaluated for any technology and for 5 µm technology

= x 0.01 pF = 0.1 nsec

and for 2 µm (Orbit) technology,

=2* x 0.0032 pF = 0.064 nsec

and for 1.2 µm (Orbit) technology,

=2* x 0.0023 pF = 0.046 nsec

However, in practice, circuit wiring and parasitic capacitances

must be allowed for so that the figure taken for is often
increased by a factor of two or three so that for 5 µm circuit
 = 0.2 to 0.3 nsec is a typical design figure used in assessing
likely worst case delays.

Note that thus obtained is not much different from transit

time calculated

Note that Vds varies as C8 charges from 0 volts to 63% of Vdd

in period in Figure 4.6, so that an appropriate value for Vds is
the average value = 3 volts. For 5 µm technology, then,
 This is very close to the theoretical time constant calculated
above

Since the transition point of an inverter or gate is 0.5 VDD•

which is close to 0.63 VDD• it appears to be common practice
to use transit time and time constant (as defined for the delay
unit ) interchangeably and 'stray' capacitances are usually
allowed for by doubling (or more) the theoretical values
calculated.
In view of this, is used as the fundamental time unit and all
timings in a system can be assessed in relation to
For 5 µm MOS technology = 0.3 nsec is a very safe figure to use; and,
for 2 µm Orbit MOS technology, = 0.2 nsec is an equally safe figure to
use; and,
for 1.2 µm Orbit MOS technology, = 0.1 nsec is also a safe figure.
 INVERTER DELAYS
Consider the basic 4: 1 ratio nMOS inverter. In order to achieve the
4:1 Zp.u. to Zp.d. ratio, Rp.u. will be 4 Rp.d. and if Rp.d. is
contributed by the minimum size transistor then, clearly, the
resistance value associated with Rp.u. is

Meanwhile, the Rp.d. value is 1Rs = 10 KΩ so that the delay

associated with the inverter will depend on whether it is being
turned on or off.
 However, if we consider a pair of cascaded inverters, then the
delay over the pair will be constant irrespective of the sense of
the logic level transition of the input to the first. This is clearly
seen from Figure 4.7 and, assuming = 0.3 nsec and making no
extra allowances for wiring capacitance, we have an overall
delay of + 4 = 5 . In general terms, the delay through a pair of
similar nMOS inverters is

Thus, the inverter pair delay for inverters having 4: 1 ratio is 5 .

When considering CMOS inverters, the nMOS ratio rule no
longer applies, but we must allow for the natural (RS )
asymmetry of the usually equal size pull-up p-transistors and
the n-type pull-down transistors. Figure 4.8 shows the
theoretical delay associated with a pair of minimum size (both
n-and p-transistors) lambda-based inverters. Note that the gate
capacitance(= 2 ) is double that of the comparable nMOS
inverter since the input to a CMOS inverter is connected to
both transistor gates. Note also the allowance made for the
differing channel resistances.
A More Formal Estimation of CMOS Inverter
Delay
A CMOS inverter, in general, either charges or discharges a
capacitive load and rise-time or fall-time ' can be estimated
from the following simple analysis.

Rise-time estimation

In this analysis we assume that the p-device stays in saturation

for the entire charging period of the load capacitor . The circuit
may then be modeled as in Figure
The saturation current for the p-transistor is given by
 This current charges and, since its magnitude is
approximately constant, we have

Substituting for and rearranging we have

We now assume that = ' when Vout = + V DD• so that

 with = 0.2VDD• then

This result compares reasonably well with a more detailed

analysis in which the charging of CL is divided, more correctly,
into two parts: (1) saturation and (2) resistive region of the
transistor
 Fall-time estimation
Similar reasoning can be applied to the discharge of CL through
the n-transistor. The circuit model in this case is given as Figure
4.10.

Making similar assumptions we may write for fall-time:

=
 Summary of CMOS rise and fall factors
Using these expressions we may deduce that:

But = 2.5 and hence = 2.5so that the rise-time is slower by a

factor of 2.5 when using minimum size devices for both 'n' and
'p'.
In order to achieve symmetrical operation using minimum
channel length, we would need to make = 2.5 and for
minimum size lambda-based geometries this would result in
the inverter having an input capacitance of 1 (n-device)
+ 2.5 (p-device) = 3.5 in total.
This simple model is quite adequate for most practical
situations, but it should be recognized that it gives
optimistic results. However, it does provide an insight into
the factors which affect rise-times and fall-times as
follows:

1. and are proportional to 1/VDD;

2. and are proportional to ;

3. = 2.5 for equal n- and p-transistor geometries.

PROPAGATION DELAYS
Cascaded Pass Transistors
MOS technology is the use of pass transistors as series or
parallel switches in logic arrays. Quite frequently, therefore,
logic signals must pass through a number of pass transistors in
series. A chain of four such transistors is shown in Figure 4.17(a)
in which all gates have been shown connected to VDD (logic 1),
which would be the case for a signal to be propagated to the
output. The circuit thus formed may be modeled as in Figure
4.17(b) and it is then possible to evaluate the delay through the
network.

The response -at node V2 with respect to time is given by

In the limit as the number of sections in such a network becomes

large, this expression reduces to
 where
R = resistance per unit length
C = capacitance per unit length
x = distance along network from input
The propagation time for a signal to propagate a distance x is
such that

The analysis can be simplified if all Rs and Cs are lumped

together, then
where r gives the relative resistance per section in terms of Rs
and c gives the relative capacitance per section in terms of

Then, it may be shown that overall delay ' for n sections is

given by

Thus, the overall delay increases rapidly as n increases and in

practice no more than four pass transistors should be normally
connected in series. However, this number can be exceeded if
a buffer is inserted between each group of four pass
transistors or if relatively long time delays are acceptable
Design of Long Polysilicon Wires

Long polysilicon wires also contribute distributed series R

and C as was the case for cascaded pass transistors and, in
consequence, signal propagation is slowed down. This
would also be the case for wires in diffusion where the
value of C may be quite high, and for this reason the
designer is discouraged from running signals in diffusion
except over very short distances..
For long polysilicon runs, the use of buffers is
recommended. In general, the use of buffers to drive long
polysilicon runs has two desirable effects. First, the signal
propagation is speeded up and, second, there is a reduction
in sensitivity to noise
The reason why noise may be a problem with slowly rising
signals may be deduced by considering Figure 4.18. In the
diagram the slow rise-time of the signal at the input of the
inverter (to which the signal emerging from the long
polysilicon line is connected) means that the input voltage
spends a relatively long time in the vicinity of Vinv so that
small disturbances due to noise will switch the inverter state
between '0' and '1' as shown at the output point.

Thus it is essential that long polysilicon wires be driven by

suitable buffers to guard against the effects of noise and to
speed up the rise-time of propagated signal edges.
 WIRING CAPACITANCES

Fringing Fields

Capacitance due to fringing field effects can be a major

component of the overall capacitance of interconnect wires.
For fine line metallization, the value of fringing field
capacitance ( Cff) can be of the same order as that of the area
capacitance. Thus, Cff should be taken into account if
accurate prediction of performance is needed.
 where
I = wire length
t = thickness of wire
d = wire to substrate separation

Then, total wire capacitance

Interlayer Capacitances
Quite obviously the parallel plate effects are present between one
layer and another. For example; some thought on the matter will
confirm the fact that, for a given area, metal to polysilicon
capacitance must be higher than metal to substrate. The reason for
not taking such effects into account for simple calculations is that
the effects occur only where layers cross or when one layer
underlies another, and in consequence interlayer capacitance is
highly dependent on layout. However, for regular structures it is
readily calculated and contributes significantly to the accuracy of
circuit modeling and delay calculation.
Peripheral Capacitance
The source and drain n-diffusion regions (n-active regions for
Orbit processes) form junctions with the p-substrate or p-well at
well-defined and uniform depths; similarly for p-diffusion (p-
active) regions in n-substrates or n-wells. For diffusion regions,
each diode thus formed has associated with it a peripheral (side-
wall) capacitance in picofarads per unit length which, in total, can
be considerably greater than the area capacitance of the diffusion
region to substrate; the smaller the source or drain area, the
greater becomes the relative value of the peripheral capacitance
For Orbit processes, the n-active and p-active regions are formed
by impurity implant at the surface of the silicon and thus, having
negligible depth, they have negligible peripheral capacitance.
However, for n- and p-regions formed by a diffusion process, the
peripheral capacitance is important and becomes particularly so as
we shrink the device dimensions.
In order to calculate the total diffusion capacitance we must
add the contributions of area and peripheral components

Typical values follow in Table 4.3. For further considerations

on capacitive effects the reader is referred to Arpad Barna,
VHSIC- Technologies and Tradeoffs, Wiley, 1981.
 CHOICE OF LAYERS

• Vdd and Vss (GND) should be distributed on metal layers

wherever possible and should not depart from metal except for
'duck unders', preferably on the diffusion layer when this is
absolutely essential. A consideration of Rs values will reveal the
reason for this.
• Long lengths of polysilicon should be used only after careful
consideration because of the relatively high Rs value of the
polysilicon layer. Polysilicon is unsuitable for routing Vdd or
Vss other than for very small distances.

• With these restrictions in mind, it is generally the case that the

resistances associated with transistors are much higher than any
reasonable wiring resistance, so that there is no real danger of
any problem due to voltage divider effects between wiring and
transistor resistances.
• Capacitive effects must also be carefully considered,
particularly where fast signal lines are required and
particularly in relation to signals on wiring having relatively
high values of Rs Diffusion (or active) areas have relatively
high values of capacitance to substrate and are harder to drive
in consequence. Charge sharing may also cause problems in
certain circuits or architectures and must be carefully
considered. Over small equipotential regions, the signal on a
wire can be treated as being identical at all points. Within each
region the delay associated with signal propagation is small in
comparison with gate delays and with signal delays in systems
connected by the wires.
Thus the wires in a MOS system can be modeled as simple
capacitors. This concept leads to the establishment of electrical
rules (guidelines) for communication paths (wires) as given in
Table 4.4.
Choice of layers
 Scaling of MOS Circuits

Microelectronic technology may be characterized in terms of

several indicators, or
figures of merit. Commonly, the following are used:
• Minimum feature size
• Number of gates on one chip
• Power dissipation
• Maximum operational · frequency
• Die size
• Production cost.
 SCALING MODELS AND SCALINIG FACTORS

The most commonly used models are the constant electric

field. scaling model and the constant voltage scaling model.
They both present a simplified view, taking only first degree
effects into consideration, but are easily understood and well
suited to educational needs. Recently, a combined voltage
and dimension scaling model has been presented
(Bergmann, 1991).
In order to accommodate the three models, two scaling factors- and
are used

is chosen as the scaling factor for supply voltage Vdd and gate
oxide thickness D,

is used for all other linear. dimensions, both vertical and horizontal
to the chip surface.

For the constant field model and the constant voltage model, and
respectively are applied.
 SCALING FACTORS FOR DEVICE PARAMETERS

1. Gate Area
= L.W.
where L and W are the channel length and width respectively
Both are scaled by .

= L.W = . =
 2.Gate capacitance Per Unit Area Co or Cox

where is the permittivity of the gate oxide (thinox) [= ]

D is the gate oxide thickness which is scaled by

=
 3. Gate capacitance

= LW

4. Parasitic Capacitance Cx
is proportional to

where d is the depletion width around source or drain which

is scaled by

is the area of the depletion region around source or drain

which is scaled by .

=
 where Qon is the average charge per unit area in the channel
in the 'on' state
is scaled by and Vgs is scaled by

=1

Channel Resistance Ron

.

where is the carrier mobility in the channel and is assumed

constant
.
 Gate Delay Td

Td is proportional to Ron . Cg

Td =1.

Maximum Operating Frequency fo

or, fo is inversely proportional to delay Td.

Saturation Current

noting that both Vgs and Vt, are scaled by 1 /, we have

 Current Density J

where A is the cross-sectional area of the channel in the 'on'

state which is scaled by

Switching Energy Per Gate

 Power Dissipation Per Gate Pg

Pg comprises two components such that

=+
where the static component

and the dynamic component

It will be seen that both and are scaled by

So, is scaled by
 Power Dissipation Per Unit Area

Power-speed Product

=
= . =
LIMITATIONS OF SCALING
Substrate Doping
So far, in discussing the various effects, we have neglected the built-in
(junction) potential VB, which in tum depends on the substrate doping level,
and this is acceptable so long as VB is small compared with Vdd· However,
when this no longer holds, then the effects of VB must be included

Substrate doping scaling factors

As the channel length of a MOS transistor is reduced, the
depletion region widths must also be scaled down to prevent the
source and drain depletion regions from meeting. Depletion
region width d for the junctions is given by
where
= relative permittivity Of silicon (12)
= permittivity of free space ( = 8.85 x F/cm)

V = effective voltage across the junction = +

q = electron charge
= doping level of substrate
Va (maximum value = Vdd) = applied voltage

= built-in (juncction) potential

and
 where
is the source or drain doping
is the intrinsic carrier concentration in silicon
In, say, 5 technology, VB is in the region of 500 mV whilst
applied voltage Va(= Vdd) is commonly 5 V so that VB may be
neglected for scaling considerations

If is scaled by

then can be scaled by

For some more recent technologies, is increased to reduce d so
that is also enlarged. (For example, if = and = then = 0.88 V). At
the same time, VDD is also scaled down, and is thus no longer
large compared with so -that must be taken account of in scaling.

Thus, for the combined voltage and dimension scaling model

applied to a transistor for which we have a known Va, we may
write

where m is a real number, so that

Now if we scale Va by we have

where Vs is the effective scaled voltage across the depletion region.
should be scaled by

so that d scales by .
This model not only expresses the effects of the relationship
between and , but also shows their relation to the scaling factor

Where m is large and is small, the scaling factor for reverts to. but
in other cases this model becomes significant
 Depletion width
is increased to reduce the depletion width, but this also increases
the threshold voltage
must be kept below. . At higher values of , the maximum electric
field which can be applied to the gate oxide is insufficient to
invert the substrate so that no channel can be formed

However, the technology of deep channel implantation increases

N only near the source and drain to substrate junctions
Thus, can be maintained at a satisfactory level in the channel
region and this problem is thus reduced

depletion width d and built-in potential will impose limitations

on scaling
 where is the maximum electric field induced in the one-sided
step junction
When is increased by a and if Va = 0, then is increased by In
and d is decreased by

Figure 5.2(a) shows the depletion width d as a function of substrate

concentration and supply voltage V DD· The dashed line indicates
the maximum depletion width for = Substituting into the equation
· for d, we have
 whence

The area of Figure 5.2(a) above the dashed line is the region
where the increased electric field will induce breakdown. Thus,
the point at which the dashed line and the = 0 line intersect
indicates the maximum allowable substrate doping level, which
is about = (for = ). At higher values of junction tunneling will
occur. Therefore allowable values for d fall below the dashed
line and above the =0 line.
Figure 5.2(b) shows the maximum electric field in the depletion
layer versus . Any applied voltage greater than = 0 will cause
breakdown to occur at lower values of
The effects of have been assumed to be negligible
LIMITS DUE TO SUBTHRESHOLD CURRENTS
One of the major concerns in the scaling of devices is the effect
on subthreshold current which is directly proportional to exp(:

When a transistor is in the off state, then the value of Vgs - Vt is

negative and should be as large as possible to minimize lsub·
As voltages are scaled down, the ratio of Vgs – Vt to kT will
reduce so that subthreshold current increases quite dramatically

For this reason it may be desirable to scaJe both Vgs and Vt

together with by factor rather than , since a is generally greater
than b
However, this increases electric field strengths and thus lowers
breakdown voltages
The maximum electric field across a depletion region is given by

This applies to a one-sided step junction

As discussed previously, () is scaled by

d is scaled by

is scaled by
if is greater than .then more electric field stress will be applied
across depletion regions of scaled-down transistors
At the same time, the junction breakdown voltage BV must be
considered. BV is given by
It will be seen that BV is thus scaled by and will decrease
 LIMITS ON LOGIC LEVELS AND SUPPLY
VOLTAGE DUE TO NOISE

Major advantages in the scaling of devices are smaller gate delay

time, that is, higher operating frequencies and lower power
dissipation.
However, the decreased inter-feature spacing and greater
switching speeds inevitably result in noise problems. Noise may
also be amplified and is thus a major concern
The mean square current fluctuation in the channel is given by

where is the equivalent noise resistance at the input

is the bandwidth
F.M. Klaassen and J. Prins (1966) have investigated the thermal
noise in a MOS transistor over a range of substrate doping levels
from

When a transistor works in saturation, is no longer proportional to

the gate voltage , and can be expressed as

And is the pinch off voltage given by

 where

is the junction (built-in) potential

Then, the equivalent noise resistance is given by

where

Since is a monotonically decreasing function of the gate oxide

thickness and substrate doping , is also a monotonically
decreasing function of the same parameters
Consequently, the main factor of the thermal noise is given by

This indicates that is strongly and directly dependent on and and

also, to a lesser extent, on

Considering current technology in which is scaled, the effect of

is smaller

Thus, the. expression for becqmes

When constant field scaling is applied, Vg is scaled by 1/, and
are scaled by . Consequently, is only slightly reduced owing to
the increased value of · Thus, the ratio of logic level to thermal
noise is degraded by almost the same factor.
LIMITS DUE TO CURRENT DENSITY
High purity aluminum seems the most attractive, and is thus the
most widely used, material for forming interconnections in VLSI
chips. However, the scaling down of dimensions also increases the
current density in interconnects by the same factor 'if constant field
scaling is applied. When the current density in aluminum
approaches Amps/ (10 the interconnects are likely to be burned
off owing to metal migration. Thus, allowable current densities are
set well below this limit and figures of J = 1 to 2 are commonly
used.
SWITCH LOGIC
Switch logic is based on the 'pass transistor' or on transmission
gates. This approach is fast for small arrays and takes no static
current from the supply rails. Thus, power dissipation of such
arrays is small since current only flows on switching.
Switch (pass transistor) logic is similar to logic arrays based on
relay contacts in that the path through each switch is isolated
from the signal activating the switch. In consequence, the
designer has a considerable amount of freedom in implementing
architectural features compared with bipolar logic-based designs
A number of texts on switching theory, some dating from the
1950s and 1960s, have sections on relay/switch logic and the
reader is referred to such material for generating ideas for
implementation in MOS switch logic
Basic And and Or connections are set out in Figure 6.1, but
many combinations of switches are possible
Pass Transistors and Transmission Gates

Switches and switch logic may be formed from simple n- or p-

pass transistors or from transmission gates (complementary
switches) comprising an n-pass and a p-pass transistor in parallel
as shown in Figure 6.2. The reason for adopting the apparent
complexity of the transmission gate, rather than using a simple n-
switch or p-switch in most CMOS applications, is to eliminate the
undesirable threshold voltage effects which give rise to the loss of
logic levels in pass transistors as indicated in Figure 6.2. No such
degradation occurs with the transmission gate, but more area is
occupied and complementary signals are needed to drive it. 'On'
resistance, however, is lower than that of the simple pass
transistor switches
When using nMOS switch logic, there is one restriction
which must always be observed: no pass transistor gate
input may be driven through one or more pass transistors
(see Figure 6.2).
As shown, logic levels propagated through pass transistors
are degraded by threshold voltage effects. Since the signal
out of pass transistor T1 does not reach a full logic 1, but
rather a voltage one transistor threshold below a true logic 1,
this degraded voltage would not permit the output of T2 to
reach an acceptable logic 1 level.
GATE (restoring) LOGIC
Gate logic is based oo the general arrangement typified by the
inverter circuits (the inverter being the simplest gate).
Both Nand and Nor and, with CMOS, And and Or gate
arrangements are available. Inverters are also employed to
complement and restore logic levels that have been degraded
(e.g. because they have passed through pass transistors).
The Inverter
Some of the most commonly used inverter circuit diagrams-the
inverter symbol, and the corresponding stick and symbolic
diagrams-should be familiar by now. An assortment is reproduced
here in Figure 6.3. Note that it is often useful to indicate the
nMOS inverter Zp.u / zp.d. ratio and/or the channel length to width
ratio for each MOS transistor as shown
In achieving the desired pull-up to pull-down ratio, several
possibilities emerge, two of which are illustrated in Figures 6.4
and 6.5 for an 8:1 nMOS inverter. Note the effect that the
different approaches have on power dissipation P d and on the
area occupied by the inverter. Also note the resistance and
capacitance values. The CMOS inverter carries no static
current and thus has no power dissipation unless switching.
The reader must not, however, imagine that CMOS circuits
have no dissipation problems. The switching dissipation for
fast CMOS logic circuits will be considerable.
Two-Input nMOS, CMOS and BICMOS Nand Gates
Two-input Nand gate arrangements are given in Figure 6.6.
The nMOS (and pseudo-nMOS) L: W ratios ·should be
carefully noted since they must be chosen to achieve the
desired overall Zp.u/ Z p d ratio (where Zpd. is contributed in
this case by both input transistors in series).
In order to arrive at the required L: W ratios for an nMOS (or
pseudo-nMOS) Nand gate with n inputs, it is only necessary to
consider the very simple circuit model of the gate in the
condition when all n pull-down transistors are conducting as in
Figure 6.7.
The critical factor here is that the output voltage Vout must be
near enough to ground to turn off any following inverter-like
stages, that is
where ZPd applies for any one pull-down transistor. The
boundary condition then is

that is, the ratio between Zp.u. and the sum of all the pull-
down Zp.d.s.must be 4:1 (as for the nMOS inverter).

This ratio must be adjusted appropriately if input signals are

derived through pass transistors
Further consideration of the nMOS Nand gate geometry reveals
two significant factors:

1. nMOS Nand gate area requirements are considerably greater

than those of a corresponding nMOS inverter, since not only must
pull-down transistors be added in series to provide the desired
number of inputs, but, as inputs are added, so must there be a
corresponding adjustment of the length of the pull-up transistor
channel to maintain the required overall ratio .
2. nMOS Nand gate delays are also increased in direct
proportion to the number of inputs added. If each pull-down
transistor is kept to minimum size (2 x 2 ), then each will present
at its input, but if there are n such inputs, .then the length and
resistance of the pull-up transistor must be increased by a factor
of n to keep the correct ratio. Thus, delays associated · with the
nMOS Nand are
 In consequence of these properties, the nMOS Nand gate is used
only where absolutely necessary and the number of inputs is
restricted.
The CMOS Nand gate has no such restrictions but, bearing in
mind the remarks on asymmetry (Figure 6.6), it is necessary to
allow for extended fall-times on capacitive loads owing to the
number of n-transistors in series forming the pull-down. Some
adjustment of transistor geometry may be necessary for this
reason and to keep the transfer characteristic symmetrical about
VDD/2 .

The BiCMOS gate shown is a practical version and is thus more

complex than the simple intuitive version. However, it has
considerable load-driving capabilities and is most useful where a
large fan-out is required or where there is some other form of high
capacitance load on the output.
Two-Input nMOS, CMOS and BICMOS Nor Gates