SECA1601-MICROPROCESSORS AND MICROCONTROLLERS

COURSE HANDLED BY
Dr.V.Vijaya Baskar,Dr.M.R.Ebenezar Jebarani, Dr.S.Lakshmi,
Dr.P.Chitra,Dr.Aranganathan
School of EEE,
Sathyabama Institute of Science and Technology,
Chennai.
 How to Achieve your Target
• You are eligible to give advise or Guide
• Remember that you have precious 1.5 years for learning
• Set your Target- Job, Salary, etc.
• Prepare yourself to achieve your target
• Set weekly target to reach your final target
• Think yourself in others position ( even for recruitment)
• Identify your domain and be strong in that domain
• Keep yourself away from the sources ,which are disturbing or wasting your time
(Bad Friends,Mobiles,etc.)
• At least two students can become entrepreneur-Lot of support available inside
the campus(TBI, Start up support, etc.)
• You have 1.5 years – Enough time to innovate a product- observe the
environment
 SEC1201 –Microprocessors And Microcontrollers

Course objectives
To understand
The operation of microprocessors and
microcontrollers

 Assembly language programming

 Interfacing techniques and their applications

 SEC1201 –Microprocessors And Microcontrollers

COURSE OUTCOMES:
At the end of the course student will be able to
 Remember the digital circuits (ALU, Registers, Counters, etc.)

which are building blocks of Microprocessor and Microcontroller (CO1)

 Understand the architecture of Microprocessor and Microcontroller (CO2)
 Solve problem using assembly program for microprocessor and

Microcontroller (CO3.)
 Identify the need for various interfacing ICs and understand its architecture

(CO4)
 Compare the advantages of Microcontroller over Microprocessor while

solving real world problems (CO5)

 Design and implement 8051 Microcontroller based system (CO6)
 Unit 1- Introduction to Microprocessors

Introduction 8085 Architecture

Pin Diagram and signals

Timing Diagram- Memory read, Memory write, I/O

cycle
Interrupts and its types

Introduction to 8086 microprocessors and its

operation
 UNIT 2 - Programming 8085 Microprocessor

8085 assembly language programming

 Addressing modes
8085 instruction set
Instruction formats
Instruction Classification:
 Data transfer
 Arithmetic operations
 Logical operations
 Branching operations
 Machine control —Stack and subroutines
 Example Programs
 UNIT 3 - Peripherals And Interfacing

Introduction, Memory And I/O Interfacing

Data Transfer Schemes
Interface ICs’-
 USART (8251)
 programmable peripheral interface (8255)
 programmable interrupt controller (8259)
 programmable counter/interval timer (8254)
 Analog to Digital Converter (ADC)
 Digital to Analog Converter (DAC)
 UNIT 4 - Introduction To Microcontrollers

Introduction to Microcontrollers
Difference Between Microprocessors and
Microcontrollers
Architectural Features of 8051
 I/O Ports, Interrupts
Addressing Modes and
Instruction Set Of 8051
Programming Examples
 UNIT 5 -Applications Based On 8085 And 8051

Interfacing Basic Concepts, Interfacing LED

7 Segment LED
Stepper Motor Control System
Temperature Control System
Traffic Light Control System
Motor Speed Control System
Waveform Generation, Interfacing LCD
 Text / Reference Books

1. Ramesh Gaonkar, “Microprocessor Architecture, Programming

and applications with 8085”, 5th Edition, Penram International
Publishing Pvt Ltd, 2010.

2. Kenneth J Ayala, “The 8051 Microcontroller”, 2nd Edition,

Thomson, 2005.

3. Nagoor Kani A, “Microprocessor and Microcontroller”, 2nd

Edition, Tata McGraw Hill, 2012.

4. Mathur A.P. ” Introduction to microprocessor “

5. Muhammad Ali Mazidi “The 8051 Microcontroller and Embedded

Systems.”
 UNIT 1

INTRODUCTION TO MICROPROCESSORS
 Basic Concepts of Microprocessors

 Microprocessor – silicon chip which includes

ALU, registers & control circuits

 Microcomputer – a computer with a

microprocessor as its CPU. Includes memory,
I/O etc.

 Microcontroller – silicon chip which includes

microprocessor, memory & I/O in a single
package.
 What is a Microprocessor?

• The word comes from the combination micro and processor.

 Processor means a device that processes whatever. In

this context processor means a device that processes
numbers, specifically binary numbers, 0’s and 1’s.
 To process means to manipulate. It is a general term that
describes all manipulation. Again in this content, it means
to perform certain operations on the numbers that depend
on the microprocessor’s design.
 What about micro?

• Micro is a new addition.

– In the late 1960’s, processors were built using
discrete elements.
• These devices performed the required operation, but were
too large and too slow.

– In the early 1970’s the microchip was invented. All

of the components that made up the processor were
now placed on a single piece of silicon. The size
became several thousand times smaller and the
speed became several hundred times faster. The
“Micro”Processor was born.
 Definition of the Microprocessor

• The microprocessor is a programmable device that

takes in numbers, performs on them arithmetic or
logical operations according to the program stored
in memory and then produces other numbers as a
result.
 Definition (Contd.)

• Lets expand each of the words:

– Programmable device: The microprocessor can perform different

sets of operations on the data it receives depending on the
sequence of instructions supplied in the given program. By
changing the program, the microprocessor manipulates the data in
different ways.

– Instructions: Each microprocessor is designed to execute a

specific group of operations. This group of operations is called an
instruction set. This instruction set defines what the
microprocessor can and cannot do.
 Definition (Contd.)

– Takes in: The data that the microprocessor manipulates

must come from somewhere.

• It comes from what is called “input devices”.

• These are devices that bring data into the system from the
outside world.

• These represent devices such as a keyboard, a mouse,

switches, and the like.

 Definition (Contd.)

– Numbers: The microprocessor can only understands

binary numbers.
 A binary digit is called a bit (which comes from binary
digit).
 The microprocessor recognizes and processes a
group of bits together. This group of bits is called a
“word”.
 The number of bits in a Microprocessor’s word, is a
measure of its “abilities”.
 Definition (Contd.)
– Words, Bytes, etc.
• The earliest microprocessor (the Intel 8088 and Motorola’s 6800)
recognized 8-bit words.
– They processed information 8-bits at a time. That’s why they are
called “8-bit processors”. They can handle large numbers, but
in order to process these numbers, they broke them into 8-bit
pieces and processed each group of 8-bits separately.

• Later microprocessors (8086 and 6800) were designed with 16-bit

words.
– A group of 8-bits were referred to as a “half-word” or “byte”.
– A group of 4 bits is called a “nibble”.
– Also, 32 bit groups were given the name “long word”.

• Today, all processors manipulate at least 32 bits at a time and there

exists microprocessors that can process 64, 80, 128 bits
 Definition (Contd.)
– Stored in memory :
• First, what is memory?
– Memory is the location where information is kept while not in
current use.
– Memory is a collection of storage devices. Usually, each
storage device holds one bit. Also, in most kinds of memory,
these storage devices are grouped into groups of 8. These 8
storage locations can only be accessed together. So, one
can only read or write in terms of bytes to and from memory.
– Memory is usually measured by the number of bytes it can
hold.
It is measured in Kilos, Megas and lately Gigas. A Kilo in computer
language is 210 =1024. So, a KB (KiloByte) is 1024 bytes. Mega is
1024 Kilos and Giga is 1024 Mega.
 Definition (Contd.)

– Stored in memory:
• When a program is entered into a computer, it is
stored in memory. Then as the microprocessor
starts to execute the instructions, it brings the
instructions from memory one at a time.

• Memory is also used to hold the data. The

microprocessor reads (brings in) the data from
memory when it needs it and writes (stores) the
results into memory when it is done.
 Definition (Contd.)

– Produces: For the user to see the result of the

execution of the program, the results must be
presented in a human readable form.
 The results must be presented on an output device.
 This can be the monitor, a paper from the printer, a
simple LED or many other forms.
 A Microprocessor-based system

From the above description, we can draw the following

block diagram to represent a microprocessor-based
system:

Input Output

Memory
 Inside The Microprocessor

• Internally, the microprocessor is made up of 3 main units.

 The Arithmetic/Logic Unit (ALU)

 The Control Unit.

 An array of registers for holding data while it is being

manipulated.
 Organization of a microprocessor- based system

• Let’s expand the picture a bit.

I/O
Input / Output
ALU Register
Array
System
Bus
Control Memory

ROM RAM
 Memory
• Memory stores information such as instructions and data in
binary format (0 and 1). It provides this information to the
microprocessor whenever it is needed.

• Usually, there is a memory “sub-system” in a

microprocessor-based system. This sub-system includes:
– The registers inside the microprocessor
– Read Only Memory (ROM)
• used to store information that does not change.
– Random Access Memory (RAM) (also known as
Read/Write Memory).
• used to store information supplied by the user. Such
as programs and data.
 Memory Map and Addresses
• The memory map is a picture representation of the
address range and shows where the different memory
chips are located within the address range.

0000 0000

EPROM Address Range of EPROM Chip

3FFF
4400
RAM 1 Address Range of 1st RAM Chip
5FFF
6000

RAM 2 Address Range of 2nd RAM Chip

8FFF
9000
RAM 3 Address Range of 3rd RAM Chip
A3FF
A400

Address Range of 4th RAM Chip

RAM 4

F7FF
FFFF
 Memory-Execute a program

• To execute a program:

– the user enters its instructions in binary format into the

memory.

– The microprocessor then reads these instructions and

whatever data is needed from memory, executes the
instructions and places the results either in memory or
produces it on an output device.
 The three cycle instruction execution model

• To execute a program, the microprocessor “reads” each

instruction from memory, “interprets” it, then “executes” it.
• To use the right names for the cycles:
– The microprocessor fetches each instruction,
– decodes it,
– Then executes it.
• This sequence is continued until all instructions are
performed.
 Programming Languages

 Machine or Binary Language

 Assembly Language
 High Level Language
 Machine Language

• The number of bits that form the “word” of a microprocessor

is fixed for that particular processor.
– These bits define a maximum number of combinations.
• For example an 8-bit microprocessor can have at
most 28 = 256 different combinations.

• However, in most microprocessors, not all of these

combinations are used.
– Certain patterns are chosen and assigned specific
meanings.
– Each of these patterns forms an instruction for the
microprocessor.
– The complete set of patterns makes up the
microprocessor’s machine language.
 The 8085 Machine Language

• The 8085 (from Intel) is an 8-bit microprocessor.

– The 8085 uses a total of 246 bit patterns to form its
instruction set.
– These 246 patterns represent only 74 instructions.
• The reason for the difference is that some (actually
most) instructions have multiple different formats.

– Because it is very difficult to enter the bit patterns

correctly, they are usually entered in hexadecimal instead
of binary.
• For example, the combination 0011 1100 which
translates into “increment the number in the register
called the accumulator”, is usually entered as 3C.
 Assembly Language

• Entering the instructions using hexadecimal is quite easier

than entering the binary combinations.
– However, it still is difficult to understand what a program
written in hexadecimal does.
– So, each company defines a symbolic code for the instructions.

– These codes are called “mnemonics”.

– The mnemonic for each instruction is usually a group of letters

that suggest the operation performed.
 Assembly Language

• Using the same example from before,

– 00111100 translates to 3C in hexadecimal (OPCODE)
– Its mnemonic is: “INR A”.

– INR stands for “increment register” and A is short for

accumulator.

• Another example is: 1000 0000,

– Which translates to 80 in hexadecimal.
– Its mnemonic is “ADD B”.

– “Add register B to the accumulator and keep the result in

the accumulator”.
 Assembly Language

• It is important to remember that a machine language

and its associated assembly language are completely
machine dependent.
– In other words, they are not transferable from one
microprocessor to a different one.
• For example, Motorolla has an 8-bit microprocessor
called the 6800.
– The 8085 machine language is very different from that of
the 6800. So is the assembly language.
– A program written for the 8085 cannot be executed on the
6800 and vice versa.
 “Assembling” The Program

• How does assembly language get translated into machine

language?

– There are two ways:

– 1st there is “hand assembly”.

• The programmer translates each assembly

language instruction into its equivalent hexadecimal
code (machine language). Then the hexadecimal
code is entered into memory.

– The other possibility is a program called an

“assembler”, which does the translation automatically.
 8085 Microprocessor Architecture
 8-bit general purpose µp

 Capable of addressing 64 k of memory

 Has 40 pins

 Requires +5 v power supply

 Can operate with 3 MHz clock

 8 bit multiplexed address/data bus, which reduce the number
of pins.
 16 address lines, hence it can address 2^16 = 64 K bytes of
memory
 5 hardware interrupts i.e. TRAP, RST7.5, RST65.5, RST5.5,
and INTR
 It provides DMA
Architecture of Intel 8085 Microprocessor
Internal Architecture (functional block diagram)of 8085
13
 Intel 8085 Microprocessor

Microprocessor consists of:

 ALU: performs data processing function.

 Registers: provide storage internal to CPU

 Timing & Control unit: control microprocessor

operations.
 Interrupts

 Serial I/O

 Address. Data & Internal data bus

 1. The ALU

• In addition to the arithmetic & logic circuits, the

ALU includes the accumulator, which is part of
every arithmetic & logic operation.
• Also, the ALU includes a temporary register used
for holding data temporarily during the execution of
the operation. This temporary register is not
accessible by the programmer.
 2. Registers Array
Registers Array : 14 register out of which 12 are 8 bit capacity and 2 of 16 bit.
Classified into 4 types
(a) General purpose register: (user accessible)

(b) Special Purpose Register[A, Instruction Register and Flag]

(b.1) Accumulator (A): (user accessible)

(b.2) Instruction Register: (user not accessible)

(b.3) Flag Register(F): (user accessible)

(c) Temporary Register[ W, Z, Temporary data register]

(c.1) Internally used by the MP(user not accessible)

(c.2) Temporary data register:

(d) Pointer Register or special purpose [SP, PC]

(d.1) Stack Pointer(SP)

(d.1) Program Counter(PC)

15
 Registers (Contd.)
– General Purpose Registers
• B, C, D, E, H & L (8 bit registers)
• Can be used singly
• Or can be used as 16 bit register pairs
– BC, DE, HL
• H & L can be used as a data pointer (holds
memory address)
– Special Purpose Registers Accumulator
B
Flags
C
• Accumulator (8 bit register) D E
H L
– Store 8 bit data Program Counter
Stack Pointer
– Store the result of an operation
– Store 8 bit data during I/O transfer Address 16 8
Data
 Registers (Contd.)
Temporary Register
 8 bit register
 During the arithmetic and logical operations one operand is
available in A and other operand is always transferred to
temporary register
For Eg.: ADD B – content of B is transferred into
temporary register before actual addition
Flag Register
 Five flag is connected to ALU
 After the ALU operation is performed the status of result will
be stored in five flags.
22
• Flag Register
– 8 bit register – shows the status of the microprocessor before/after an
operation
– S (sign flag), Z (zero flag), AC (auxiliary carry flag), P (parity flag)
& CY (carry flag)

D7 D6 D5 D4 D3 D2 D1 D0

S Z X AC X P X CY

– Sign Flag
• Used for indicating the sign of the data in the accumulator

• The sign flag is set if negative (1 – negative)

• The sign flag is reset if positive (0 –positive)

 Flag Register (Cont.)
Flag Significance
C or CY (Carry) CY is set when an arithmetic operation generates a carry
out, otherwise it is 0 (reset)

P (Parity) P= 1; if the result of an ALU operation has an even number

of 1’s in A;
P= 0; if number of 1 is odd.

AC (Auxiliary carry) Similar to CY,

AC= 1 if there is a carry from D3 to D4 Bit AC= 0 if there is
a no carry from D3 to D4 Bit (not available for user)

Z(zero) Z = 1; if result in A is 00H 0 otherwise

S(Sign) S=1 if D7 bit of the A is 1(indicate the result is -ive)

S= 0 if D7 bit of the A is 0(indicate the result is +ive)

17
• Zero Flag
– Is set if result obtained after an operation is 0
– Is set following an increment or decrement operation of that register
10110011
+ 01001101
1 00000000

• Carry Flag
– Is set if there is a carry or borrow from arithmetic
operation

1011 0101 1011 0101

+ 0110 1100 - 1100 1100

Carry 1 0010 Borrow 1110

0001 1 1001
• Auxillary Carry Flag
– Is set if there is a carry out of bit
3
• Parity Flag
– Is set if parity is even
– Is cleared if parity is odd
 Program Counter
• We have already discussed the general purpose
registers, the Accumulator, and the flags.
• The Program Counter (PC)
– This is a register that is used to control the sequencing
of the execution of instructions.
– This register always holds the address of the next
instruction.
– Since it holds an address, it must be 16 bits wide.
 Stack Pointer

• The Stack pointer

– The stack pointer is also a 16-bit register that is used

to point into memory.

– The memory this register points to is a special area

called the stack.

– The stack is an area of memory used to hold data that

will be retrieved soon.

– The stack is usually accessed in a Last In First Out

(LIFO) fashion.
 Non Programmable Registers

Instruction Register & Decoder

– Instruction is stored in IR after fetched by
processor
– Decoder decodes instruction in IR

Internal Clock generator

– 3 MHz internally
– 6 MHz externally
 3.Timing and Control Unit
 It generates the necessary timing and control signals

 works as the brain of the CPU

 For proper sequence and synchronization of all the operations of MP

 This unit generates all the timing and control signals necessary for
communication between microprocessor and peripherals.
 Clock (Crystal Oscillator)

 Control Signals (Rd,WR,ALE)

 Status signals [So,S1,S2(IO/M)]

 DMA (HOLD & HLDA)

 Reset (RESET IN & RESET OUT)

 4. INTERRUPTS
 Interrupt:- Occurrence of an external disturbance
 After servicing the interrupt, 8085 resumes its normal working
sequence
 Transfer the control to special routines
 Five interrupts: - TRAP, RST7.5, RST6.5, RST5.5, INTR
 In response to INTR, it generates INTA signal
TRAP [Non Maskable & High priority]

RST 7.5 [ Vector Interrupt ]

RST 6.5 [ Vector Interrupt ]

RST 5.5 [ Vector Interrupt ]

INTR [General Purpose ]

INTA [Interrupt Acknowledgement ]
 5. Serial Input/ Output

 Data transferred on D0- D7 lines is parallel data

 But under some condition it is used serial data transfer
 Serial data is entered through SID(serial input data) input
(received)
 Serial data is outputted on SOD(serial output data) input
(send)
 8085 Architecture (cont…)
In addition to register MP contains some latches and
buffer
Increment and
 16 bitdecrement
register address latch

Used
 to increment or decrement the content of PC and SP
 Address buffer
 8 bit unidirectional buffer
 Used to drive high order address bus(A8 to A15)
 When it is not used under such as reset, hold and halt etc this buffer is used
tristate high order address bus.
 Data/Address buffer
 8 bit bi-Directional buffer
 Used to drive the low order address (A0 to A7) and data (D0 to D7) bus.
 Under certain conditions such as reset, hold and halt etc. this buffer is used
tristate low order address bus.
20
Signals or Pin Configuration of 8085
 Pins
Power
Supply: +5 V
Frequency
Generator is
connected to
those pins

Input/Output/
Memory

Read

Write

Address latch
Multiplexed Enable
Address Data
Bus

Address
Bus
 Signals of 8085

 Address Bus
 Data Bus
 Control & Status Signals
 Externally Initiated Signals
 Serial I/O
 Power supply and Frequency
 8085 Pin Description
 The 8085 is an 8-bit general purpose microprocessor that
can address 64K Byte of memory.
 It has 40 pins and uses +5V for power. It can run at a maximum
frequency of 3 MHz.
 The pins on the chip can be grouped into 6 groups:
 Address Bus and Data Bus.
 Status Signals.
 Control signal
 Interrupt signal
 Power supply and Clock signal
 Reset Signal
 DMA request Signal
 Serial I/O signal

 Externally Initiated Signals.

26
 The Address and Data Busses
 Address Bus (Pin 21-28)
 16 bit address lines A0 to A15
 The address bus has 8 signal lines A8 – A15 which are unidirectional.

 The other 8 address lines A0 to A7 are multiplexed (time shared) with the
8 data bits.

 Data Bus (Pin 19-12)

 To save the number of pins lower order address pin are multiplexed with 8 bit
data bus (bidirectional)
 So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0 – D7 at the
same time.
 During the execution of the instruction, these lines carry the address bits during
the early part (T1 state), then during the late parts(T2 state) of the execution, they
carry the 8 data bits.
27
 Demultiplexing AD7-AD0

– From the above description, it becomes obvious that the AD7–

AD0 lines are serving a dual purpose and that they need to be
demultiplexed to get all the information.

– The high order bits of the address remain on the bus for three
clock periods. However, the low order bits remain for only one
clock period and they would be lost if they are not saved
externally. Also, notice that the low order bits of the address
disappear when they are needed most.

– To make sure we have the entire address for the full three
clock cycles, we will use an external latch to save the value of
AD7– AD0 when it is carrying the address bits. We use the ALE
signal to enable this latch.
 Demultiplexing AD7-AD0

8085
A15-A8

ALE

Latch
AD7-AD0 A7- A0

D7- D0

– Given that ALE operates as a pulse during T1, we will be

able to latch the address. Then when ALE goes low, the
address is saved and the AD7– AD0 lines can be used for
their purpose as the bi-directional data lines.
 Demultiplexing the Bus AD7 – AD0

• The high order address is placed on the address bus and

hold for 3 clk periods,
• The low order address is lost after the first clk period, this
address needs to be hold however we need to use latch
• The address AD7 – AD0 is connected as inputs to the
latch 74LS373.
• The ALE signal is connected to the enable (G) pin of the
latch and the OC – Output control – of the latch is
grounded
 Status Signals
Status Pins – ALE, S1, S0
1.ALE(Address Latch Enable): (Pin 30)
 Used to demultiplexed the address and data bus
 +ive going pulse generated when a new operation is started by uP.
 ALE = 1 when the AD0 – AD7 lines have an address
 ALE = 0 When it is low it indicates that the contents are data.
 This signal can be used to enable a latch to save the address bits from the AD lines.

2. S1 and S0 (Status Signal): (Pin 33 and 29)

 Status signals to specify the kind of operation being performed .
 Usually un-used in small systems.
S1 S0 Operation
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
 Control Signals

Control Pins – RD, WR, IO/M(active low)

1.RD: Read(Active low) (Pin 32)
 Read Memory or I/O device
 Indicated that data is to be read either from memory or I/P device and
data bus is ready
for accepting data from the memory or I/O device.
2.WR: Write(Active low) (Pin 31)
 Write Memory or I/O device
 Indicated that data on the data bus are to be written into selected
memory or I/P device.
3.IO/M: (Input Output/Memory-Active low) (Pin 34)
 Signal specifies that the read/write operation relates to whether
memory or I/O device.
 When (IO/M=1) the address on the address bus is for I/O device
 When (IO/M=0) the address on the address bus is for memory
 Control and status Signals
When S0, S1 is combined with IO/M(active low), we get status of
machine cycle
Control
S2(IO/M) S1 S0 OPERATION
Signal
0 1 1 Opcode fetch RD = 0
0 1 0 Memory read RD= 0
0 0 1 Memory write WR = 0
1 1 0 I/O read RD = 0
1 0 1 I/O write WR = 0
Interrupt INTA = 0
1 1 0
Acknowledge
Z 0 0 Halt
Z x x Hold RD, WR = Z
and INTA =1
Z x x Reset

Z= Tristate, X = don’t care

condition
 Interrupts
 They the signals initiated by an external device to request the
microprocessor
are to do a particular task or work.
There are five hardware interrupts called, (Pin 6-11)

 On receipt of an interrupt, the microprocessor acknowledges the interrupt

by the active low INTA (Interrupt Acknowledge) signal.

31
 Power supply and Clock Signal

Vcc (Pin 40) : single +5 volt power supply Vss (Pin 20) : Ground
There are 3 important pins in this group.

X0 and X1 :((Pin 1-2)

 Crystal or R/C network or LC
network connectionsto set the
frequency of internal clock generator.
 The frequency is internally divided by two.
 Since the basic operating timing frequency is 3 MHz, a 6 MHz
crystal is connected to the X0 and X1 pins.

CLK (output): (Pin 37)

 Clock Output is used as the system clock for peripheral and devices
interfaced with the microprocessor.
 Reset Signals
 Reset In (input, active low) (Pin 36)
 This signal is used to reset the microprocessor.
 The program counter inside the microprocessor is set to
zero(0000H)
 The buses are tri-stated.

 Reset Out (Output, Active High) (Pin 3)

 It indicates MP is being reset.
 Used to reset all devices when the
the connected
microprocessor is reset.
 DMA Request Signals
 DMA:
 When 2 or more devices are connected to a common bus, to prevent the devices from
interfering with each other, the tristate gates are used to disconnect all devices except the one
that is communicating at a given instant .
 The CPU controls the data transfer operation between memory and I/O device.
 DMA operation is used for large volume data transfer between memory and an I/O device
directly.
 The CPU is disabled by tri-stating its buses and the transfer is effected directly by external
control circuits.

 HOLD (Pin 38)

 This signal indicates that another device is requesting the use of address and data bus.
 So it relinquish the use of buses as soon as the current machine cycle is completed.
 MP regains the bus after the removal of a HOLD signal

 HLDA (Pin 39)

 On receipt of HOLD signal, the MP
acknowledges the request by sending out HLDA signal and
leaves out the control of the buses.
 After the HLDA signal the DMA controller starts the direct transfer of data.
 After the removal of HOLD request HLDA goes low.
 Serial I/O Signals
These pins are used for serial data communication
SID (input) Serial input data (Pin 4)
 It is a data line for serial input
 Used to accept serial data bit by bit from external device
 The data on this line is loaded into accumulator bit 7 whenever a
RIM instruction is executed.

SOD (output) Serial output data (Pin 5)

 It is a data line for serial output
 Used to transmit serial data bit by bit to the external device
 The 7th bit of the accumulator is outputted on SOD line when SIM
instruction is executed.
 Externally Initiated signal

 Ready (input) (Pin 35)

 Memory and I/O devices will have slower
response compared to microprocessors.
 Before completing the present job such a slow peripheral may not be
able to handle further data or control signal from CPU.
 The processor sets the READY signal after completing the present job
to access the data.
 It synchronize slower peripheral to the processor.
 The microprocessor enters into WAIT state while the READY pin is
disabled.
 The Address and Data Busses

• The address bus has 8 signal lines A8 – A15

which are unidirectional.
• The other 8 address bits are multiplexed (time
shared) with the 8 data bits.
– So, the bits AD0 – AD7 are bi-directional and serve
as A0 – A7 and D0 – D7 at the same time.
• During the execution of the instruction, these lines carry the
address bits during the early part, then during the late parts of
the execution, they carry the 8 data bits.
– In order to separate the address from the data, we
can use a latch to save the value before the function
of the bits changes.
 The Overall Picture
• Putting all of the concepts together, we
get: Chip Selection
A15- A10 Circuit

8085
CS
A15-A8

ALE
A9- A0 1K Byte
Latch Memory Chip
AD7-AD0 A7- A0

WR RD IO/M D7- D0
RD
WR
 8085 Architecture …… cont….
In addition to register MP contains some latches and
buffer
Increment and
 16 bitdecrement
register address latch

Used
 to increment or decrement the content of PC and SP
 Address buffer
 8 bit unidirectional buffer
 Used to drive high order address bus(A8 to A15)
 When it is not used under such as reset, hold and halt etc this buffer is used
tristate high order address bus.
 Data/Address buffer
 8 bit bi-Directional buffer
 Used to drive the low order address (A0 to A7) and data (D0 to D7) bus.
 Under certain conditions such as reset, hold and halt etc this buffer is used
tristate low order address bus.
20
 8085 Architecture …… cont….
(2) ALU & Logical Group: it consists ALU, Accumulator, Temporary
register and Flag Register.

(a) ALU
 Performs arithmetic and logical operations
 Stores result of arithmetic and logical operations in accumulator

(b) Accumulator
 General purpose register
 Stores one of the operand before any arithmetic and logical
operations and result of operation is again stored back in
Accumulator
 Store 8 bit data during I/O transfer
21
 8085 Programming register and
programming model
 The register which are programmable and available for the use are six

general purpose register, A, F, PC, SP.

8085 programming model

 Fetching & Exécution Cycles
 Fetching Cycles
 Thefetch cycle takes the instruction required
from memory, stores it in the instruction register, and
increment the program counter on one so that it points to the
next instruction.

 Execute cycle
 The actual actions which occur during the execute cycle of
an instruction.
 Depend on both the instruction itself and the addressing mode
specified to be used to access the data that may be required.

38
 Fetching an instruction

Step 1: Instruction pointer (program counter) hold

the address of the next instruction to be fetch.

39
 Fetching an instruction….Cont….

Step 2

40
 Fetching an instruction….Cont….

Step 3

41
 Fetching an instruction….Cont….

Step 4

42
 Fetching an instruction….Cont….

Step 5

43
 Fetching an instruction….Cont….

Step 6

44
 Data flow from memory to MPU

Steps and data flow,

when the instruction
code 01001111
(4FH –
MOV C,A)
Stored in the location
2005H, is being fetch.

Step 1: MPU places the 16 bit memory address from PC on the address bus
Step 2: Control unit send the signal RD to enable memory chip
Step 3: The byte from the memory location is placed on the data bus.
Step 4: The byte is placed on the instruction decoder of the MPU and task is
carried out according to the instruction.
 Buses Structure
 Various I/O devices and memories are connected to CPU by a group of lines

called as bus.

8085 Bus structure

 Generating Control Signals
Signals are used both for memory and I/O
related operations. So four different control
signals are generated by combining
the signals RD, WR and IO/M. MEMR =
Reading from memory MEMW = writing
into memory IOR = Reading from input
port IOW = writing to an output port

Fig: Generate Read/write control

signal for memory and I/O
Fig: 8085 De-multiplexed address and
data bus with control signal
Timing Diagram

7
4
 Introduction
 It represents the execution time taken by each instruction in a graphical format.
 It is the graphical representation of initiation of read/write and transfer of data
operations under the control of 3-status signals IO / M , S1, and S0. All the operation is
performed with respect to CLK signal.
 The combination of these 3-status signals identify read or write operation and remain
valid for the duration of the cycle.

Machine cycle status and control signal

Clock Signal - The 8085 divides the clock frequency
provided at x1 and x2 inputs by 2 which is called operating
frequency.
Rise time and fall time

T-State = 1 Clock cycle

Ideal Practical

Single Signal - Single signal status is

represented by a line. It may have status either logic 0 or
logic 1 or tri-state
 Group of signals - Group of signals is also called a bus.
Eg: Address bus, data bus

Machine cycle showing clock periods -

 Machine Cycles and
Instruction
From the above discussion, we can define terms that will become handy later
on:
T- State:
 One subdivision of an operation performed in one clock period.
 Each T states is precisely equal to one clock period.
 An instruction’s execution length is usually measured in a number of T-states.
Machine Cycle:
 The time required to complete oneoperation of accessing memory, I/O, or
 acknowledging an external request. i.e. Time required to execute a simple instruction or
part of the complex instruction
 This cycle may consist of 3 to 6 T-states.
 Various machine cycle in 8085 is
 Opcode fetch
 Memory read/write
 Input read/write
 Intereupt acknowledge
 Halt/hold
 Reset
Instruction Cycle:
 The time required to complete the execution of an instruction.
 In the 8085, an instruction cycle may consist of 1 to 6 machine cycles.
 Processor Cycle
 The function of the microprocessor is divided into two cycle of the instruction
 Fetch
 Execute
 Instructions are stored in the memory in sequence.

 In the normal process of operation, the microprocessor fetches (receives or reads) and
executes one instruction at a time in the sequence until it executes the halt (HLT)
instruction.

 Thus, an instruction cycle is defined as the time required to fetch and execute an
instruction.
Instruction Cycle (IC) = Fetch cycle (FC) + Execute Cycle (EC)

Processor Cycle
 Instruction cycle

Machine cycle 1 Machine cycle 2 Machine cycle 5

T – State 1 T – State 2 T – State 3 T – State 6

The 8085 microprocessor has 7 basic machine cycles. They are
1.Opcode fetch cycle (4T)
2.Memory read cycle or operand fetch(3 T)
3.Memory write cycle (3 T)
4.I/O read cycle (3 T)
5.I/O write cycle (3 T)
6.Interrupt Acknowledge
7.Bus Idle cycle
 Opcode Fetch Machine Cycle
The first step of executing any instruction is the Opcode fetch cycle.
In this cycle, the microprocessor brings in the instruction’s Opcode from

memory.
To differentiate this machine cycle from the very similar “memory read”

cycle, the control & status signals are set as follows:

 IO/M=0 (memory operation),

 s1 and s0 are both 1. (opcode fetch)

This machine cycle has four T-states.

 The 8085 uses the first 3 T-states to fetch the opcode.

 T4 is used to decode and execute it.
It is also possible for an instruction to have 6 T-states in an opcode fetch

machine cycle.
Timing Diagram of Opcode Fetch

Timing Diagram for Opcode Fetch Machine Cycle

 Timing: Transfer of byte from memory to
MPU
How a data byte is transfer from memory to the MPU.
It shows the five different group of signals with clock

Step 1: At T1 higher order memory address 20H is placed on the A15 – A8 and the lower
order memory address 05H is placed on the bus AD7-AD0, and ALE signal high. IO/M goes
low(memory related signal).

Step 2: During T2 RD signal is sent out. RD is active during two clock periods.

Step 3 : During T3, Memory is enabled then instruction byte 4FH is placed on the data bus
and transferred to MPU. When RD goes high it causes the bus to go into high impedance
state.
Step 4: During T4, the machine code or byte is decoded by the instruction decoder and
content of A is copied into register.
 Example: MOV C,A
Address:2005 , Opcode = 4F
Data Flow
form
Memory to
MP

85
 Memory Read or Operand Fetch Machine Cycle

 This cycle is executed by the processor to read a data byte from memory or
to fetch operand in a multi byte instruction. For ex. 2 or 3 byte instruction
because in 1 byte instruction the machine code is an opcode; so operation
is always an opcode fetch
 The instructions which have more than one byte word size will use the
machine cycle after the opcode fetch machine cycle.
 The memory read machine cycle is exactly the same as the opcode fetch
except:
 IO/M= 0(memory operation),
 s1 = 1 and s0 = 0. (memory read)
 WR = 1 & RD = 0
 It only has 3 T-states

 First cycle is opcode fetch cycle.

 So this cycle requires
4T(opcode) +3T(memory read )=7 T states to execute.
Timing Diagram of Memory Read Machine
Cycle
 Timing for execution of the instruction
MVI A, 32H
MVI A, 32H is 2 byte instruction, so hex code for MVI A is 3E.
8085 decode the opcode and finds out a second byte need to be read

High Impedance state.

The execution times of the memory read machine cycle and the instruction cycle
are calculated as

Clock Frequency f = 2MHz

T state = clock period (1/f) = 0.5µsec
Execution time for opcode fetch = 4T * 0.5 = 2µsec
Execution time for Memory Read = 3T * 0.5 = 1.5µsec
Execution time for Instruction = 7T * 0.5 = 3.5µsec

89
 Memory Write Machine Cycle
 The memory write machine cycle is executed by the processor
to write a data byte in a memory location.
 The memory write machine cycle is exactly the same as the
memory read except:
 IO/M= 0(memory operation),
 s1 = 0 and s0 = 1. (memory read
 WR = 0 & RD = 1
 It only has 3 T-states

 First cycle is opcode fetch cycle.

 So this cycle requires
4T(opcode) +3T(memory write )=7 T states to execute.
Timing Diagram of Memory write Machine Cycle
 Input/ Output Read Machine Cycle
 Microprocessor executes this cycle to read content of I/O port
or to read 8 bit data present on an input ports through data bus.
 The I/O read machine cycle is exactly the same as the memory
read except:
 IO/M= 1(I/O operation),
 s0 = 0 and s1 = 1. ( read)
 WR = 1 & RD = 0
 It only has 3 T-states

 This instruction reads the data from an input device and

places the data byte in the accumulator.
 It accept the data from input device by using
I/O read signal(IOR).
Timing Diagram of I/O read Machine Cycle
 Data Flow
form input
device to MP

96
 Input/output write Machine Cycle

 Microprocessor executes this cycle to write a data into an I/O

port or to write 8 bit data present on an output ports.
 The I/O write machine cycle is exactly the same as the memory
write except:
 IO/M= 1(I/O operation),
 s1 = 1 and s0 = 0. ( write)
 WR = 0 & RD = 1
 It only has 3 T-states

 This instruction places the content of the accumulator on the

data bus.
 It transmit the data to output device by using I/O write
signal(IOW).
Timing Diagram of I/O write Machine Cycle
 Interrupt Acknowledge Cycle

 Interrupt is hardware call of subroutine.

 MPU executes this cycle to acknowledge INTR request

 MPU determines the starting address of the interrupt

service routine by using interrupt information.
 RSTn and CALL address is used as interrupt information.

 Length of this cycle is 6T or 3T states.

 So two interrupt acknowledge cycle

(A) Interrupt acknowledge of RSTn

(B) Interrupt acknowledge of CALL address

 Interrupt Acknowledge of RSTn

 The RSTn instruction is one byte.

 It is similar to opcode fetch cycle with

 INTA signal is activated instead of RD
signal.
 IO/M= 1(I/O operation),

 s0 = 1 and s1 = 1.

 It only has 6 T-states

Timing Diagram of Restart instruction
 Interrupt Acknowledge for CALL

 The CALL instruction is Three byte. So MPU executes 3

interrupt acknowledge cycle.
 The length of the first cycle is 6 T states while second and third
cycle is 3T states.
 PC is not incremented. IR is selected as destination register
during 1st interrupt acknowledge cycle and in 2nd and 3rd cycle Z
and W are selected as destination register
 It is similar to opcode fetch cycle with
 IO/M= 1(I/O operation),

 s0 = 1 and s1 = 1.
Timing Diagram of CALL instruction
 Bus Idle Cycle
 The MPU executes this cycle for internal operation.
Few situations where the machine cycle are neither read nor
write.

 For Execution of DAD instruction: -

 this instruction add the content of a specified register pair to the
 After
contentopcode
of HLfetch,
pair. DAD requires extra 6 T states to add 16 bit
content .
 This extra T states are divided into two machine cycle do not involve
any memory or I/O operation.

 During Internal Opcode generation(For TRAP and RST) –

 In response to TRAP interrupt, 8085 enters into a bus idle cycle
during which it invokes restart instruction, stores the content of PC
onto the stack and places 0024H on the PC.
Timing Diagram of DAD instruction
Timing Diagram of DAD instruction
 WAIT State
 When speed of memory system and I/O system are not
compatible with MPU timings, means longer time for read/
write data.
 So MPU has to confirm whether a peripheral is to ready transfer
data op not
 If READY pin s high the peripheral is ready. Otherwise it is
continue as long as READY is low.
 During the wait state the content of the address bus, the data
bus and control bus are held constant.
 The wait state gives an I/O port an extra clock time to output
valid data on the data bus.
Timing Diagram Examples
STA 526A
STA….
IN C0
IN…
MOV A,M
MOV A,M
LXI H,FO45
LXI….
CALL example
• 4200 : Call 4F50
• HEX CODE CD,50,4F
• OPCODE FETCH, MR,MR
• PC= 4203 (SHOULD BE PUSHED TO STACK MEMORY)
• MW,MW
• SP=4100
• SP=SP-1
• = 4100-1
• =40FF - (42)
• SP=SP-1
• = 40FE (03)
Call 4F50
INR M
INR M
Interrupts
 Interrupts

• Interrupt is a process where an external device can get

the attention of the microprocessor.
– The process starts from the I/O device
– The process is asynchronous.

• Interrupts can be classified into two types:

• Maskable (can be delayed)
• Non-Maskable (can not be delayed)

• Interrupts can also be classified into:

• Vectored (the address of the service routine is hard-wired)
• Non-vectored (the address of the service routine needs to be supplied
externally)
 Interrupts
• An interrupt is considered to be an emergency signal.
– The Microprocessor should respond to it as soon as
possible.
• When the Microprocessor receives an interrupt signal,
it suspends the currently executing program and
jumps to an Interrupt Service Routine (ISR) to
respond to the incoming interrupt.
– Each interrupt will most probably have its own ISR.
 Responding to Interrupts

• Responding to an interrupt may be immediate or

delayed depending on whether the interrupt is
maskable or non-maskable and whether interrupts
are being masked or not.

• There are two ways of redirecting the execution

to the ISR depending on whether the interrupt is
vectored or non-vectored.
– The vector is already known to the Microprocessor
– The device will have to supply the vector to the
Microprocessor
 The 8085 Interrupts

• The maskable interrupt process in the 8085 is

controlled by a single flip flop inside the
microprocessor. This Interrupt Enable flip flop is
controlled using the two instructions “EI” and
“DI”.

• The 8085 has a single Non-Maskable interrupt.

– The non-maskable interrupt is not affected by the value
of the Interrupt Enable flip flop.
 The 8085 Interrupts

• The 8085 has 5 interrupt inputs.

– The INTR input.
• The INTR input is the only non-vectored interrupt.
• INTR is maskable using the EI/DI instruction pair.

– RST 5.5, RST 6.5, RST 7.5 are all automatically

vectored.
• RST 5.5, RST 6.5, and RST 7.5 are all maskable.

– TRAP is the only non-maskable interrupt in the

8085
• TRAP is also automatically vectored
 The 8085 Interrupts

Interrupt name Maskable Vectored

INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes
 Interrupt Vectors and the Vector Table

• An interrupt vector is a pointer to where the ISR

is stored in memory.
• All interrupts (vectored or otherwise) are mapped
onto a memory area called the Interrupt Vector
Table (IVT).
– The IVT is usually located in memory page 00
(0000H
- 00FFH).
– The purpose of the IVT is to hold the vectors that
redirect the microprocessor to the right place when an
interrupt arrives.
– The IVT is divided into several blocks. Each block is
used by one of the interrupts to hold its “vector”
 The 8085 Non-Vectored Interrupt
Process

1. The interrupt process should be enabled using the

EI instruction.
2. The 8085 checks for an interrupt during the
execution of every instruction.
3. If there is an interrupt, the microprocessor will
complete the executing instruction, and start a
RESTART sequence.
4. The RESTART sequence resets the interrupt flip
flop and activates the interrupt acknowledge
signal (INTA).
5. Upon receiving the INTA signal, the interrupting
device is expected to return the op-code of one of
the 8 RST instructions.
 The 8085 Non-Vectored
Interrupt
Process
6. When the microprocessor executes the RST
instruction received from the device, it saves the
address of the next instruction on the stack and
jumps to the appropriate entry in the IVT.
7. The IVT entry must redirect the microprocessor
to the actual service routine.
8. The service routine must include the instruction
EI to re-enable the interrupt process.
9. At the end of the service routine, the RET
instruction returns the execution to where the
program was interrupted.
 The 8085 Non-Vectored Interrupt
Process Restart Equivalent
Instruction to

RST0 CALL
0000H

• The 8085 recognizes 8 RST1 CALL

0008H
RESTART instructions: RST0 -
RST2 CALL
RST7. 0010H
– each of these would send the RST3 CALL
execution to a predetermined 0018H
hard-wired memory location: RST4 CALL
0020H
RST5 CALL
0028H
RST6 CALL
0030H
RST7 CALL
0038H
 Restart Sequence

• The restart sequence is made up of three machine

cycles
– In the 1st machine cycle:
• The microprocessor sends the INTA signal.
• While INTA is active the microprocessor reads the data lines
expecting to receive, from the interrupting device, the opcode
for the specific RST instruction.
– In the 2nd and 3rd machine cycles:
• the 16-bit address of the next instruction is saved on the
stack.
• Then the microprocessor jumps to the address associated with
the specified RST instruction.
 Restart Sequence

• The location in the IVT associated with

the RST instruction can not hold the
complete service routine.
– The routine is written somewhere else in
memory.
– Only a JUMP instruction to the ISR’s location
is kept in the IVT block.
 Hardware Generation of
RST Opcode

• During the interrupt acknowledge machine cycle,

(the 1st machine cycle of the RST operation):
– The Microprocessor activates the INTA signal.
– This signal will enable the Tri-state buffers, which
will place the value EFH on the data bus.
– Therefore, sending the Microprocessor the RST 5
instruction.

• The RST 5 instruction is exactly equivalent to

CALL 0028H
 Issues in Implementing
INTR
Interrupts
• How long must INTR remain high?
– The microprocessor checks the INTR line one clock
cycle before the last T-state of each instruction.
– The interrupt process is Asynchronous.
– The INTR must remain active long enough to allow
for the longest instruction.
– The longest instruction for the 8085 is the conditional
CALL instruction which requires 18 T-states.

Therefore, the INTR must remain active for 17.5

T-states.
 Issues in Implementing
INTR
Interrupts
• How long can the INTR remain high?
– The INTR line must be deactivated before the EI is
executed. Otherwise, the microprocessor will be
interrupted again.
– The worst case situation is when EI is the first
instruction in the ISR.
– Once the microprocessor starts to respond to an INTR
interrupt, INTA becomes active (=0).

Therefore, INTR should be turned off as soon as the

INTA signal is received.
 Issues in Implementing
INTR
Interrupts
• Can the microprocessor be interrupted again
before the completion of the ISR?
– As soon as the 1st interrupt arrives, all maskable
interrupts are disabled.
– They will only be enabled after the execution of the
EI instruction.

Therefore, the answer is: “only if you allow it to”.

If the EI instruction is placed early in the ISR, other
interrupt may occur before the ISR is done.
 Multiple Interrupts & Priorities

• How do we allow multiple devices to

interrupt using the INTR line?
– The microprocessor can only respond to one
signal on INTR at a time.
– Therefore, we must allow the signal from only
one of the devices to reach the
microprocessor.
– We must assign some priority to the different
devices and allow their signals to reach the
microprocessor according to the priority.
 The Priority Encoder

• The solution is to use a circuit called the priority

encoder (74366).
– This circuit has 8 inputs and 3 outputs.
– The inputs are assigned increasing priorities
according to the increasing index of the input.
• Input 7 has highest priority and input 0 has the lowest.
– The 3 outputs carry the index of the highest priority
active input.
– Figure 12.4 in the book shoes how this circuit can be
used with a Tri-state buffer to implement an
interrupt priority scheme.
• The figure in the textbook does not show the method for
distributing the INTA signal back to the individual devices.
 Multiple Interrupts & Priorities

• Note that the opcodes for the different RST

instructions follow a set pattern.
• Bit D5, D4 and D3 of the opcodes change in a binary
sequence from RST 7 down to RST 0.
• The other bits are always 1.
• This allows the code generated by the 74366 to be used
directly to choose the appropriate RST instruction.

• The one draw back to this scheme is that the

only way to change the priority of the devices
connected to the 74366 is to reconnect the
hardware.
 Multiple Interrupts and Priority

INTR
Dev. 7 O7
Circuit
O6 7
INTA Circuit
O5 4
Dev. 6 O4 RST Circuit
1
O3
3 +5 V
O2
Dev. 5
O1
8
O0
Dev. 4
INTA

Dev. 3
I7
INTR
AD7
8
I6
Dev. 2 7 AD6
I5
4
Dev. 1 I3 3
I4
0
AD5
I2 AD4
Tri –
Dev. 0
6 State
I1
I0 6
Priority
Buffer
8
AD3
Encoder
AD2
 The 8085
Maskable/Vect
ored
Interrupts
• The 8085 has 4 Masked/Vectored interrupt
inputs.
– RST 5.5, RST 6.5, RST 7.5
• They are all maskable.
• They are automatically vectored according to the following
table: Interrupt Vector
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

– The vectors for these interrupt fall in between the vectors for the RST
instructions. That’s why they have names like RST 5.5 (RST 5 and a
half).
 Masking RST 5.5, RST 6.5 and
RST 7.5

• These three interrupts are masked at two

levels:
– Through the Interrupt Enable flip flop and the
EI/DI instructions.
• The Interrupt Enable flip flop controls the whole
maskable interrupt process.
– Through individual mask flip flops that
control the availability of the individual
interrupts.
• These flip flops control the interrupts
individually.
 Maskable Interrupts

RST7.5
Memory
RST 7.5

M 7.5

RST
6.5
M 6.5

RST
5.5
M 5.5

INT
R
Interrupt
Enable
Flip Flop
 The 8085 Maskable/Vectored
Interrupt Process
1. The interrupt process should be enabled using the
EI instruction.
2. The 8085 checks for an interrupt during the
execution of every instruction.
3. If there is an interrupt, and if the interrupt is
enabled using the interrupt mask, the
microprocessor will complete the executing
instruction, and reset the interrupt flip flop.
4. The microprocessor then executes a call
instruction that sends the execution to the
appropriate location in the interrupt vector table.
 The 8085 Maskable/Vectored
Interrupt Process
5. When the microprocessor executes the call
instruction, it saves the address of the next
instruction on the stack.
6. The microprocessor jumps to the specific service
routine.
7. The service routine must include the instruction
EI to re-enable the interrupt process.
8. At the end of the service routine, the RET
instruction returns the execution to where the
program was interrupted.
 Manipulating the Masks

• The Interrupt Enable flip flop is manipulated

using the EI/DI instructions.

• The individual masks for RST 5.5, RST 6.5 and

RST 7.5 are manipulated using the SIM
instruction.
– This instruction takes the bit pattern in the Accumulator
and applies it to the interrupt mask enabling and
disabling the specific interrupts.
 How SIM Interprets the
Accumulator
7 6 5 4
3 2 1
0

}
RST5.5
Serial Data Mask 1-
Out Available
RST6.5 Mask
2 - Masked
RST7.5 Mask

Enable Serial Data 0 - Mask Set Enable 0 -

Ignore bit 7 Ignore bits 0-2
1 - Send bit 7 to SOD 1 - Set the masks
pin according to bits 0-2

Not Force RST7.5 Flip Flop to

Used reset
 SIM and the Interrupt Mask

• Bit 0 is the mask for RST 5.5, bit 1 is the mask

for RST 6.5 and bit 2 is the mask for RST 7.5.
• If the mask bit is 0, the interrupt is available.
• If the mask bit is 1, the interrupt is masked.

• Bit 3 (Mask Set Enable - MSE) is an enable for

setting the mask.
• If it is set to 0 the mask is ignored and the old settings remain.
• If it is set to 1, the new setting are applied.
• The SIM instruction is used for multiple purposes and not
only for setting interrupt masks.
– It is also used to control functionality such as Serial Data
Transmission.
– Therefore, bit 3 is necessary to tell the microprocessor whether or
not the interrupt masks should be modified
 SIM and the Interrupt Mask

• The RST 7.5 interrupt is the only 8085 interrupt that has
memory.
– If a signal on RST7.5 arrives while it is masked, a flip flop will
remember the signal.
– When RST7.5 is unmasked, the microprocessor will be
interrupted even if the device has removed the interrupt signal.
– This flip flop will be automatically reset when the microprocessor
responds to an RST 7.5 interrupt.

• Bit 4 of the accumulator in the SIM instruction allows

explicitly resetting the RST 7.5 memory even if the
microprocessor did not respond to it.
 SIM and the Interrupt Mask
• The SIM instruction can also be used to perform
serial data transmission out of the 8085’s SOD
pin.
– One bit at a time can be sent out serially over the SOD
pin.

• Bit 6 is used to tell the microprocessor whether

or not to perform serial data transmission
• If 0, then do not perform serial data transmission
• If 1, then do.
• The value to be sent out on SOD has to be placed
in bit 7 of the accumulator.

• Bit 5 is not used by the SIM instruction

 Using the SIM Instruction to
Modify the Interrupt
• Example: Set the interrupt masks so that
Masks
RST5.5 is enabled, RST6.5 is masked, and
RST7.5 is enabled.
– First, determine the contents of the accumulator
- Enable 5.5 bit 0 =
- Disable 6.5 0
- Enable 7.5 bit 1 =
0 0 0 0 1 0 1 0
- Allow setting the 1
masks bit 2 =
- Don’t reset the flip flop 0 Contents of accumulator are:
- Bit 5 is not used bit 3 = 0AH
- Don’t use serial data 1
- Serial data is ignored bit 4 =
EI 0
; Enable interrupts including INTR
MVI A, bit 5 = the mask to enable RST 7.5, and 5.5, disable
; Prepare
0A SIM 6.5 0
bit 6the
; Apply = settings RST masks
0
bit 7 =
0
 Triggering
Levels
• RST 7.5 is positive edge sensitive.
• When a positive edge appears on the RST7.5 line, a logic 1 is
stored in the flip-flop as a “pending” interrupt.
• Since the value has been stored in the flip flop, the line does
not have to be high when the microprocessor checks for the
interrupt to be recognized.
• The line must go to zero and back to one before a new
interrupt is recognized.

• RST 6.5 and RST 5.5 are level sensitive.

• The interrupting signal must remain present until the
microprocessor checks for interrupts.
 Determining the Current Mask
Settings
• RIM instruction: Read Interrupt Mask
– Load the accumulator with an 8-bit pattern
showing the status of each interrupt pin and
mask.
RST7.5
Memory
RST 7.5
M 7.5
7 6 5 4 3 2 1
0
RST
6.5
M 6.5

RST
5.5
M 5.5

Interrupt Enable
Flip Flop
 How RIM sets the
Accumulato
r’s different
7 6 5 4 3 2 1
0
bits
}
RST5.5 Mask
Serial Data In 1-
RST6.5 Mask
Available
RST7.5 Mask 2 - Masked
RST5.5 Interrupt
Pending RST6.5
Interrupt Pending Interrupt Enable
Value of the Interrupt
RST7.5 Interrupt
Enable Flip Flop
Pending
 The RIM Instruction and
the Masks

• Bits 0-2 show the current setting of the mask

for each of RST 7.5, RST 6.5 and RST 5.5
• They return the contents of the three mask flip flops.
• They can be used by a program to read the mask settings in
order to modify only the right mask.

• Bit 3 shows whether the maskable interrupt

process is enabled or not.
• It returns the contents of the Interrupt Enable Flip Flop.
• It can be used by a program to determine whether or not
interrupts are enabled.
 The RIM Instruction and
the Masks

• Bits 4-6 show whether or not there are pending

interrupts on RST 7.5, RST 6.5, and RST 5.5
• Bits 4 and 5 return the current value of the RST5.5 and
RST6.5 pins.
• Bit 6 returns the current value of the RST7.5 memory flip flop.

• Bit 7 is used for Serial Data Input.

• The RIM instruction reads the value of the SID pin on the
microprocessor and returns it in this bit.
 Pending Interrupts

• Since the 8085 has five interrupt lines, interrupts

may occur during an ISR and remain pending.
– Using the RIM instruction, the programmer can read
the status of the interrupt lines and find if there are
any pending interrupts.

– The advantage is being able to find about interrupts

on RST 7.5, RST 6.5, and RST 5.5 without having
to enable low level interrupts like INTR.
 Using RIM and SIM to set
Individual Masks

• Example: Set the mask to enable RST6.5 without

modifying the masks for RST5.5 and RST7.5.
– In order to do this correctly, we need to use the RIM
instruction to find the current settings of the RST5.5
and RST7.5 masks.
– Then we can use the SIM instruction to set the masks
using this information.
– Given that both RIM and SIM use the Accumulator,
we can use some logical operations to masks the un-
needed values returned by RIM and turn them into
the values needed by SIM.
 Using RIM and SIM to set
Individual Masks
– Assume the RST5.5 and RST7.5 are enabled and the interrupt process
is disabled. Accumulato
r

RIM ; Read the current

0 0 0 0 0 0 1
settings.
0

ORI ;00001000 0 0 0 1 1
08H ; Set bit 4 for 0 0 0
MSE.

ANI ;00001101 0 0 0 0 1 0 0
0DH ; Turn off Serial Data, Don’t reset 0
; RST7.5 flip flop, and set the
mask
; for RST6.5 off. Don’t cares are
; assumed to be 0. 0 0 0 0 1 0 0 0
SIM ; Apply the
settings.
 TRAP

• TRAP is the only non-maskable interrupt.

– It does not need to be enabled because it cannot be
disabled.
• It has the highest priority amongst interrupts.
• It is edge and level sensitive.
– It needs to be high and stay high to be recognized.
– Once it is recognized, it won’t be recognized again
until it goes low, then high again.

• TRAP is usually used for power failure and

emergency shutoff.
 Internal Interrupt Priority

• Internally, the 8085 implements an interrupt

priority scheme.
– The interrupts are ordered as follows:
• TRAP
• RST 7.5
• RST 6.5
• RST 5.5
• INTR

– However, TRAP has lower priority than the HLD

signal used for DMA.
 The 8085 Interrupts

Interrupt Masking Triggerin

Maskable Vectored Memory
Name Method g Method
Level
INTR Yes DI / EI No No
Sensitive
RST 5.5 / DI / EI Level
Yes Yes No
RST 6.5 SIM Sensitive
DI / EI Edge
RST 7.5 Yes Yes Yes
SIM Sensitive
Level &
TRAP No None Yes No Edge
Sensitive
Block diagram of 8086
Software Model of the 8086 Microprocessors
 8086 Registers
General Purpose Index
AH AL
BP
AX

SP
BH BL
BX
SI

CH CL
DI
CX

DH DL
DX Segment

CS

Status and Control SS

Flags DS

IP ES
 General Purpose Registers

AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register

• Normally used for storing temporary results

• Each of the registers is 16 bits wide (AX, BX, CX, DX)
• Can be accessed as either 16 or 8 bits AX, AH, AL
 General Purpose Registers

• AX
– Accumulator Register
– Preferred register to use in arithmetic, logic
and data transfer instructions because it
generates the shortest Machine Language
Code
– Must be used in multiplication and division
operations
– Must also be used in I/O operations

• BX
– Base Register
– Also serves as an address register
 General Purpose Registers

• CX
– Count register
– Used as a loop counter
– Used in shift and rotate operations

• DX
– Data register
– Used in multiplication and division
– Also used in I/O operations
 Pointer and Index Registers

• All 16 bits wide, L/H bytes are not accessible

• Used as memory pointers
– Example: MOV AH, [SI]
• Move the byte stored in memory location whose address is contained in register
SI to register AH

• IP is not under direct control of the programmer

 Flag Register

Overflow Carry
Direction Parity

Interrupt enable Auxiliary Carry

Trap Zero
6 are status flags
Sign
3 are control flag
 8086 Programmer’s Model
ES Extra Segment
CS Code Segment
BIU registers SS Stack Segment
DS Data Segment
(20 bit adder)
IP Instruction Pointer

AX AH AL Accumulator
EU registers BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS
 The Stack

• The stack is used for temporary storage of

information such as data or addresses.

• When a CALL is executed, the 8086 automatically

PUSHes the current value of CS and IP onto the
stack.

• Other registers can also be pushed

• Before return from the subroutine, POP instructions

can be used to pop values back from the stack into
the corresponding registers.
The Stack
INTEL 8086 - Pin Diagram
 INTEL 8086 - Pin DETAILS

Power Supply
5V  10%
Ground

Reset
Registers, seg
regs, flags
CS: FFFFH, IP:
0000H
If high for
minimum 4
Clock clks
Duty cycle: 33%
 INTEL 8086 - Pin DETAILS

Address/Data Bus:
Contains address bits Address Latch Enable:
A15-A0 when ALE is 1
& data bits D15 – D0 When high,
multiplexed
when ALE is 0.
address/data bus
contains address
information.
 INTEL 8086 - Pin DETAILS

INTERRUPT

Non - maskable
interrupt

Interrupt
acknowledge

Interrupt request
INTEL 8086 - Pin DETAILS

Direct
Memory
Access

Hold

Hold
acknowledge
INTEL 8086 - Pin DETAILS

Address/Status Bus
Address bits A19 –
A16 & Status bits S6 –
S3
 INTEL 8086 - Pin DETAILS

BHE#, A0: Bus High Enable/S7

0,0: Whole word Enables most
(16-bits)
significant data bits
0,1: High byte D15 – D8 during read
to/from odd address or write operation.
1,0: Low byte S7: Always 1.
to/from even address

1,1: No selection
 INTEL 8086 - Pin DETAILS

Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V

Minimum Mode Pins

Maximum Mode
Pins
Minimum Mode- Pin Details
 Maximum Mode - Pin Details

S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access
101: read memory
Status Signal
110: write memory
Inputs to 8288 to
111: none -passive
generate eliminated
signals due to max
mode.
 Maximum Mode - Pin Details

Lock Output
Used to lock peripherals
off the system
DMA
Activated by using the
Request/Grant
LOCK: prefix on any
instruction

Lock Output
 Maximum Mode - Pin Details

QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode

Queue Status
Used by numeric
coprocessor (8087)
• MOV A, H
• MVI A,08
• LXI H,9100
• INR M
• LDA 9100
THANK YOU