+

Chapter 3  A Top-Level View of Computer

 Function and Interconnection

William Stallings, Computer Organization and Architecture,9 th Edition

+ Objectives 2

CLO4 Describe in detail the essential elements of computer organisation including

internal bus, memory, Input/Output ( I/O) organisations and interfacing
standards and discuss how these elements function;

 At top level, what are main components of a computer?

 How are they connected?
 After studying this chapter, you should be able to:
 Understand the basic elements of an instruction cycle and the role of
interrupts.
 Describe the concept of interconnection within a computer system.
 Understand the difference between synchronous and asynchronous bus
timing.
 Explain the need for multiple buses arranged in a hierarchy.
 Assess the relative advantages of point-to-point interconnection compared
to bus interconnection.
+ 3

Contents

CLO4 Describe in detail the essential elements of computer organization including

internal bus, memory, Input/Output ( I/O) organizations and interfacing
standards and discuss how these elements function.

 3.1- Computer Components

 3.2- Computer Function
 3.3- Interconnection Structures
 3.4- Bus Interconnection
+ 4

3.1- Computer Components

 Contemporary (nowaday) computer designs are based on concepts
developed by John von Neumann at the Institute for Advanced
Studies, Princeton (Stored Program)

 Referred to as the von Neumann architecture and is based on three

key concepts:
 Data and instructions are stored in a single read-write memory
 The contents of this memory are addressable by location, without regard to
the type of data contained there
 Execution occurs in a sequential fashion (unless explicitly modified) from
one instruction to the next

 Hardwired program
 The result of the process of connecting the various components in the
desired configuration
+
Programming:H
ardware
and Software
Approaches
Lập trình là gì?
Đọc phần note của
slide để có lời giải
thích
 6
Read by yourself for more details
Software
• A sequence of codes or instructions Software
• Part of the hardware interprets each instruction and
generates control signals
• Provide a new sequence of codes for each new program
instead of rewiring the hardware
Major components:
I/O
• CPU Components
• Instruction interpreter
• Module of general-purpose arithmetic and logic
functions
• I/O Components
+ • Input module
• Contains basic components for accepting data and
instructions and converting them into an internal form
of signals usable by the system
• Output module
• Means of reporting results
 7

Computer
Components:
Top Level
View
+ Computer CPU   MEM 8

Components: Memory address Memory buffer

register (MAR) register (MBR)
Means for • Specifies the address in • Contains the data to be
memory for the next written into memory or
communication read or write receives the data read
from memory
s
 Communicate
between two I/O address register I/O buffer register
(I/OAR) (I/OBR)
objects = • Specifies a particular I/O • Used for the exchange of
transfer data device data between an I/O
module and the CPU
back and forth
between them.

CPU   IO
 9
CÁC THANH GHI GIÚP CPU TRUY XUẤT BỘ NHỚ

Memory address Memory buffer MEMORY

register (MAR) register (MBR)
• Specifies the address in • Contains the data to be
memory for the next written into memory or
read or write receives the data read
from memory

MAR

I/O address register I/O buffer register

(I/OAR) (I/OBR)
• Specifies a particular I/O • Used for the exchange of
+ device data between an I/O
module and the CPU

MBR

CÁC THANH GHI GIÚP CPU TRUY XUẤT IO

+ 10

3.2- Computer Function

CPU thực thi lệnh như thế nào?

Basic Instruction Cycle – 2 bước của chu kỳ lệnh cơ bản

(1) Fetch cyle: Lệnh kế tiếp từ bộ nhớ (địa chỉ trong PC) được
chuyển vào thanh ghi IR
(2) Execute cycle: Từ opcode của lệnh hiện hành, một mạch xử lý
phù hợp trong ALU được kích hoạt để thực thi lệnh
 11
Categories of actions
Các hành động của phần cứng
• Data transferred • Data transferred to or
from processor to from a peripheral
memory or from device by
memory to processor transferring between
Communications •
the processor and an
I/O module

Processor-
I/O
memory
Processor-

Control Data
processing

• An instruction may • The processor may

specify that the perform some
sequence of arithmetic or logic
execution be altered operation on data
+ Instruction structure: Lệnh máy: Mô tả 1
hành động- Một thí dụ
12

4- bit opcode 
maximum of 16 actions

Tập lệnh giả định này được dùng cho

việc chạy chương trình ở slide kế tiếp
 + Example
of
Program
Execution
1940(h)
1(h): 0001
 Load AC from memory 940(h)

5941(h)
5(h) 0101
 Add to AC from memory 941(h)

2941(h)
2(h): 0010Store AC to memory 941

 Add 2 memory cell at addresses 940,

941. The result is stored at 941
Khi thực thi 1 lệnh, PC tự động tăng 1
đơn vị sang địa chỉ của lệnh kế tiếp
+ 14

Instruction Cycle State Diagram

Lặp nếu trong lệnh Opcode Addr1 Addr2
có nhiều toán hạng

Vector:
nhóm trị,
thí dụ
{1,2,3,4,5}
String:
chuỗi ký
tự, thí dụ
“abcde”
+ Interrupts – Ngắt 15

- Interrupt: A signal will pause CPU

5V Interrupt pin
normal CPU execution for doing Interrupt occurs: 5V  0v
something else.
- Interrupt sources: IO Module
Program Flow Control 16

Xem giải thích trong phần note

+ 17

Transfer of Control via Interrupts

- Chuyển điều khiển:

Buộc CPU tạm ngưng
thực thi code ở vùng nhớ
này để thực thi code ở
vùng nhớ khác.
- Tập lệnh giúp CPU xử
lý 1 intterupt được gọi là
Interrupt Handler được
ấn định sẵn trong bộ nhớ
ROM
+ 18

Instruction Cycle With Interrupts

CPU thực thi HOÀN TẤT lệnh

hiện hành rồi mới xử lý interrupt.
CPU
5V Interrupt
Interrupts Disabled/Enabled: pin
OS decides whether CPU accepts interrupt or not

IO Module
+ 19

Program
Timing:
Short I/O
Wait

Vẫn là thí dụ cũ nhưng hình vẽ dựa trên thời gian

thực thi đoạn code nào. Vùng ĐEN: CPU không
chạy lệnh nào cả  Hiệu suất thấp
+ 20

Program
Timing:
Long I/O
Wait
Với long IO wait, user
program vẫn phải chờ. Tuy
nhiên hiệu suất vẫn cao hơn
khi không dùng interrupt.
Instruction Cycle State Diagram
21

With Interrupts
 22

Transfer of
Multiple
Control
interrupt:
Tình huống
code interrupt
này lại kích
hoạt interupt Multiple
khác (nested) Interrupts
 Hiệu suất
giảm nhiều.

+ Cách giải quyết 1: Chỉ dùng cơ chế

tuần tự thông qua cơ chế độc chiếm.
Cách giải quyết 2: ấn định độ ưu tiên
cho các interrupt(cơ chế nhường).
+ Time Sequence of Ex
23

Multiple Interrupts am
ple
+ 24

I/O Function
 I/O module can exchange data directly with the processor

 Processor can read data from or write data to an I/O module

 Processor identifies a specific device that is controlled by a particular I/O
module
 I/O instructions rather than memory referencing instructions

 In some cases it is desirable to allow I/O exchanges to occur directly

with memory
 The processor grants to an I/O module the authority to read from or write
to memory so that the I/O memory transfer can occur without tying up the
processor
 The I/O module issues read or write commands to memory relieving (làm
giảm nhẹ) the processor of responsibility for the exchange
 This operation is known as direct memory access (DMA)
+
25

3.3- Interconnection
Structures

Đầu ra của thành phần này nối vào

đầu vào của thành phần khác.
The interconnection structure must support the 26

following types of transfers:

I/O to or
Memory to Processor I/O to Processor
from
processor to memory processor to I/O
memory

An I/O
module is
allowed to
exchange data
Processor Processor
Processor directly with
reads an reads data Processor
writes a unit memory
instruction or from an I/O sends data to
of data to without going
a unit of data device via an the I/O device
memory through the
from memory I/O module
processor
using direct
memory
access
 27
A communication pathway Signals transmitted by any one
connecting two or more devices device are available for reception
• Key characteristic is that it is a shared
transmission medium
by all other devices attached to
the bus
• If two devices transmit during the same
3.4-
time period their signals will overlap
and become garbled Bus
Inter-
Typically consists of multiple
communication lines Computer systems contain a connec
number of different buses that
tion
• Each line is capable of transmitting
signals representing binary 1 and provide pathways between
binary 0 components at various levels of
the computer system hierarchy

Bus is a set of
connecting lines.
System bus 3 buses: Data/
• A bus that connects major computer
components (processor, memory, I/O)
The most common computer Address/
interconnection structures are
based on the use of one or more Control bus.
system buses
 28

Data Bus

 Datalines that provide a path for moving data among

system modules
 May consist of 32, 64, 128, or more separate lines
 The number of lines is referred to as the width of the
data bus
 The number of lines determines how many bits can be
transferred at a time((n: bus width  n bits/ transmission)
 The width of the data bus is a key factor in
determining overall system performance
+ Address Bus 29

 Used to designate the source or destination of the data on the data

bus
 If the processor wishes to read a word of data from memory it
puts the address of the desired word on the address lines
 Widthdetermines the maximum possible memory capacity of the
system ( n: bus width  2n mem. words)
 Also used to address I/O ports
 The higher order bits are used to select a particular module on
the bus and the lower order bits select a memory location or I/O
port within the module
+ Control Bus 30

 Used to control the access and the use of the data and address lines
 Because the data and address lines are shared by all components
there must be a means of controlling their use
 Controlsignals transmit both command and timing information
among system modules
 Timing signals indicate the validity of data and address
information
 Command signals specify operations to be performed
 31

Bus Interconnection Scheme

Fig. 3.17- Example Bus Configuration 32

Configuration/cấu hình:
một cách lắp đặt cụ thể
Fig. 3.17- Example Bus Configuration 33
+ Elements of Bus Design
34

Dedicated: chuyên dụng, multiplex: đa thành phần

Synchronous- đồng bộ- At a time, only one device can uses the bus. The others must
wait until the bus is idle.
Asynchronous- không đồng bộ- At a time, some devices can use the bus concurrently
Arbitration: phân xử, quản lý
 35

Timing of
Synchronous
Bus Operations

Synchronous bus:
Bus in which all
components share a
pulse generator 
They operate at the
same frequency.
 36

Timing of
Asynchronous
Bus
Operations
Asynchronous bus:
Bus in which each
component has a
individual pulse
generator  They
operate at different
frequencies.
+ 37

Questions
(Write answers to your notebook)

 3.1 What general categories of functions are specified by computer

instructions?

 3.2 List and briefly define the possible states that define an
instruction execution.

 3.3 List and briefly define two approaches to dealing with multiple
interrupts.

 3.4 What types of transfers must a computer’s interconnection

structure (e.g., bus) support?

 3.5 What is the benefit of using a multiple-bus architecture compared

to a single-bus architecture?
+ 38

Building Block
Read by yourself
 3.5- Point-to-Point Interconnect

 3.6- PCI Express

+ Summary A Top-Level View of
39

Computer Function and

Interconnection
Chapter 3

 Computer components
 Computer function
 Instruction fetch and execute
 Interrupts
 I/O function
 Interconnection structures
 Bus interconnection
 Bus structure
 Multiple bus hierarchies
 Elements of bus design