Multiprocessors

Outline
• MP Motivation
• SISD v. SIMD v. MIMD
• Centralized vs. Distributed Memory
• Challenges to Parallel Programming
• Consistency, Coherency, Write Serialization
• Write Invalidate Protocol
• Example
• Conclusion
CSCI 330 – Computer Architecture

SISD vs SIMD vs MIMD

 Uniprocessor Performance (SPECint)
3X
From Hennessy and Patterson,
10000
Computer Architecture: A Quantitative
Approach, 4th edition, 2006
??%/year

1000
Performance (vs. VAX-11/780)

52%/year

100

10
25%/year

1
1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006
• VAX : 25%/year 1978 to 1986
• RISC + x86: 52%/year 1986 to 2002
• RISC + x86: ??%/year 2002 to present
 Other Factors  Multiprocessors
• Growth in data-intensive applications
– Data bases, file servers, …
• Growing interest in high-end servers as cloud
computing and SaaS, server performance.
• Increasing desktop performance less important
– Outside of graphics
• Improved understanding in how to use multiprocessors
effectively
– Especially server where significant natural TLP
• Advantage of leveraging design investment by
replication
– Rather than unique design
 Flynn’s Taxonomy M.J. Flynn, "Very High-Speed Computers",
Proc. of the IEEE, V 54, 1900-1909, Dec. 1966.

• Flynn classified by data and control streams in 1966

Single Instruction Single Data Single Instruction Multiple
(SISD) Data SIMD
(Uniprocessor) (single PC: Vector, CM-2)

Multiple Instruction Single Multiple Instruction Multiple

Data (MISD) Data MIMD
(????) (Clusters, SMP servers)

• SIMD  Data Level Parallelism

• MIMD  Thread Level Parallelism
• MIMD popular because
– Flexible: N pgms and 1 multithreaded pgm
– Cost-effective: same MPU in desktop & MIMD
• Multiprocessors – computers consisting of
tightly coupled processors and controlled by
single processing system
• Parallel processing – single task with multiple
parallel threads
• Request level parallelism – single application
running on MPs, such as database responding
queries, often called multiprogramming
• Multicore – single-chip with multiple cores
 Back to Basics
• “A parallel computer is a collection of processing
elements that cooperate and communicate to solve
large problems fast.”
• Parallel Architecture = Computer Architecture +
Communication Architecture
• 2 classes of multiprocessors w.r.t memory:
1. Centralized Memory Multiprocessor
• < few dozen processor chips (and < 100 cores) in 2006
• Small enough to share single, centralized memory
2. Physically Distributed-Memory multiprocessor
• Larger number chips and cores than 1.
• BW demands  Memory distributed among processors
 Centralized vs. Distributed
Memory
Scale
P1 Pn P1 Pn

$ $ $ $
Mem Mem
Inter
connection network
Inter
connection network
Memory

Centralized Memory Distributed Memory

Centralized
Memory

Distributed
Memory
Centralized Memory Multiprocessor
• Also called symmetric multiprocessors (SMPs)
because single main memory has a symmetric
relationship to all processors
• Large caches  single memory can satisfy
memory demands of small number of processors
• Can scale to a few dozen processors by using a
switch and by using many memory banks
• Although scaling beyond that is technically
conceivable, it becomes less attractive as the
number of processors sharing centralized memory
increases
Distributed Memory Multiprocessor
• Pro: Cost-effective way to scale memory
bandwidth
• If most accesses are to local memory

• Pro: Reduces latency of local memory

accesses
• Con: Communicating data between
processors more complex
• Con: Must change software to take
advantage of increased memory BW
 2 Models for Communication and
Memory Architecture
1. Communication occurs by explicitly passing
messages among the processors:
message-passing multiprocessors
2. Communication occurs through a shared
address space (via loads and stores):
shared memory multiprocessors either
• UMA (Uniform Memory Access time) for shared
address, centralized memory MP
• NUMA (Non Uniform Memory Access time
multiprocessor) for shared address, distributed
memory MP
 Challenges of Parallel Processing

• First challenge is what % of program inherently

sequential
• Suppose 80X speedup from 100 processors. What
fraction of original program can be sequential?
a. 10%
b.5%
c. 1%
d.<1%
Challenges of Parallel Processing
• Second challenge is long latency to remote memory
• Suppose 32 CPU MP, 2GHz, 200 ns remote memory,
all local accesses hit memory hierarchy and base CPI
is 0.5. (Remote access = 200/0.5 = 400 clock cycles.)
• What is performance impact if 0.2% instructions
involve remote access?
a. 1.5X
b. 2.0X
c. 2.6X
 Challenges of Parallel Processing
1. Application parallelism  primarily via new
algorithms that have better parallel performance
2. Long remote latency impact  both by architect and
by the programmer
• For example, reduce frequency of remote accesses
either by
– Caching shared data (HW)
– Restructuring the data layout to make more
accesses local (SW)
 Symmetric Shared-Memory
Architectures
• From multiple boards on a shared bus to multiple
processors inside a single chip
• Caches both
– Private data are used by a single processor
– Shared data are used by multiple processors
• Caching shared data
 reduces latency to shared data, memory bandwidth
for shared data, and interconnect bandwidth
 cache coherence problem
 Example Cache Coherence
Problem
P1 P2 P3
u=? 3
u=?
4 5 $
$ $

u :5 u :5 u = 7

I/O devices
1
2
u :5
Memory

– Processors see different values for u after event 3

– With write back caches, value written back to memory depends on
happenstance of which cache flushes or writes back value when
• Processes accessing main memory may see very stale value
– Unacceptable for programming, and its frequent!
 Example
P1 P2
/*Assume initial value of A and flag is 0*/
A = 1; while (flag == 0); /*spin idly*/
flag = 1; print A;

• Intuition not guaranteed by coherence

• expect memory to respect order between accesses to different
locations issued by a given process
– to preserve orders among accesses to same location by different processes
• Coherence is not enough!
– pertains only to single location
P1 Pn

Conceptual
Picture Mem
Multiprocessor Cache Coherence
 Intuitive Memory Model
P

L1
 Reading an address
100:67
should return the last
L2
100:35
value written to that
address
Memory – Easy in uniprocessors,
except for I/O
Disk 100:34

• Too vague and simplistic; 2 issues

1. Coherence defines values returned by a read
2. Consistency determines when a written value will be returned
by a read
• Coherence defines behavior to same location, Consistency
defines behavior to other locations
 Defining Coherent Memory System
1. Preserve Program Order: A read by processor P to location X that follows a
write by P to X, with no writes of X by another processor occurring between
the write and the read by P, always returns the value written by P
2. Coherent view of memory: Read by a processor to location X that follows a
write by another processor to X returns the written value if the read and write
are sufficiently separated in time and no other writes to X occur between the
two accesses
3. Write serialization: 2 writes to same location by any 2 processors are seen in
the same order by all processors
– If not, a processor could keep value 1 since saw as last
write
– For example, if the values 1 and then 2 are written to a
location, processors can never read the value of the
location as 2 and then later read it as 1
 Write Consistency
• For now assume
1. A write does not complete (and allow the next write to
occur) until all processors have seen the effect of that
write
2. The processor does not change the order of any write
with respect to any other memory access
 if a processor writes location A followed by location B,
any processor that sees the new value of B must also
see the new value of A
• These restrictions allow the processor to reorder reads,
but forces the processor to finish writes in program
order
 Basic Schemes for Enforcing Coherence
• Program on multiple processors will normally have copies of the same
data in several caches
– Unlike I/O, where it is rare
• Rather than trying to avoid sharing in SW,
SMPs use a HW protocol to maintain coherent caches
– Migration and Replication key to performance of shared data
• Migration - data can be moved to a local cache and used there in a
transparent fashion
– Reduces both latency to access shared data that is allocated
remotely and bandwidth demand on the shared memory
• Replication – for shared data being simultaneously read, since caches
make a copy of data in local cache
– Reduces both latency of access and contention for read shared data
 2 Classes of Cache Coherence Protocols

1. Directory based — Sharing status of a block of physical

memory is kept in just one location, the directory
2. Snooping — Every cache with a copy of data also has a
copy of sharing status of block, but no centralized state
is kept
• All caches are accessible via some broadcast medium (a bus or switch)
• All cache controllers monitor or snoop on the medium to determine
whether or not they have a copy of a block that is requested on a bus
or switch access
 Snoopy Cache-Coherence
Protocols
State P1 Pn
Bus snoop
Address
Data
$ $

Cache-memory
I/O devices transaction
Mem

• Cache Controller “snoops” all transactions on the shared medium

(bus or switch)
– relevant transaction if for a block it contains
– take action to ensure coherence
• invalidate, update, or supply value
– depends on state of the block and the protocol
• Either get exclusive access before write via write invalidate or
update all copies on write
Example: Write-thru Invalidate
P1 P2 P3
u=? 3
u=?
4 5 $
$ $

u :5 u :5 u = 7

I/O devices
1
2
u :5 u=7
Memory

• Must invalidate before step 3

• Write update uses more broadcast medium BW
 all recent MPUs use write invalidate
 Architectural Building Blocks
• Cache block state transition diagram
– FSM specifying how disposition of block changes
• invalid, valid, dirty
• Broadcast Medium Transactions (e.g., bus)
– Fundamental system design abstraction
– Logically single set of wires connect several devices
– Protocol: arbitration, command/addr, data
 Every device observes every transaction
• Broadcast medium enforces serialization of read or write
accesses  Write serialization
– 1st processor to get medium invalidates others copies
– Implies cannot complete write until it obtains bus
– All coherence schemes require serializing accesses to same
cache block
• Also need to find up-to-date copy of cache block
 Locate updated copy of data
• Write-through: get updated copy from memory
– Write through simpler if enough memory BW
• Write-back harder
– Most recent copy can be in a cache
• Can use same snooping mechanism
1. Snoop every address placed on the bus
2. If a processor has dirty copy of requested cache block, it
provides it in response to a read request and aborts the
memory access
– Complexity from retrieving cache block from a processor
cache, which can take longer than retrieving it from memory

• Write-back needs lower memory bandwidth

 Support larger numbers of faster processors
 Most multiprocessors use write-back
 Cache Resources for WB Snooping
• Normal cache tags can be used for snooping
• Valid bit per block makes invalidation easy
• Read misses easy since rely on snooping
• Writes  Need to know whether any other copies of the block are
cached
– No other copies  No need to place write on bus for WB
– Other copies  Need to place invalidate on bus
 Cache Resources for WB Snooping

• To track whether a cache block is shared, add

extra state bit associated with each cache block,
like valid bit and dirty bit
– Write to Shared block  Need to place invalidate on bus and
mark cache block as private (if an option)
– No further invalidations will be sent for that block
– This processor called owner of cache block
– Owner then changes state from shared to unshared (or exclusive)
Cache behavior in response to bus
• Every bus transaction must check the cache-address tags
– could potentially interfere with processor cache accesses
• A way to reduce interference is to duplicate tags
– One set for caches access, one set for bus accesses
• Another way to reduce interference is to use L2 tags
– Since L2 less heavily used than L1
 Every entry in L1 cache must be present in the L2 cache, called
the inclusion property
– If Snoop gets a hit in L2 cache, then it must arbitrate for the L1
cache to update the state and possibly retrieve the data, which
usually requires a stall of the processor
 Example Protocol
• Snooping coherence protocol is usually implemented by
incorporating a finite-state controller in each node
• Logically, think of a separate controller associated with each
cache block
– That is, snooping operations or cache requests for different
blocks can proceed independently
• In implementations, a single controller allows multiple
operations to distinct blocks to proceed in interleaved
fashion
– that is, one operation may be initiated before another is
completed, even through only one cache access or one bus access
is allowed at time
 Write-through Invalidate Protocol
PrRd/ --
• 2 states per block in each cache PrWr / BusWr
– as in uniprocessor V
– state of a block is a p-vector of states BusWr / -
– Hardware state bits associated with
blocks that are in the cache PrRd / BusRd
– other blocks can be seen as being in
I
invalid (not-present) state in that cache
• Writes invalidate all other cache PrWr / BusWr
copies
– can have multiple simultaneous readersState Tag Data State Tag Data
of block,but write invalidates them
P1 Pn
PrRd: Processor Read
PrWr: Processor Write $ $
BusRd: Bus Read Bus
BusWr: Bus Write Mem I/O devices
 Is 2-state Protocol Coherent?
• Processor only observes state of memory system by issuing memory
operations
• Assume bus transactions and memory operations are atomic and a one-
level cache
– all phases of one bus transaction complete before next one starts
– processor waits for memory operation to complete before issuing next
– with one-level cache, assume invalidations applied during bus transaction
• All writes go to bus + atomicity
– Writes serialized by order in which they appear on bus (bus order)
=> invalidations applied to caches in bus order
• How to insert reads in this order?
– Important since processors see writes through reads, so determines
whether write serialization is satisfied
– But read hits may happen independently and do not appear on bus or enter
directly in bus order

• Let’s understand other ordering issues

 Ordering
P0: R R R W R R

P1: R R R R R W

P2: R R R R R R

• Writes establish a partial order

• Doesn’t constrain ordering of reads, though
shared-medium (bus) will order read misses too
– any order among reads between writes is fine,
as long as in program order
CSCI 330 – Computer Architecture

Summary
 And in Conclusion …
• “End” of uniprocessors speedup => Multiprocessors
• Parallelism challenges: % parallalizable, long latency to
remote memory
• Centralized vs. distributed memory
– Small MP vs. lower latency, larger BW for Larger MP
• Message Passing vs. Shared Address
– Uniform access time vs. Non-uniform access time
• Snooping cache over shared medium for smaller MP
by invalidating other cached copies on write
• Sharing cached data  Coherence (values returned
by a read), Consistency (when a written value will be
returned by a read)
• Shared medium serializes writes
 Write consistency
 Next Time…

More Multiprocessors