Microprocessor Systems

Spring 2024

Dr Jameel Malik
[email protected]
Office: A-311 SEECS

1
 Outline
• Instructor

• Course Learning Outcomes

• Course Books

• Introduction to the Microprocessor Systems

2
 Instructor: Dr. Jameel Malik
• PhD from TU Kaiserslautern, Germany
– Area of expertise
• Computer Vision and Artificial Intelligence

• Joined NUST-SEECS in Fall 2011 as Lecturer

– Subjects
• Digital Logic Design, Computer Organization and Assembly
Language, Microprocessor Systems, Embedded Systems, Advanced
Computer Vision.

• Office hours: through email

3
 Course Learning Outcomes (CLOs)
 Understand the basic concepts of
micro-controller/microprocessor, memory interfacing and
interrupts. (C2 Level)
 Use Assembly and C language for
micro-processor/microcontrollers. (C3 Level)
 Conduct experiments as well as analyze and interpret
experimental data. (P4 Level)
 Design and implement real time systems using 8051, AVR, ARM
Cortex or similar micro-controllers. (P4 Level)
 Exhibit good professional and ethical behavior. Adhere to lab
safety rules. (A3 Level)
 Function effectively both individually and as a member of a team.
(A4 Level) 4
 Course Books
• Text Books
– The AVR Microcontroller and Embedded Systems: Using
Assembly and C by Mazidi et al., Prentice Hall

– Computer Organization and Design The Hardware/Software

Interface (RISC-V Edition) by Hennessy and Patterson,
Morgan Kaufmann

– The Intel Microprocessors, 8086/8088, 80XXX & Pentium

series Architecture, Programming and Interfacing by Barry
B. Brey, 8 th edition, published by Prentice Hall.

5
 Course Books
• Reference Books
– Computer Organization & Architecture by William Stallings.
– 8051 Microcontroller by Machenzie.
– The 8051 Microcontroller and Embedded Systems using
Assembly and C by Mazidi.
– Assembly Language for x86 Processors by Kip R. Irvine,
6th edition.
– Some Assembly Required; Assembly language programming
with the AVR microcontroller by Margush, CRC

6
Where this course fits in

7
Computers Now

8
 Microprocessor-based Computer System

Figure: Block diagram of microprocessor-based computer system

-- The Intel Microprocessors, 8086/8088, 80XXX & Pentium series - Architecture, 9

Programming and Interfacing by Barry B. Brey, 8th edition.
 The Microprocessor
• Among various, some tasks of the microprocessor are
– Controlling all other parts of the machine and sending
timing signals.
– Transferring data between memory and I/O devices
– Fetching data and instructions from memory
– Decoding instruction
– Performing arithmetical and logical operations
– Executing programs stored in memory
– Performing communication among the I/O devices etc.

-- The Intel Microprocessors, 8086/8088, 80XXX & Pentium series - Architecture, 10

Programming and Interfacing by Barry B. Brey, 8th edition.
 Computer Buses
• A bus is a common group of wires that interconnect
components in a computer system.
– Three types: Address bus, Data bus, Control bus

Figure: Address, Data and Control bus structure

-- The Intel Microprocessors, 8086/8088, 80XXX & Pentium series - Architecture, 11
Programming and Interfacing by Barry B. Brey, 8th edition.
 Computer Buses
• Address Bus
– Requests a memory
location or I/O.
• Data Bus
– Transfers data
between
microprocessor and
memory and I/O. Figure: Address, Data and
Control bus structure
• Control Bus
– Requests reading or
writing of data.

-- The Intel Microprocessors, 8086/8088, 80XXX & Pentium series - Architecture, 12

Programming and Interfacing by Barry B. Brey, 8th edition.
 Basic Architecture of Processor

Processor
Control unit Datapath

Control
ALU
/Status
Controller
Registers
PC IR

I/O

Memory

PC stands for “Program Counter” ALU stands for “Arithmetic and 13

IR stand for “Instruction Register” Logic Unit”
 Datapath Operations
• Load
Processor
– Read memory location Control unit Datapath
into register
ALU
• ALU operation Controller Control +1
/Status
– Input certain registers
through ALU, store Registers
back in register
• Store 10 11
– Write register to PC IR

memory location
I/O
Memory
...
10
11
...
14
 Control Unit
• Control unit: configures the datapath
operations Processor
– Sequence of desired operations Control unit Datapath
(“instructions”) stored in memory –
“program” ALU
Controller
• Instruction cycle – broken into Control
/Status
several sub-operations, each one
clock cycle, e.g.: Registers
– Fetch: Get next instruction into IR
– Decode: Determine what the
instruction means
– Fetch operands: Move data from PC IR R0 R1
memory to datapath register
– Execute: Move data through the
ALU I/O
– Store results: Write data from
100 load R0, M[500] Memory
...
register to memory 500 10
101 inc R1, R0
102 store M[501], R1
501
...
15
 Control Unit Sub-Operations

• Fetch Processor

– Get next instruction Control unit Datapath

ALU
into IR Controller Control
– PC: program /Status

counter, always Registers

points to next
instruction
PC100 IR R0 R1
– IR: holds the load R0, M[500]

fetched instruction
I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
16
 Control Unit Sub-Operations

• Decode Processor

– Determine what the Control unit Datapath

ALU
instruction means Controller Control
/Status

Registers

PC100 IR R0 R1
load R0, M[500]

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
17
 Control Unit Sub-Operations

• Fetch operands Processor

– Move data from Control unit Datapath

ALU
memory to datapath Controller Control
register /Status

Registers

10
PC100 IR R0 R1
load R0, M[500]

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
18
 Control Unit Sub-Operations

• Execute Processor

– Move data through Control unit Datapath

ALU
the ALU Controller Control
– This particular /Status

instruction does Registers

nothing during this

sub-operation 10
PC100 IR R0 R1
load R0, M[500]

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
19
 Control Unit Sub-Operations

• Store results Processor

– Write data from Control unit Datapath

ALU
register to memory Controller Control
– This particular /Status

instruction does Registers

nothing during this

sub-operation 10
PC100 IR R0 R1
load R0, M[500]

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
20
 Instruction Cycle

PC=100 Processor

FetchDecode Fetch Exec. Store Control unit Datapath

ops results ALU
clk Controller Control
/Status

Registers

10
PC 100 IR R0 R1
load R0, M[500]

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
21
 Instruction Cycle

PC=100 Processor

FetchDecode Fetch Exec. Store Control unit Datapath

ops results ALU
clk Controller Control +1
/Status

PC=101
Registers
FetchDecode Fetch Exec. Store
ops results
clk
10 11
PC 101 IR R0 R1
inc R1, R0

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
22
 Instruction Cycles

PC=100 Processor

FetchDecode Fetch Exec. Store Control unit Datapath

ops results ALU
clk Controller Control
/Status

PC=101
Registers
FetchDecode Fetch Exec. Store
ops results
clk
10 11
PC 102 IR R0 R1
store M[501], R1

PC=102
FetchDecode Fetch Exec. Store I/O
ops results ...
100 load R0, M[500] Memory
clk 500 10
101 inc R1, R0 501 11
102 store M[501], R1 ...
23
 Intel’s Brief Historical Background
• The Microprocessor Age
– In 1971, the world’s 1st microprocessor, the Intel 4004
microprocessor was introduced
• 4-bit microprocessor (data bus)
• 45 instructions
• Addresses only 4096 x 4bit memory
• 50KIPs (kilo-instructions per second)

• Still used in microwave ovens,

small control systems, calculators …

-- The Intel Microprocessors, 8086/8088, 80XXX & Pentium series - Architecture, 24

Programming and Interfacing by Barry B. Brey, 8th edition.
 Intel’s Brief Historical Background
• Intel´s Pentium Microprocessors
– Introduced in 1993
– 16K byte Cache Memory
– 4G Bytes of Memory Addressing
– Speed150 MIPs
– Data bus width increased to 64-bit

• Later Pentium versions are up-gradations of above

specifications (Table 1-2 of the reference below)

• Multiple Core Processors – use multithreading for

faster program execution
-- The Intel Microprocessors, 8086/8088, 80XXX & Pentium series - Architecture, 25
Programming and Interfacing by Barry B. Brey, 8th edition.
 Latest Intel’s Processors
• Core i3, i5, i7 and i9 (upto 20 cores, 16 threads,
processor base frequency 3.60 GHz)
• GPU (Graphics Processing Unit) based gaming
computers
– Nvidia GTX series
• GeForce GTX 1660 Ti (2019)
– Nvidia RTX series Intel Core i7
• GeForce RTX 4090 (Oct. 2022) in 1599 dollars 8 cores
– 24 GB GPU memory
– 76.3 billion transistors
– CPUs to pair with can be Intel Core i5, i9, AMD Ryzen 5, 9

https://en.wikipedia.org/wiki/List_of_Nvidia_graphics_processing_units 26
 Microprocessor Chips

Intel Core i7 IBM Cell BE IBM POWER7

AMD Barcelona 8 cores 8+1 cores 8 cores
4 cores

Nvidia Fermi Intel SCC Tilera TILE Gx

Sun Niagara II 448 “cores” 48 cores, networked 100 cores, networked
8 cores

27
Microprocessor Chips

What do you observe?

28
 Brief Historical Background
• Programming Advancements
– Machine Language - binary codes (e.g., 0100 0111 for
addition) stored in computer memory.

– Assembly Language - Instructions (mnemonic codes such as

ADD for addition) stored in computer memory.

– FORTRAN - allows programmers to use formulas

– COBOL, BASIC, C/C++, JAVA, Python etc.

-- The Intel Microprocessors, 8086/8088, 80XXX & Pentium series - Architecture, 29

Programming and Interfacing by Barry B. Brey, 8th edition.
 Moore’s Law

https://en.wikipedia.org/wiki/List_of_Nvidia_graphics_processing_units 30