CS 5513 Computer Architecture

Lecture 5 – Instruction Level

Parallelism
Outline
• ILP
• Compiler techniques to increase ILP
• Loop Unrolling
• Static Branch Prediction
• Dynamic Branch Prediction
• Overcoming Data Hazards with Dynamic
Scheduling
• (Start) Tomasulo Algorithm
• Conclusion
Recall from Pipelining Review

• Pipeline CPI = Ideal pipeline CPI + Structural

Stalls + Data Hazard Stalls + Control Stalls
– Ideal pipeline CPI: measure of the maximum
performance attainable by the implementation
– Structural hazards: HW cannot support this
combination of instructions
– Data hazards: Instruction depends on result of prior
instruction still in the pipeline
– Control hazards: Caused by delay between the fetching
of instructions and decisions about changes in control
flow (branches and jumps)
Instruction Level Parallelism
• Instruction-Level Parallelism (ILP): overlap the
execution of instructions to improve
performance
• 2 approaches to exploit ILP:
1) Rely on hardware to help discover and exploit the parallelism
dynamically (e.g., Pentium 4, AMD Opteron, IBM Power) , and
2) Rely on software technology to find parallelism, statically at
compile-time (e.g., Itanium 2)
• Next 4 lectures on this topic
Instruction-Level Parallelism (ILP)
• Basic Block (BB) ILP is quite small
– BB: a straight-line code sequence with no branches in
except to the entry and no branches out except at the exit
– average dynamic branch frequency 15% to 25%
=> 4 to 7 instructions execute between a pair of branches
– Plus instructions in BB likely to depend on each other
• To obtain substantial performance
enhancements, we must exploit ILP across
multiple basic blocks
• Simplest: loop-level parallelism to exploit
parallelism among iterations of a loop. E.g.,
for (i=1; i<=1000; i=i+1)
x[i] = x[i] + y[i];
Loop-Level Parallelism
• Exploit loop-level parallelism to parallelism by
“unrolling loop” either by
1. dynamic via branch prediction or
2. static via loop unrolling by compiler
(Another way is vectors)
• Determining instruction dependence is critical to
Loop Level Parallelism
• If 2 instructions are
– parallel, they can execute simultaneously in a
pipeline of arbitrary depth without causing any
stalls (assuming no structural hazards)
– dependent, they are not parallel and must be
executed in order, although they may often be
partially overlapped
 Data Dependence and Hazards
• InstrJ is data dependent (aka true dependence) on
InstrI:
1. InstrJ tries to read operand before InstrI writes it
I: add r1,r2,r3
J: sub r4,r1,r3
2. or InstrJ is data dependent on InstrK which is dependent on InstrI
• If two instructions are data dependent, they cannot
execute simultaneously or be completely overlapped
• Data dependence in instruction sequence
 data dependence in source code  effect of
original data dependence must be preserved
• If data dependence caused a hazard in pipeline,
called a Read After Write (RAW) hazard
 ILP and Data Dependencies,Hazards
• HW/SW must preserve program order:
order instructions would execute in if executed
sequentially as determined by original source program
– Dependences are a property of programs
• Presence of dependence indicates potential for a
hazard, but actual hazard and length of any stall is
property of the pipeline
• Importance of the data dependencies
1) indicates the possibility of a hazard
2) determines order in which results must be calculated
3) sets an upper bound on how much parallelism can possibly be
exploited
• HW/SW goal: exploit parallelism by preserving program
order only where it affects the outcome of the program
Name Dependence #1: Anti-dependence

• Name dependence: when 2 instructions use same

register or memory location, called a name, but no
flow of data between the instructions associated
with that name; 2 versions of name dependence
• InstrJ writes operand before InstrI reads it
I: sub r4,r1,r3
J: add r1,r2,r3
K: mul r6,r1,r7
Called an “anti-dependence” by compiler writers.
This results from reuse of the name “r1”
• If anti-dependence caused a hazard in the pipeline,
called a Write After Read (WAR) hazard
Name Dependence #2: Output dependence
• InstrJ writes operand before InstrI writes it.
I: sub r1,r4,r3
J: add r1,r2,r3
K: mul r6,r1,r7
• Called an “output dependence” by compiler writers
This also results from the reuse of name “r1”
• If anti-dependence caused a hazard in the pipeline,
called a Write After Write (WAW) hazard
• Instructions involved in a name dependence can
execute simultaneously if name used in instructions is
changed so instructions do not conflict
– Register renaming resolves name dependence for regs
– Either by compiler or by HW
Control Dependencies

• Every instruction is control dependent on

some set of branches, and, in general, these
control dependencies must be preserved to
preserve program order
if p1 {
S1;
};
if p2 {
S2;
}
• S1 is control dependent on p1, and S2 is
control dependent on p2 but not on p1.
Control Dependence Ignored

• Control dependence need not be

preserved
– willing to execute instructions that should not have been
executed, thereby violating the control dependences, if
can do so without affecting correctness of the program
• Instead, 2 properties critical to program
correctness are
1) exception behavior and
2) data flow
Exception Behavior
• Preserving exception behavior
 any changes in instruction execution order
must not change how exceptions are raised in
program
( no new exceptions)
• Example:
DADDU R2,R3,R4
BEQZ R2,L1
LW R1,0(R2)
L1:
– (Assume branches not delayed)
• Problem with moving LW before BEQZ?
Data Flow

• Data flow: actual flow of data values among

instructions that produce results and those that
consume them
– branches make flow dynamic, determine which instruction is
supplier of data
• Example:
DADDU R1,R2,R3
BEQZ R4,L
DSUBU R1,R5,R6
L: …
OR R7,R1,R8
• OR depends on DADDU or DSUBU?
Must preserve data flow on execution
Outline
• ILP
• Compiler techniques to increase ILP
• Loop Unrolling
• Static Branch Prediction
• Dynamic Branch Prediction
• Overcoming Data Hazards with Dynamic
Scheduling
• (Start) Tomasulo Algorithm
• Conclusion
Software Techniques - Example

• This code, add a scalar to a vector:

for (i=1000; i>0; i=i–1)
x[i] = x[i] + s;
• Assume following latencies for all examples
– Ignore delayed branch in these examples
FP Loop: Where are the Hazards?

The straightforward RISC-V code, not scheduled for the

pipeline, looks like this:

Loop: fld f0, 0(x1) //f0=array element

fadd.d f4, f0, f2 //add scalar in f2
fsd f4, 0(x1) //store result
addi x1, x1, 8 //decrement pointer
//8 bytes (per DW)
bne x1, x2, Loop //branch x16¼x2
 FP Loop Showing Stalls
Show how the loop would look on RISC-V, both scheduled and unscheduled,
including any stalls or idle clock cycles. Schedule for delays from floating-point
operations.
Show our loop unrolled so that there are four copies of the loop body,
assuming x1 x2 (that is, the size of the array) is initially a multiple of 32,
which means that the number of loop iterations is a multiple of 4. Eliminate
any obviously redundant computations and do not reuse any of the registers.
 Unroll Loop Four Times
(straightforward way)
1 cycle stall
1 Loop:L.D F0,0(R1) Rewrite loop to
3 ADD.D F4,F0,F2 2 cycles stall
minimize stalls?
6 S.D 0(R1),F4 ;drop DSUBUI & BNEZ
7 L.D F6,-8(R1)
9 ADD.D F8,F6,F2
12 S.D -8(R1),F8 ;drop DSUBUI & BNEZ
13 L.D F10,-16(R1)
15 ADD.D F12,F10,F2
18 S.D -16(R1),F12 ;drop DSUBUI & BNEZ
19 L.D F14,-24(R1)
21 ADD.D F16,F14,F2
24 S.D -24(R1),F16
25 DADDUI R1,R1,#-32 ;alter to 4*8
26 BNEZ R1,LOOP

27 clock cycles, or 6.75 per iteration

(Assumes R1 is multiple of 4)
Unrolled Loop Detail
• Do not usually know upper bound of loop
• Suppose it is n, and we would like to unroll the
loop to make k copies of the body
• Instead of a single unrolled loop, we generate a
pair of consecutive loops:
– 1st executes (n mod k) times and has a body that is the
original loop
– 2nd is the unrolled body surrounded by an outer loop that
iterates (n/k) times
• For large values of n, most of the execution time
will be spent in the unrolled loop
Unrolled Loop That Minimizes Stalls
1 Loop:L.D F0,0(R1)
2 L.D F6,-8(R1)
3 L.D F10,-16(R1)
4 L.D F14,-24(R1)
5 ADD.D F4,F0,F2
6 ADD.D F8,F6,F2
7 ADD.D F12,F10,F2
8 ADD.D F16,F14,F2
9 S.D 0(R1),F4
10 S.D -8(R1),F8
11 S.D -16(R1),F12
12 DSUBUI R1,R1,#32
13 S.D 8(R1),F16 ; 8-32 = -24
14 BNEZ R1,LOOP
14 clock cycles, or 3.5 per iteration
5 Loop Unrolling Decisions
• Requires understanding how one instruction depends on
another and how the instructions can be changed or
reordered given the dependences:
1. Determine loop unrolling useful by finding that loop
iterations were independent (except for maintenance code)
2. Use different registers to avoid unnecessary constraints
forced by using same registers for different computations
3. Eliminate the extra test and branch instructions and adjust
the loop termination and iteration code
4. Determine that loads and stores in unrolled loop can be
interchanged by observing that loads and stores from
different iterations are independent
• Transformation requires analyzing memory addresses and finding
that they do not refer to the same address
5. Schedule the code, preserving any dependences needed to
yield the same result as the original code
3 Limits to Loop Unrolling
1. Decrease in amount of overhead amortized with
each extra unrolling
• Amdahl’s Law
2. Growth in code size
• For larger loops, concern it increases the instruction cache
miss rate
3. Register pressure: potential shortfall in
registers created by aggressive unrolling and
scheduling
• If not be possible to allocate all live values to registers, may
lose some or all of its advantage
• Loop unrolling reduces impact of branches on
pipeline; another way is branch prediction
Static Branch Prediction
• Previous lecture showed scheduling code around
delayed branch
• To reorder code around branches, need to predict
branch statically when compile
• Simplest scheme is to predict a branch as taken
– Average misprediction = untaken branch frequency = 34% SPEC
25% 22%
• More accurate
Misprediction Rate

20% 18%
scheme predicts
15%
branches using 15% 12% 11% 12%
profile 10%
9%
information 10%
6%
collected from 4%
5%
earlier runs, and
modify 0%
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Dynamic Branch Prediction
• Why does prediction work?
– Underlying algorithm has regularities
– Data that is being operated on has regularities
– Instruction sequence has redundancies that are artifacts of
way that humans/compilers think about problems
• Is dynamic branch prediction better than static
branch prediction?
– Almost always yes
– There are a small number of important branches in programs
which have dynamic behavior
 Dynamic Branch Prediction

• Performance = ƒ(accuracy, cost of misprediction)

• Branch History Table: Lower bits of PC address index
table of 1-bit values
– Says whether or not branch taken last time
– No address check
• Problem: in a loop, 1-bit BHT will cause two
mispredictions (avg is 9 iterations before exit):
– End of loop case, when it exits instead of looping as before
– First time through loop on next time through code, when it predicts
exit instead of looping
 Dynamic Branch Prediction

• Solution: 2-bit scheme where change prediction only if get misprediction

twice

NT
Predict Taken Predict Taken
T
• Red: stop, not taken T NT NT
• Green:Predict
go, takenNot Predict Not
T Taken
Takento decision making process
• Adds hysteresis

NT
 BHT Accuracy
• Mispredict because either:
– Wrong guess for that branch
– Got branch history of wrong branch when index the table
• 4096 entry table:

20% 18%
18%
Misprediction Rate

16%
14% 12%
12% 10%
10% 9% 9% 9%
8%
6% 5% 5%
4%
2% 1%
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Correlated Branch Prediction
• Idea: record m most recently executed branches
as taken or not taken, and use that pattern to
select the proper n-bit branch history table

• In general, (m,n) predictor means record last m

branches to select between 2m history tables,
each with n-bit counters
– Thus, old 2-bit BHT is a (0,2) predictor

• Global Branch History: m-bit shift register

keeping T/NT status of last m branches.
Correlating Branches

(2,2) predictor Branch address

– Behavior of recent 4
branches selects 2-bits per branch predictor
between four
predictions of next
branch, updating just Prediction
that prediction

2-bit global branch history

 Accuracy of Different Schemes

20%

18% 4096 Entries 2-bit BHT

Frequency of Mispredictions

16% Unlimited Entries 2-bit BHT

14% 1024 Entries (2,2) BHT
12%
11%
10%

8%
6% 6% 6%
6%
5% 5%
4%
4%

2%
1% 1%
0%
0%
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4,096 entries: 2-bits per entry Unlimited entries: 2-bits/entry 1,024 entries (2,2)
Tournament Predictors

• Multilevel branch predictor

• Use n-bit saturating counter to choose between
predictors
• Usual choice between global and local predictors
Tournament Predictors

Tournament predictor using, say, 4K 2-bit counters

indexed by local branch address. Chooses
between:
• Global predictor
– 4K entries index by history of last 12 branches (212 = 4K)
– Each entry is a standard 2-bit predictor

• Local predictor
– Local history table: 1024 10-bit entries recording last 10
branches, index by branch address
– The pattern of the last 10 occurrences of that particular branch
used to index table of 1K entries with 3-bit saturating counters
 Comparing Predictors (Fig. 2.8)
• Advantage of tournament predictor is ability to
select the right predictor for a particular branch
– Particularly crucial for integer benchmarks.
– A typical tournament predictor will select the global predictor
almost 40% of the time for the SPEC integer benchmarks and
less than 15% of the time for the SPEC FP benchmarks
Pentium 4 Misprediction Rate
(per 1000 instructions, not per branch)
14
13
6% misprediction rate per branch SPECint
13
12 (19% of INT instructions are branch)
12
Branch mispredictions per 1000 Instructions

11
2% misprediction rate per branch SPECfp
11
(5% of FP instructions are branch)
10

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Branch Target Buffers (BTB)

• Branch target calculation is costly and stalls the

instruction fetch.
• BTB stores PCs the same way as caches
• The PC of a branch is sent to the BTB
• When a match is found the corresponding
Predicted PC is returned
• If the branch was predicted taken, instruction
fetch continues at the returned predicted PC
Branch Target Buffers
Dynamic Branch Prediction Summary
• Prediction becoming important part of execution
• Branch History Table: 2 bits for loop accuracy
• Correlation: Recently executed branches correlated
with next branch
– Either different branches (GA)
– Or different executions of same branches (PA)
• Tournament predictors take insight to next level, by
using multiple predictors
– usually one based on global information and one based on local
information, and combining them with a selector
– In 2006, tournament predictors using  30K bits are in processors
like the Power5 and Pentium 4
• Branch Target Buffer: include branch address &
prediction
Outline
• ILP
• Compiler techniques to increase ILP
• Loop Unrolling
• Static Branch Prediction
• Dynamic Branch Prediction
• Overcoming Data Hazards with Dynamic
Scheduling
• (Start) Tomasulo Algorithm
• Conclusion
 Advantages of Dynamic Scheduling
• Dynamic scheduling - hardware rearranges the instruction execution to
reduce stalls while maintaining data flow and exception behavior

• It handles cases when dependences unknown at compile time

– it allows the processor to tolerate unpredictable delays such as cache misses, by
executing other code while waiting for the miss to resolve

• It allows code that compiled for one pipeline to run efficiently on a

different pipeline

• It simplifies the compiler

• Hardware speculation, a technique with significant performance

advantages.
 HW Schemes: Instruction Parallelism

• Key idea: Allow instructions behind stall to proceed

DIVD F0,F2,F4
ADDD F10,F0,F8
SUBD F12,F8,F14

• Enables out-of-order execution and allows out-of-order completion (e.g.,

SUBD)
– In a dynamically scheduled pipeline, all instructions still pass through issue stage in
order (in-order issue)

• Will distinguish when an instruction begins execution and when it

completes execution; between 2 times, the instruction is in execution

• Note: Dynamic execution creates WAR and WAW hazards and makes
exceptions harder
Out-of-order execution introduces the possibility of WAR and WAW hazards, which do not
exist in the five-stage integer pipeline and its logical extension to an in-order floating-point
pipeline.
Consider the following MIPS floating-point code sequence:

DIV.D F0,F2,F4
ADD.D F6,F0,F8
SUB.D F8,F10,F14
MUL.D F6,F10,F8

There is an antidependence between the ADD.D and the SUB.D, and if the pipeline executes
the SUB.D before the ADD.D (which is waiting for the DIV.D), it will violate the
antidependence, yielding a WAR hazard. Likewise, to avoid violating output dependences,
such as the write of F6 by MUL.D, WAW hazards must be handled.
 Dynamic Scheduling Step 1

• Simple pipeline had 1 stage to check both structural and data

hazards: Instruction Decode (ID), also called Instruction Issue

• Split the ID pipe stage of simple 5-stage pipeline into 2 stages:

 Issue—Decode instructions, check for structural hazards

 Read operands—Wait until no data hazards, then read operands

 Tomasulo Algorithm

• Control & buffers distributed with Function Units (FU)

– FU buffers called “reservation stations”; have pending operands

• Registers in instructions replaced by values or pointers to reservation stations(RS);

called register renaming ;
– Renaming avoids WAR, WAW hazards

– More reservation stations than registers, so can do optimizations compilers can’t

• Results to FU from RS, not through registers, over Common Data Bus that
broadcasts results to all FUs
– Avoids RAW hazards by executing an instruction only when its operands are available

• Load and Stores treated as FUs with RSs as well

• Integer instructions can go past branches (predict taken), allowing FP ops beyond
basic block in FP queue
 Tomasulo Organization
From Mem FP Op FP Registers
Queue
Load Buffers
Load1
Load2
Load3
Load4
Load5 Store
Load6
Buffers

Add1
Add2 Mult1
Add3 Mult2

Reservation To Mem
Stations
FP
FP adders
adders FP
FP multipliers
multipliers

Common Data Bus (CDB)

Reservation Station Components
Op: Operation to perform in the unit (e.g., + or –)
Vj, Vk: Value of Source operands
– Store buffers has V field, result to be stored
Qj, Qk: Reservation stations producing source registers (value to
be written)
– Note: Qj,Qk=0 => ready
– Store buffers only have Qi for RS producing result
A: used to hold the information for the memory address calculation for
a load or store.
Busy: Indicates reservation station or FU is busy

Register result status—Indicates which functional unit will write

each register, if one exists. Blank when no pending instructions
that will write that register.
Three Stages of Tomasulo Algorithm

1. Issue—get instruction from FP Op Queue

If reservation station free (no structural hazard),
control issues instr & sends operands (renames registers).
2. Execute—operate on operands (EX)
When both operands ready then execute;
if not ready, watch Common Data Bus for result
3. Write result—finish execution (WB)
Write on Common Data Bus to all awaiting units;
mark reservation station available
• Normal data bus: data + destination (“go to” bus)
• Common data bus: data + source (“come from” bus)
– 64 bits of data + 4 bits of Functional Unit source address
– Write if matches expected Functional Unit (produces result)
– Does the broadcast
• Example speed:
3 clocks for Fl .pt. +,-; 10 for * ; 40 clks for /
 Tomasulo Example
Instruction stream
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 Load1 No
LD F2 45+ R3 Load2 No
MULTD F0 F2 F4 Load3 No
SUBD F8 F6 F2
DIVD F10 F0 F6
ADDD F6 F8 F2 3 Load/Buffers
Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
FU count Add2 No
3 FP Adder R.S.
Add3 No
down 2 FP Mult R.S.
Mult1 No
Mult2 No

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
0 FU

Clock cycle
counter
 Tomasulo Example Cycle 1
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 Load1 Yes 34+R2
LD F2 45+ R3 Load2 No
MULTD F0 F2 F4 Load3 No
SUBD F8 F6 F2
DIVD F10 F0 F6
ADDD F6 F8 F2

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
Add2 No
Add3 No
Mult1 No
Mult2 No

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
1 FU Load1
 Tomasulo Example Cycle 2
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 Load1 Yes 34+R2
LD F2 45+ R3 2 Load2 Yes 45+R3
MULTD F0 F2 F4 Load3 No
SUBD F8 F6 F2
DIVD F10 F0 F6
ADDD F6 F8 F2

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
Add2 No
Add3 No
Mult1 No
Mult2 No

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
2 FU Load2 Load1

Note: Can have multiple loads outstanding

 Tomasulo Example Cycle 3
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 Load1 Yes 34+R2
LD F2 45+ R3 2 Load2 Yes 45+R3
MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2
DIVD F10 F0 F6
ADDD F6 F8 F2

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
Add2 No
Add3 No
Mult1 Yes MULTD R(F4) Load2
Mult2 No

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
3 FU Mult1 Load2 Load1

• Note: registers names are removed (“renamed”) in Reservation

Stations; MULT issued
• Load1 completing; what is waiting for Load1?
 Tomasulo Example Cycle 4
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 Load2 Yes 45+R3
MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4
DIVD F10 F0 F6
ADDD F6 F8 F2

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 Yes SUBD M(A1) Load2
Add2 No
Add3 No
Mult1 Yes MULTD R(F4) Load2
Mult2 No

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
4 FU Mult1 Load2 M(A1) Add1

• Load2 completing; what is waiting for Load2?

 Tomasulo Example Cycle 5
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4
DIVD F10 F0 F6 5
ADDD F6 F8 F2

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
2 Add1 Yes SUBD M(A1) M(A2)
Add2 No
Add3 No
10 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
5 FU Mult1 M(A2) M(A1) Add1 Mult2

• Timer starts down for Add1, Mult1

 Tomasulo Example Cycle 6
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4
DIVD F10 F0 F6 5
ADDD F6 F8 F2 6

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
1 Add1 Yes SUBD M(A1) M(A2)
Add2 Yes ADDD M(A2) Add1
Add3 No
9 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
6 FU Mult1 M(A2) Add2 Add1 Mult2

• Issue ADDD here despite name dependency on F6?

 Tomasulo Example Cycle 7
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4 7
DIVD F10 F0 F6 5
ADDD F6 F8 F2 6

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
0 Add1 Yes SUBD M(A1) M(A2)
Add2 Yes ADDD M(A2) Add1
Add3 No
8 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
7 FU Mult1 M(A2) Add2 Add1 Mult2

• Add1 (SUBD) completing; what is waiting for it?

 Tomasulo Example Cycle 8
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5
ADDD F6 F8 F2 6

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
2 Add2 Yes ADDD (M-M) M(A2)
Add3 No
7 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
8 FU Mult1 M(A2) Add2 (M-M) Mult2
 Tomasulo Example Cycle 9
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5
ADDD F6 F8 F2 6

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
1 Add2 Yes ADDD (M-M) M(A2)
Add3 No
6 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
9 FU Mult1 M(A2) Add2 (M-M) Mult2
 Tomasulo Example Cycle 10
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5
ADDD F6 F8 F2 6 10

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
0 Add2 Yes ADDD (M-M) M(A2)
Add3 No
5 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
10 FU Mult1 M(A2) Add2 (M-M) Mult2

• Add2 (ADDD) completing; what is waiting for it?

 Tomasulo Example Cycle 11
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5
ADDD F6 F8 F2 6 10 11

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
Add2 No
Add3 No
4 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
11 FU Mult1 M(A2) (M-M+M)(M-M) Mult2

• Write result of ADDD here?

• All quick instructions complete in this cycle!
 Tomasulo Example Cycle 12
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5
ADDD F6 F8 F2 6 10 11

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
Add2 No
Add3 No
3 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
12 FU Mult1 M(A2) (M-M+M)(M-M) Mult2
 Tomasulo Example Cycle 13
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5
ADDD F6 F8 F2 6 10 11

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
Add2 No
Add3 No
2 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
13 FU Mult1 M(A2) (M-M+M)(M-M) Mult2
 Tomasulo Example Cycle 14
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 Load3 No
SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5
ADDD F6 F8 F2 6 10 11

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
Add2 No
Add3 No
1 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
14 FU Mult1 M(A2) (M-M+M)(M-M) Mult2
 Tomasulo Example Cycle 15
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 15 Load3 No
SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5
ADDD F6 F8 F2 6 10 11

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
Add2 No
Add3 No
0 Mult1 Yes MULTD M(A2) R(F4)
Mult2 Yes DIVD M(A1) Mult1

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
15 FU Mult1 M(A2) (M-M+M)(M-M) Mult2

• Mult1 (MULTD) completing; what is waiting for it?

 Tomasulo Example Cycle 16
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 15 16 Load3 No
SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5
ADDD F6 F8 F2 6 10 11

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
Add2 No
Add3 No
Mult1 No
40 Mult2 Yes DIVD M*F4 M(A1)

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
16 FU M*F4 M(A2) (M-M+M)(M-M) Mult2

• Just waiting for Mult2 (DIVD) to complete

Faster than light computation
(skip a couple of cycles)
 Tomasulo Example Cycle 55
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 15 16 Load3 No
SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5
ADDD F6 F8 F2 6 10 11

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
Add2 No
Add3 No
Mult1 No
1 Mult2 Yes DIVD M*F4 M(A1)

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
55 FU M*F4 M(A2) (M-M+M)(M-M) Mult2
 Tomasulo Example Cycle 56
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 15 16 Load3 No
SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5 56
ADDD F6 F8 F2 6 10 11

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
Add2 No
Add3 No
Mult1 No
0 Mult2 Yes DIVD M*F4 M(A1)

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
56 FU M*F4 M(A2) (M-M+M)(M-M) Mult2

• Mult2 (DIVD) is completing; what is waiting for it?

 Tomasulo Example Cycle 57
Instruction status: Exec Write
Instruction j k Issue Comp Result Busy Address
LD F6 34+ R2 1 3 4 Load1 No
LD F2 45+ R3 2 4 5 Load2 No
MULTD F0 F2 F4 3 15 16 Load3 No
SUBD F8 F6 F2 4 7 8
DIVD F10 F0 F6 5 56 57
ADDD F6 F8 F2 6 10 11

Reservation Stations: S1 S2 RS RS
Time Name Busy Op Vj Vk Qj Qk
Add1 No
Add2 No
Add3 No
Mult1 No
Mult2 Yes DIVD M*F4 M(A1)

Register result status:

Clock F0 F2 F4 F6 F8 F10 F12 ... F30
56 FU M*F4 M(A2) (M-M+M)(M-M) Result

• Once again: In-order issue, out-of-order execution and

out-of-order completion.
 Why can Tomasulo overlap
iterations of loops?
• Register renaming
– Multiple iterations use different physical destinations for
registers (dynamic loop unrolling).
• Reservation stations
– Permit instruction issue to advance past integer control flow
operations
– Also buffer old values of registers - totally avoiding the WAR
stall
• Other perspective: Tomasulo building data
flow dependency graph on the fly
Tomasulo’s scheme offers 2 major
advantages
1. Distribution of the hazard detection logic
– distributed reservation stations and the CDB
– If multiple instructions waiting on single result, & each
instruction has other operand, then instructions can be
released simultaneously by broadcast on CDB
– If a centralized register file were used, the units would
have to read their results from the registers when
register buses are available
2. Elimination of stalls for WAW and WAR
hazards
Tomasulo Drawbacks

• Complexity
– delays of 360/91, MIPS 10000, Alpha 21264,
IBM PPC 620 in CA:AQA 2/e, but not in silicon!
• Many associative stores (CDB) at high speed
• Performance limited by Common Data Bus
– Each CDB must go to multiple functional units
high capacitance, high wiring density
– Number of functional units that can complete per cycle
limited to one!
» Multiple CDBs  more FU logic for parallel assoc stores
• Non-precise interrupts!
– We will address this later
 And In Conclusion … #1
• Leverage Implicit Parallelism for Performance:
Instruction Level Parallelism
• Loop unrolling by compiler to increase ILP
• Branch prediction to increase ILP
• Dynamic HW exploiting ILP
– Works when can’t know dependence at compile time
– Can hide L1 cache misses
– Code for one machine runs well on another
 And In Conclusion … #2
• Reservations stations: renaming to larger set of registers +
buffering source operands
– Prevents registers as bottleneck
– Avoids WAR, WAW hazards
– Allows loop unrolling in HW
• Not limited to basic blocks
(integer units gets ahead, beyond branches)
• Helps cache misses as well
• Lasting Contributions
– Dynamic scheduling
– Register renaming
– Load/store disambiguation
• 360/91 descendants are Intel Pentium 4, IBM Power 5, AMD
Athlon/Opteron, …