1.

Stack and Subroutine

2. Interrupt and Serial
Communication
 The Stack

The stack is an area of memory

identified by the programmer for
temporary storage of
information

The stack uses a LIFO (Last

In First Out) structure
 Define Stack Memory
oStack memory operates in reverse direction, it is
customary to place the bottom of the stack at the end of
memory to keep it as far away from user programs as possible.

oIn the 8085, the stack is defined by setting the SP (Stack

Pointer) register.
LXI SP, FFFFH

oThis sets the Stack Pointer to location FFFFH (end of memory

for the 8085).
 Communication with Stack
o The 8085 provides two instructions: PUSH and POP
for storing information on the stack and
retrieving it back.
o Both PUSH and POP work with register pairs only.

PUSH Instruction POP Instruction Operation with

PUSH B POP B B – C Register pair

PUSH D POP D D – E Register pair

PUSH H POP H H – L Register pair

PUSH PSW POP PSW Accumulator and Flag

 The PUSH Instruction
• PUSH B
 Decrement SP by 1
 Copy the contents of register B to the memory location pointed
by SP
 Decrement SP by 1
 Copy the contents of register C to the memory location pointed
by SP
 The POP Instruction
• POP D
 Copy the contents of the memory location pointed to by the SP
to register E
 Increment SP by 1
 Copy the contents of the memory location pointed to by the SP
to register D
 Increment SP by 1
 The PSW Register Pair

o The 8085 recognizes one additional register pair called

the PSW (Program Status Word).

o This register pair is made up of the Accumulator and

the Flags registers.

PSW = Acc Flag

o It is possible to manipulate flag register using stack

memory concept.
 Some special instructions
• SPHL
Content of H-L pair are transferred to the stack
pointer

• XTHL
Exchange the content of H-L pair with top of the Stack

H A2 57 L H 67 38 L
8097 38 8097 8097 57 8097
SP SP
67 8098 A2 8098
Subroutines
 Subroutines
o A subroutine is a group of
instructions that will be
used repeatedly in different
locations of the program.

oRather than repeat the same

instructions several times, they
can be grouped into a subroutine
that is called from the different
locations.

oHowever, it is customary to
place subroutines separately from
the main program.
 Subroutines

o The 8085 has two instructions for dealing with

subroutines.

o The CALL instruction is used to redirect

program execution to the subroutine.

o The RET instruction is used to return the

execution to the calling routine.
Call & Return Instructions
2000H Instruction 1
4020H Instruction 1
2001H Instruction 2
4021H Instruction 2
2002H
4022H .
.
4023H .
2003H CALL 4020H
. 4024H .
2004H 4025H .
2005H 4026H .
2006H 4027H .
2007H 4028H .
. 4029H .
2008H 402AH .
.
402BH
2009H RET
.
200AH
.
 The CALL Instruction
• CALL 4000H
o 3-byte instruction.
o Push the address of the instruction immediately following
the CALL onto the stack and decrement the stack pointer
register by two.
o Load the program counter with the 16-bit address supplied
with the CALL instruction.
o Jump Unconditionally to memory location.
Timing Diagram of CALL
Instruction
 The RET Instruction
• RET
o 1-byte instruction
o Retrieve the return address from the top of the stack
and increments stack pointer register by two.
o Load the program counter with the return address.
o Unconditionally returns from a subroutine.

RET
Conditional CALL
Instruction
• CP <16-Bit Address> call when s = 0
• CM <16-Bit Address> call when s = 1

• CZ <16-Bit call when z = 1

Address> call when z = 0
• CNZ <16-Bit
• CPE <16-Bit Address> call when P = 1
Address>
• CPO <16-Bit Address> call when P = 0

• CC <16-Bit call when CY = 1

Address> call when CY = 0
• CNC <16-Bit
Conditional RETURN
Instruction
• RP <16-Bit Address> return when s = 0
• RM <16-Bit Address> return when s = 1

• RZ <16-Bit return when z = 1

Address> return when z = 0
• RNZ <16-Bit
• RPE <16-Bit Address> return when P = 1
Address>
• RPO <16-Bit Address> return when P = 0

• RC <16-Bit return when CY =

Address> 1 return when CY =
Interrupts
 Interrupts
• Interrupt is a process where an external device can get
the attention of the microprocessor.
– When the Microprocessor receives an interrupt signal,

– It suspends the currently executing program and

– jumps to a particular location of the program memory

known as Interrupt Service Routine (ISR) to respond to
the incoming interrupt.
– After servicing it returns back to the main program
and continue program execution
 Classification of Interrupts

• Maskable Interrupts (Can be blocked)

• Non-Maskable Interrupts (Can not be

blocked)

• Vectored (the address of the service routine is hard-

wired)
• Non-vectored (the address of the service routine needs
to be supplied externally by the device)
 The 8085 Interrupts

Interrupt Maskable Vectored

name
INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes

Priority Decreasing
 The 8085 Non-Vectored Interrupt
Process
1. The interrupt process should be enabled using the ‘EI’ instruction.
2. The 8085 checks for an interrupt during the execution of every instruction.
3. If INTR is high, μp completes current instruction, disables the interrupt
and sends INTA (Interrupt acknowledge) signal to the device that
4. interrupted
INTA allows the I/O device to send a RST instruction through data
Upon receiving the RST instruction, μp saves the memory location of
bus. 5.
the next instruction on the stack and the program is transferred to ‘ISR’
location (ISR Call) specified by the RST instruction
6. Microprocessor Performs the ISR.
7. ISR must include the ‘EI’ instruction to enable the further interrupt
within the program.
8. RET instruction at the end of the ISR allows the μp to retrieve the
return address from the stack and the program is transferred back to
where the program was interrupted.
 RST (Restart) Instructions

• The 8085 recognizes 8 RESTART instructions: RST0

- RST7. Restart Opcode ISR
Instruction Address

RST0 C7 0000H

each of these would send RST1 CF 0008H

RST2 D7 0010H
the execution to a
RST3 DF 0018H
predetermined memory RST4 E7 0020H
RST5 EF 0028H
location:
RST6 F7 0030H
RST7 FF 0038H
 The 8085 Maskable & Vectored
• Interrupts
The 8085 has 4 Masked & Vectored
interrupt inputs.
– RST 5.5, RST 6.5, RST 7.5
• They are all hardware interrupt and individually
maskable.
• They are automatically vectored according to the
following table:
Interrupt ISR Address

RST 5.5 002CH

RST 6.5 0034H

RST 7.5 003CH

 The 8085 Maskable & Vectored Interrupt
Process
1. The interrupt process should be enabled using the EI instruction.
2. The 8085 checks for an interrupt during the execution of
every instruction.
3. If there is an interrupt, and if the corresponding interrupt pin
is enabled using the interrupt mask, the microprocessor will
complete the executing instruction, and reset the interrupt flip flop.
4. The microprocessor then saves the address of the next instruction
on the stack.
5. The microprocessor jumps to the specific service routine.
5. The service routine must include the instruction EI to re-enable
the interrupt process.
6. At the end of the service routine, the RET instruction returns
the execution to where the program was interrupted.
 Set Interrupt Mask
(SIM)
7
0
6 5 4 3 2 1

SDO SDE XX R7.5 MSE M7.5

M6.5 M5.5

RST5.5 Mask
Serial Data Out
RST6.5 Mask
RST7.5 Mask } 0-
Available
1 - Masked

Enable Serial Data Mask Set Enable

0 - Ignore bit 7 0 - Ignore bits 0-2
1 - Send bit 7 to 1 - Set the masks
SOD pin according to bits 0-2

Not Used 1 - Force RST7.5 Flip Flop to

reset
Maskable Interrupts Hardware
Logic RST 7.5 Memory
RST 7.5

M 7.5

RST 6.5

M 6.5

RST 5.5

M 5.5

INTR

Interrupt
Enable
Flip Flop
 Modify the Interrupt Masks Using the SIM Instruction

• Example: Set the interrupt masks so that RST5.5 and

RST7.5 are enabled, but RST6.5 is masked.
SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5
0 0
Serial Don’t Bit 5 is Allow Allow Enable Disable Enable
data is use serial not used setting setting 7.5 6.5 5.5
ignored data the the
masks masks

Content of accumulator is = 0 0 0 0 1 0 1 0 = 0A H

EI ; Enable interrupts including INTR

MVI A, ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5
0A SIM ; Apply the settings RST masks
 Read Interrupt Mask
(RIM)
7 6 5 4 3 2 1 0
SDI P7.5 P5.5 IE
P6.5 M7.5 M6.5 M5.5

RST5.5 Mask
Serial Data In RST6.5 Mask
RST7.5 Mask
} 0-
Available
1 - Masked
RST5.5 Interrupt
Pending RST6.5
Interrupt Enable
Interrupt Pending
Value of the Interrupt
RST7.5 Interrupt Enable Flip Flop
Pending
 The 8085 Non-Maskable
• Interrupts
TRAP is the only non-maskable interrupt.
– It does not need to be enabled because it cannot
be disabled.
• It has the highest priority amongst interrupts.
• The ISR address for TRAP is 0024H
• It is edge and level sensitive.
– It needs to be high and stay high to be recognized.
– Once it is recognized, it won’t be recognized again until
it goes low, then high again.

• TRAP is usually used for power failure and

emergency shutoff.
 The 8085
Interrupts
Interrupt Maskable Masking Vectored Memory Triggering
Name Method Method

INTR Yes DI / EI No No Level

Sensitive

RST 5.5 Yes DI / EI Yes No Level

SIM Sensitive

RST 6.5 Yes DI / EI Yes No Level

SIM Sensitive

RST 7.5 Yes DI / EI Yes Yes Edge

SIM Sensitive

TRAP No None Yes No Level &

Edge
Sensitive
 Serial Data
Communication
 Serial Input / Output data using
8085
8085 Microprocessor has
two Serial Input / Output pins
that are used to read / write
one bit data to and from
peripheral devices.

Pin 4: SOD (Serial Output Data)

Pin 5: SID (Serial Input Data)

 SID (Serial Input Data) line
• There is an One bit Input line inside the 8085 CPU
(Pin number 5)
• 1 bit data can be externally read and stored using
this SID line
• The data that is read is stored in the D7th bit of the
Accumulator
• RIM instruction is used to read the SID line
7 6 5 4 3 2 1 0
SDI P7.5 P6.5 P5.5 IE M7.5 M6.5 M5.5
RIM
 Example
• As seen from the figure 1,
if the SID line is connected
with
+5V and RIM instruction
is executed, then
the
Accumulator’s MSB bit will
be loaded with a Logic 1

• if the SID line is

connected with 0V (GND)
and RIM instruction is
executed, then the
Accumulator’s MSB bit will
be loaded with a Logic 0
 SOD (Serial Output Data)
• Line
There is a One bit Output port inside the 8085 CPU
(Pin number 4)
• 1 bit data can be externally written in this port.
• To write data into this port, SIM instruction is used.
• The data that is to be written in this port must be stored in
the D7th bit of the Accumulator.
• Bit D6 of the Accumulator is known as SOE (Serial
output Enable). This bit must be set to 1 to enable Serial
data output.
7 6 5 4 3 2 1 0
SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5
SIM
 Example

• To write a logic 1in this SOD

line, Load the accumulator
with C0H and then execute SIM
instruction
• To write a logic 0in this SOD
line, Load the accumulator
with 40H and then execute SIM
instruction