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8.troublesht DRC & Mismatch

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0% found this document useful (0 votes)
2K views64 pages

8.troublesht DRC & Mismatch

Uploaded by

魏宇
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Tessent: Scan and ATPG

Module 8

Troubleshooting
Test Patterns
Objectives

Upon completion of this module, you will be able to:

 Debug common Design Rules Checking (DRC) violations.


 C1
 C3
 C4
 C6
 D5
 D6
 E4
 E10
 T3
 Understand how to Debug simulation mismatches.

8-2 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Common DRC Rules
 May require design changes
 C1, T3, T4, T5, E4
 Impact test coverage
 D1, E10, C7, A1, A7
 May require special handling
 C2, C3, C4, C6, C8, C9, D7
 Other common DRC failures
 D5, D6, A2

8-3 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Analyzing DRC Violations: Commands
 Commands and options used in Setup mode to analyze DRC
violations:
 Using the ATPG_analysis option of the SET DRc Handling
command provides more comprehensive analysis on DRC
violations:
– C1, C3, C4, C6, D5, D6, E4 , E10, T3, etc.
 Use SET GAte Level to specify the level of information reported
or displayed:
– Design cell or primitive.
 Use SET GAte Report to specify the type of information
reported:
– Trace (simulates shift of scan chain).
– Drc_pattern (access data during any procedure).
– Pattern_index (specifies a pattern when displaying the value of a
gate).
– State_stability (displays simulation values for the load_unload
procedure and the capture clock cycle used to determine the constant
state elements value at initial load time).

8-4 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Analyzing DRC Violations: Commands (Cont.)
 Example: SET GAte Report Drc_pattern
STate_stability
 Reports which elements are stable and hold their values across
shift cycles and patterns.
 Useful for scan chain tracing.
 Useful for tracing some state, such as a TAP controller in
test_setup.
 Report includes first application of load_unload and shift data.
 Compare state stability values with superimposed values using:
– SET GAte Report Drc_pattern load_unload
– SET GAte Report Drc_pattern shift
 Data is available when:
– DRC is run after issuing the SET GAte Report DRc_pattern
command.
– A test_setup procedure exists.

8-5 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Analyzing DRC Violations: Commands in DFTVisualizer

SET GAte Report Drc_pattern load_unload

SET GAte Report Drc_pattern shift

8-6 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Analyzing DRC Violations: Commands in Visualizer (Cont.)

SET GAte Report Drc_pattern STate_stability

8-7 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Analyzing DRC Violations: Report Gates Command
 REPort GAtes reports additional information for troubleshooting
 Specific gate
– SETUP> REPort GAtes <instance_number>
 A histogram of all gate types
– SETUP> REPort GAtes -Type Histogram
 All gates of a specific logic type
– SETUP> REPort GAtes -Type gate_type . . .
 A path between two gates
– SETUP> REPort GAtes -Path gate_ID#_1 gate_ID#_2
 The first input of a gate (back tracing)
(Reports the gate connected to the first input listed of the previously
reported gate)
– SETUP> B
 Reporting on the first fanout (forward tracing) of the next gate
– SETUP>F
To use “B” or “F”, the gate level must be set to primitive.
SETUP> SET GAte Level Primitive

8-8 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Analyzing DRC Violations: Report Gates Command (Cont.)
 Report gate fan-in and fan-out (forward and backward
tracing).
 “b” traces the first input and “f” traces the first output pin.

8-9 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Clocks
 Clocks:
 Any primary input (PI) that changes the state of a sequential element.
– Includes set and reset inputs.
 The transition of the clock from OFF to ON is the leading edge
(LE) of the clock.
 The transition of clock from ON to OFF is the trailing edge
(TE) of the clock.
 Example:
Off state

SETUP>ADD CLock 0 CLK1

LE TE

CLK1

Off state
Clock Cycle

8-10 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Clock Cones
 Clock cone:
 A gate pin is defined as being in the clock cone if there is a path
through combinational logic gates from the clock pin to the
output pin.
 Pin “B” is in the “clock cone” of CLK2.

 Display clock cone with SET GAte Report -Clock <clock>.

8-11 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Effect Cones

 Effect cone:
 A signal is defined as being in the effect cone if there is a
sequential element between the output pin and the clock pin.
 “Q” is in the “effect cone” of CLK2.

8-12 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Both Cones

 Both cones:
 An output pin that is in both the clock cone and the effect cone.
 Pin “D” is in both the “clock” and “effect cone” of CLK.

8-13 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Clock Rules: C1
 Clock C1 Rules:
 All clock inputs (including sets and resets) of scan cells must not
capture data; that is, they must be at their inactive states.
– Data must not be captured when all specified clocks are set at their
off states.

The clock input value is at an X because


the EN signal value is an X.

8-14 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Clock Rules: C3
 ATPG Expert solves these automatically.
 C3 clock rules:
 Designs that contain both leading edge and trailing edge flops
have the potential for C3 DRC violations.
– Special handling is required.
Source of C3 violation

Leading Edge FF
D Q

CLK1 Combinational
Logic D Q

C3 violation
Off state of CLK1
is 0
Trailing Edge FF

8-15 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Clock Rules: C4
 ATPG Expert solves these automatically.
 C4 clock rules:
 Designs that contain both leading edge and trailing edge flops
where the output of the leading edge flop is connected through
combinational logic to the input clock port of the trailing edge
flop have the potential for C4 DRC violations.
– Special handling is required.
Source of C4 violation

Leading Edge FF
D Q

CLK1 D Q

Combinational C4 violation
Logic
Off state of CLK1
is 0
Trailing Edge FF

8-16 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Clock Rules: C6
 ATPG Expert solves these automatically.
 C6 clock rules:
 A clock may not affect data that it is capturing.
 A rule violation occurs when a clock input of a scannable element
and its data line are in the same cone.

C6 violation

1
C or B D Q

 Default is to simulate the D input with clock value at the ON state.


– Default simulation will capture a 1 in this case.
 During off state (0) data is 0. When the clock pulses the flop captures
the old data.
8-17 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
DRC Violations: C1
 A C1 violation may occur if:
 A clock is not defined or the wrong off state is defined for a
clock.

// Error: Clock PIs off failed to force off


a clock line of MASTER /addr_1/reg_q_0_ (333). (C1
-1)
SETUP> set gate report drc_pattern load_unload
SETUP> report gate 333
// /addr_1/reg_q_0_ (333) DFF
// "S" I (0) 39 -
// R I (X) 10 - /clear
// CLK I (0) 234 - /ix298/Y
// "D0" I (X) 285 -
// "OUT" O (X) 46 - 47-
SETUP> b 2
// /clear (10) PI
// clear O (X) 157 - 158- 159-
SETUP> report clocks
// list of clocks Debugging steps with DFTVisualizer
// /tclk off - state = 0 1. open visualizer
SETUP> add clocks 0 clear 2. set gate level primitive
3. analyze drc violation c1-1

8-18 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
DRC Violations: C1 (Cont.)
 What to look for when debugging a C1 violation:
 Find clock, set, or reset equal to X.
 How to debug C1 violations using commands:
1. SET GAte Report drc_pattern load_unload
2. REPort DRc Rule C1-1
3. REPort GAte -Endpoints -Backward id#_of_gate_connected
to_offending_gate’s_clock
 DFTVisualizer:
1. OPEn VIsualizer
2. SET GAte Level primitive
3. ANAlyze DRc Violation C1-1
Or
1. ANAlyze DRc Violation C1-1 -Display

8-19 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
DRC Violations: C3
 A C3 violation may occur if one of the following is true:
 The output of a leading edge triggered FF is connected to the D
input of a trailing edge triggered FF.
– Potential for data to pass through source and sink in one clock cycle.
 RAM Write input is in the clock cone and a data-in or address
input of the Write port is in the effect cone.
 RAM Read is in the clock cone and an address input of the
associated Read port is in the effect cone.

C3 violation

1 1 Combinational 1 …0
D Q D Q
Logic

8-20 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Event Simulation
 By default, the tool simulates a single event per test cycle:
 Clocks have pulsed.
 Combinational logic is updated based on state element values
from previous clock pulse.
 State elements have not changed.
 Data is captured on one clock edge.
 Simulation data is not updated between clock edges.

Ordinary PIs One clock pulse to update


state elements

Clock PIs

POs

Measure

8-21 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Setting Event Simulation
 Default event simulation is not appropriate if there are C3/C4 DRC
violations.
 Do the following to change event simulation:
SETUP> SET SPlit Capture_cycle ON // simulates 2 events in clock pulse
// Used to properly simulate
and avoid
C3 and C4 problems

Ordinary PIs

Simulate LE of clock Simulate TE of clock


1 0
D Q Clock PIs
0

1
POs
DFF
Measure
When the clock goes high (“1”)
the current value of the DFF
(“0”) is measured on Q.

8-22 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Handling C1 Violations

 If the offending clock’s off state is incorrect:


 Use the ADD CLocks command to redefine the clock with the
correct off state.
 If the off state is correct:
 The problem typically is due to an indeterminate value (X) in
related logic that causes the clock’s value at a scan cell to be X.
 Fix these by using the Add Pin Constraint command to constrain
a primary input pin to a value that removes the X:
 SETUP> add input constraints EN -c0
 This allows the tool to consider the CLK signal to be the only
clock signal to the clk input of the scan cell.

8-23 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Handling C3 and C4 Violations
 ATPG Expert solves these automatically.
 Capture data for LE and TE flip-flops between clock edges.
SETUP> SET SPlit Capture_cycle ON
 The SET SPlit Capture_cycle command cannot be used with
RAM_sequential patterns.
 Use multi_load patterns.
SETUP> SET MUltiple Load on
SETUP> SET PAttern Type -Sequential 4

8-24 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Handling C6 Violations
 The tool uses its clock sequential fault simulator to simulate
multiple events in a single cycle.

8-25 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Handling C6 Violations (Cont.)
 Handling a C6 violation:
SETUP> SET CLock_off Simulation ON
 Enables the simulation of the event where all clock primary
inputs are at their “off” value.
 Forces PIs.
 Maintains previous state element values.

1
D Q

 Simulation will capture a 0 in this case.


 Not compatible with ram_sequential.

8-26 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Data Rules: D5
 A D5 violation occurs when sequential elements are identified
as not belonging to a scan chain.
 The default handling is a warning.
– Failure to satisfy this rule results in loss of test coverage.
 Applies to both latches and FFs.
– For latches, the D6 rule will also apply.

8-27 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Data Rules: D6
 All non-scan latches must behave as transparent latches.
 A D6 violation occurs if a latch fails one of the following
conditions:
 If a latch creates a feedback path, that path must be broken.
 Latches must have a propagable path to an observe point.
 Latches must pass a value when all clocks are off.
 All clock, set, and reset inputs must be at determinate state when
all clocks are off.
 Latches must have only one set/reset/clock input when all
defined clocks are off.

8-28 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Debugging D5 and D6 Violations
 To debug a D5-D6 violation the recommended steps
(commands) are:
1. set gate report drc_pattern state_stability
2. set drc handling d5 verbose
3. set drc handling d6 verbose
 Case D5:
4. report drc rules d5
5. report gate <flip-flop>
6. Non-scan flops become TIEX. By setting a sequential depth
some non-scan flops become controllable.
– set pattern type -sequential 2
7. report gate <flip-flop>
 Case D6:
4. report gate -type TLA
5. report drc rule d6-1
6. report gate <d6 error gate>

8-29 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Debugging D5 and D6 Violations (Cont.)
 DFTVisualizer:
1. Open DFTVisualizer
2. Set gate level primitive
3. Analyze DRC violation D5-1/D6-1

8-30 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Handling D5 and D6 Violations
 Handling D5 and D6:
 Enable clock sequential ATPG.
SETUP> SET PAttern Type -SEQuential 2 (or more)
 D6—if latch creates a potential feedback path, that path must be
broken by scan cells or non-scan cells other than transparent
latches. Use the SET TLa Loop_handling command for this
case.

8-31 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
DRC Rule E4: Scan Procedure (Bus Contention)
 E4 Types:
 BIDI.
 Tri-state driver (TSD) controlled from PI.
 TSD controlled from sequential logic.
 Bus contention occurs when tri-state drivers have conflicting
values when driving the same net.
 Any two inputs at values X and X, 0 and X, 1 and X, 1 and 0.
 E4 violations occur when bus contention occurs during scan
procedure.
 Example:
– shift
– load_unload
– test_setup

8-32 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
General E4 Debugging Steps

1. Use the SET GAte Report Drc_pattern <test_setup,


load_unload, or shift> command to specify the name of
the procedure and the time in the test procedure file to
display a gate’s simulated value.
2. Use the REPort GAtes <instance_number> command to
display netlist information and simulation results.
3. Trace back on the tri-state enable line. All drivers should be
off or only one driver should be on.

8-33 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Debugging E4 Violations: Commands
 Make E4 violations occur as an error from within the tools.
SETUP> SET DRc Handling E4 Error
SETUP> SET SYstem Mode ATPG // performs DRC checking
 Use DFTVisualizer.
 Select Tools > Analyze DRC from within DFTVisualizer.
 Trace back through the design and correct the problem.
 Optionally, use the REPort GAtes command.
SETUP> SET DRc Handling E4 Error
SETUP> SET GAte Report Drc_pattern load_unload
SETUP> SET SYstem Mode ATPG
SETUP> REPort GAtes <instance_number>
SETUP> SET GAte Level Primitive
SETUP> B
HINT: B 2 will back trace on the second
input of the last gate reported.
Trace back to locate the problem.

8-34 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Design Rule E4 Example

Debugging steps with


DFTVisualizer
1. set gate report drc
<test_setup, load_unload,

shift>
2. set system mode atpg
3. open schematic viewer
4. set gate level primitive
5. analyze drc violation e4-1
6. trace back on bus gate

8-35 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Design Rule E4 Example (Cont.)

ATPG> set system mode atpg


ATPG> report drc rules e4
// Warning: Bus contention on /tsdo/dout[0] (314) occurred at time 0 of
load_unload procedure. (E4-1)
ATPG> set gate report drc_pattern load_unload
ATPG> report gate 314
// /tsdo (314) BUS
// "I0" I (XX) 294-/tsdo/ix149/Y
// "I1" I (XX) 286-/tsdo/ix145/Y
// "OUT" O (XX) 396-/dout[0] 330-
ATPG> report gate 294 286
// /tsdo/ix149 (294) TSD
// E I (XX) 247-/ix310/Y
// "D" I (XX) 221-
// Y O (XX) 314-
// /tsdo/ix145 (286) TSD
// E I (XX) 161-/ix138/Y
// "D" I (XX) 213-
// Y O (XX) 314-
ATPG> report gate -e -b 247
// ---------------------------------------------------------------------------
// Begin backward trace for gate /ix310 (247).
// ---------------------------------------------------------------------------
// /tsden[1] (29) PI
// tsden[1] O (XX) 160-/ix292/A
// /scan_en (32) PI
// scan_en O (11) 163-/ix140/A0 161-/ix138/A1 162-/senmux/ix9/A1
// /e4 (34) PI
// e4 O (XX) 163-/ix140/A1
ATPG> report test stimulus -set 247 0
// Force 1 /scan_en (32)
// Force 1 /e4 (34)

8-36 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
E4 Contention on Bidirectionals
 Bidirectionals fail when bus contention occurs between the
chip bidi outputs and the tester signal that drives the input of
the chip bidi.
 By default the tester will drive an X into the bidi.
 Debugging—constrain bidi to Z in the procedure:
 Edit test_setup and load/unload procedures.
force <bidi_signal_name> Z;

Possible contention
Scan cells

Bidi pins
Force to Z during load_unload

8-37 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Handling E4 Violations
 Case 1: TSD controlled from PI.
report gate -e -b <tsd enable>
report test stimulus -set <tsd enable> 0
 Force PI in procedure.
 Case 2: TSD controlled from sequential logic.
report gate -e -b <tsd enable>
 Analyze and fix sequential logic in procedure or make design
changes.
 Case 3: BIDI.
 Constrain bidi to Z in the procedure.
force <bidi> Z;

8-38 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
DRC Rule E10: Scan Procedure (Bus Contention)
 Performs bus contention mutual-exclusivity checking.
 Differs from rule E4 in that it does not check for this condition
during test procedures.
 Analyzes each dominant strong bus to determine if it can
cause contention.
 Debug using the same commands as you would for E4
violations.
 Use additional command SET DRc Handling Atpg_analysis
to fully provide test generation analysis.

8-39 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Handling E10 Violations
 Two methods address this failure:
1. Turn on additional analysis during the ATPG process.
2. Define atpg functions and constraints to assure that contention
cannot occur.
 To turn on additional ATPG analysis for bus contention
checking use the following command:
set contention check capture -catpg
 This command assures that bus contention does not exist before
or after the capture clock.
 Use of this command will impact ATPG run times.
 The second method uses atpg functions and constraints. The
following commands are an example of using this method.
add atpg function func1 SELECT1 tsden[0] ~tsden[1]
add atpg constraint 1 func1
 Use of this feature also requires additional run time.
 Use set bus handling if you know the bus is “safe”.

8-40 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Scan Chain Trace Rules: T3, T4, and T5
 T3 Trace Rule:
 The shift procedure must create a sensitizable path from the scan
chain output back to the scan chain input.
 T4 Trace Rule:
 A memory element in the scan path must have an active clock
during some time period of the shift procedure.
 T5 Trace Rule:
 There must never be an X value placed on a clock input or an
active (X or 1) value on a set or reset input of a memory element
in the scan path.

8-41 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Scan Chain Trace Rules: T3
 Tool traces from scan output pin to scan input pin using load-
unload and shift procedures.
 An unknown (x) is shifted backwards from scan-out.
 Some circuit values are learned “tied” from test_setup, pin
constraint, and other procedures.
 Follows sensitized path backward.
 Simulates shift to back trace through sequential gates.
 An improperly sensitized gate in the scan path will cause an
error condition (T3).
T3 here
XXX XXX Scan_out
SI Q XXX XXX
SI Q

010 XXX
010

Scan cell 1 Scan cell 0

Simulation of one shift operation Combinational


Logic

8-42 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Scan Chain Trace Rules: T5
 T5 trace rule:
 During the shift procedure, scan clocks should pulse and
set/resets should be disabled.

SI Q SI Q SI Q SO
XXX 010
SET

XXX

CLK
Good

Combinational
Logic

Bad, T5 violations

8-43 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Common Causes of T3, T4, and T5 Errors
 Common causes of T3, T4, and T5 errors:
 Scan Enable (SE) controlled through TAP or state machine not
initialized with test_setup and constraints.
 Set or reset not properly initialized.
 Shift clock incorrectly defined in shift procedure.
 Missing or incorrect pin constraint.

8-44 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Debugging T3, T4, and T5 Violations
 Use DFTVisualizer to back trace on problem value.
 Optionally, use the REPort GAtes command.
 SETUP> SET TRace Report ON
– The tool prints out all the gates it traces through when it traces the
scan chains.
 SETUP> SET GAte Report Trace
– The tool prints out the data for the “shift” procedure.
– Optionally, use the SET Gate Report Drc shift command.
 SETUP> SET SYstem Mode ATPG
 SETUP> REPort GAtes <instance_number>
– Determine where scan chain is blocked.
 SETUP> B
– Trace back the blocking value through the design and correct the
problem(s).
 Correct error by accessing simulated values of all time
periods of the shift procedure.
8-45 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
State Stability
 Condition of the device to have known states on non-
scan latches
 Keeping these values for the duration of the test session

 Non-scan latches hold the device in a condition for


the purpose of a test strategy
 Routing chains
 Using a TAP controller as part of the capture
 Other non-scan block initialization

 Impact on:
 Scan chain tracing (T3/T5), C1 and other DRC checking
 Tied non-scan latches (D5)
 Directly and indirectly affects test coverage

8-46 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
The Need for State Stability Analysis
 Test procedures are applied many times.

 Scan chain tracing is done only once.


 ATPG uses traced cells as control and observation points.

 Values of non-scan memory elements could change over


procedures (e.g. TAP controller registers).

 Verifies the question: Can the initialized state of any non-scan


cell be predicted so that it can be trusted for scan operation?

 Analyzes the stability of the value of non-scan memory


elements across multiple application of test procedures.

8-47 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Testbenches
 Tessent FastScan and Tessent TestKompress provide serial
and parallel Verilog or VHDL testbenches.
 They drive time-based simulations to verify the tool’s
expected values against the simulated values.
 When these values do not match, there is a simulation
mismatch:
 Functional discrepancies.
 Timing issues (Tessent FastScan and Tessent TestKompress are
event-driven).

8-48 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Serial Testbench
 In the serial testbench, the scan chain is operated like a tester:
 Data is shifted serially through the chain.
 Takes a long time to simulate test vectors.
 Reports the scan output pin and time of mismatch.
 Reports on simulation mismatch only available at POs and scan_out
pins.
 Normal practice is to simulate 2 or 3 serial patterns.
ATPG> SET PAttern Filtering –Sample_per_type 2
ATPG> SAVe PAtterns –Verilog –Serial <filename>
 You also can designate a Verilog vector signal parameter file to
use in your testbench that can help you troubleshoot any
problems you may encounter during simulation.
ATPG> SET PAttern Filtering –Sample_per_type 2
ATPG> SAVe PAtterns –Verilog –Serial <pat_filename>
\
-PARameter <parameter_filename>
8-49 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Parallel Testbench
 The parallel testbench simulator has access to the internal
nodes in the design:
 Data is loaded in parallel.
– Data is directly “forced” at scan cell inputs.
– Shift procedure is applied once.
– Loads and unloads the entire scan chain in one clock cycle.
 Reduced simulation time.
 Reports the following:
 Time.
 Pattern number.
 Name/location of scan cell (or PO) where mismatch is observed.
 Normal practice is to simulate all parallel patterns.

8-50 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Debugging Simulation Mismatches
Start

When, Where, and How Many Mismatches?

Serial Clock Skew


Chain Test Y Problem in
Fails? Scan Path

All Timing Violations


Scan Tests Y
Fail?

Library Problems

Parallel
Patterns Fail, N
Serial Pass? DRC Issues

8-51 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
DRC Violations: Simulation Mismatches

 DRC violations that are most likely to cause simulation


mismatches are:
 C3
 C4
 C6
 If mismatches occur, first check if DRCs were reported.

8-52 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
When, Where, and How Many Mismatches
 Checking for mismatches:
 Does the chain test fail?
– If the serial pattern fails the chain test also fails.
– If chain test fails, check for timing violations or library discrepancy.
 Do both the serial and parallel test bench fail or just one of them?
– Serial failure indicates mismatch is related to scan shifting.
– A shadow problem may cause a serial testbench to pass and the
parallel testbench to fail.
 Do only certain pattern types fail?
– If only ram sequential patterns fail, the problem is related to RAMs.
– If only clock_sequential patterns fail, the problem is related to non-
scan flip-flops and latches.

8-53 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Mismatch Symptoms

 When running the testbench, simulation mismatches are


reported as follows:

# Loading pat_par.v.0.vec
#
# Begin chain test
#
# End chain test
#
# 2970: Simulated response 001001 pattern 21 cycle 74
# 2970: Expected response 101001 pattern 21 cycle 74
# 2970: Mismatch at chain chain3 cell 0 name I1foo3.Q, Simulated 0, Expected 1
# 3090: Simulated response 001101 pattern 22 cycle 77
# 3090: Expected response 101101 pattern 22 cycle 77
# 3090: Mismatch at chain chain3 cell 0 name I1.foo3.Q, Simulated 0, Expected 1
# 3210: Simulated response 110011 pattern 23 cycle 80
# 3210: Expected response 010011 pattern 23 cycle 80
# 3210: Mismatch at chain chain3 cell 0 name I1.foo3.Q, Simulated 1, Expected 0
# ** Note: $finish : pat_par.v(501)
# Time: 3242 ns Iteration: 0 Instance: /top_par_v

8-54 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Clock Skew Problems
 Clock delays are caused by the following:
 Routing.
 Gates (muxes, buffers) on clock lines.
 Do the following to detect this problem:
 Run a time-based simulation using full timing.
– QuestaSim or HDL simulator.
 Run a critical timing analysis in scan mode.
– SST Velocity or another static timing analyzer.

8-55 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Timing Violations
 The following timing issues cause mismatches:
 Setup and hold violations during testbench simulation.
 Timeplate with timing too tight.
– Timing events need more separation.
 Do the following to correct this problem:
 Examine the simulation data and compare the values observed
with values expected by the tool.
 Expand timeplate and/or test procedure files.
– Default timing has 10 ns separation of events.
– Delay the measured PO and pulse capture clock.

8-56 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Library Problems
 Incorrect library model:
 For combinational and sequential elements, this causes
mismatches for all patterns.
 For instances such as RAM, this causes mismatches for a few
patterns (as an example, RAM_sequential).
 Non-equal values on the inputs to non-tristate multi-driven nets
 To check for this problem:
 Run simulation on library.
– Has the library been validated (verified)?

8-57 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Report Mismatch Sources Command

8-58 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Analyze Simulation Mismatches
 ANAlyze Simulation Mismatches {-AUto |
{- FAilure_file failure_file [-VCD_file
vcd filename]} | {-MISmatches mismatch_bit..}
|Verilog_testbench_pathname}
[-Internal Patterns | -External Patterns]
[-SImulation_script simulator_invoke_script]
[-Manual]} [-SCan_test | -Chain_test | -ALl_test]
[-HOST server_name] [-Lib lib_name]
[-TEstbench_for_vcd new_filename [-REplace]]

 Create the first Verilog testbench with fail file dump capability
enabled.
 Run the testbench to generate a failure file.
 Load the failure file and save fail patterns to a new Verilog testbench
with VCD dump capability.
 Run the new testbench to create a VCD file.
 Load the VCD file and trace mismatch sources.

8-59 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Automatic Simulation Mismatch Analysis Flow
1. Invoke Tessent FastScan or
Tessent TestKompress on the
netlist.
2. Specify the scan data for scan
cells and switch to Good, Fault,
or ATPG system mode.
3. Specify the source of the test
patterns.
4. If you use a third-party
simulator, specify your
simulator invocation script.
5. Run the automatic mismatch
analysis.
6. Open DFTVisualizer to view
For more information, refer to “Analyzing and further troubleshoot
Simulation Mismatches” in the Scan and mismatches.
ATPG Process Guide.

8-60 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Troubleshooting Tips
 Adding dummy signals in the design and in the test
procedures will show up in the testbench to help
troubleshoot.
 This can now be accomplished in a more automated way by
putting “VERILOG_VECTYPE_SIGNAL 1;” in the parameter
file.

8-61 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Debugging Serial Simulation Mismatches: Chain Test
 In most cases where there are serial simulation mismatches,
but the parallel simulation passes, the serial chain test will
also fail.
 Confirm that the chain test fails:
 Save out a pattern with chain test.
SETUP> SAVe PAtterns <filename> -Serial -CHain_test
 Verify pattern using a time-based simulator.
 If the chain test fails, do the following:
 Edit the procedure file so that it contains two independent shifts.
 Use the parallel test bench.
 Use the new VERILOG_VECTYPE_SIGNAL directive in the
parameter file to help troubleshoot the problem.

8-62 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Clock Skew in Chain Test
 Clock skew occurs in chain test when the scan cells
are clocked at slightly different times:
 Scan cells should capture “old” data of D.
– But, Q is updated with a “new” value.
 Solution:
 Add buffers.
 Redo clock synthesis.
 Add lockup latches.
Insert lockup latch

D Q D Q

DFF1 DFF2

Clk1 Clk2

8-63 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation
Lab 8: Troubleshooting Test Patterns
During this lab, you will

 Use DFTVisualizer to debug DRC violations.


 Correct DRC violations.
 Troubleshoot simulation mismatches.

8-64 • Tessent: Scan and ATPG: Troubleshooting Test Patterns Copyright © 1999-2009 Mentor Graphics Corporation

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