THE NATIONAL INSTITUTE OF ENGINEERING

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

COURSE: INTRODUCTION TO ELECTRONICS ENGINEERING

Module – 3
Boolean Algebra and Logic Circuits

Course Instructor
Ms. SOBIA NAZ
Assistant Professor
Dept. of ECE
NIE, Mysuru

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Course Structure: Module – 3: Boolean Algebra and Logic Circuits
Boolean Algebra and Logic Circuits
 Introduction to number systems  Encoder
 Basic definitions  Decoder
 Axiomatic definition of Boolean algebra  Flip-flop’s
 Basic theorems and properties of Boolean algebra  Counters
 Boolean functions
 Canonical and standard forms
 Other logic operations
 Digital logic gates
 Adders- half adder
 Full adder
 Multiplexer
 Demultiplexer

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Logic Design
 Digital systems usually are binary, that is, they operate with two-valued signals, which we will label 0 and 1.

(Although multivalued systems have been built, two-valued systems are more reliable and thus almost all

digital systems use two-valued signals.)

 Computers and calculators are obvious examples of digital systems, but most electronic systems contain a

large amount of digital logic.

 The music that we listen to on our CD players or iPods, the individual dots on a computer screen (and on

the smart digital televisions), and most cell phone signals are coded into strings of binary digits, referred to as

bits.

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Logic Design
 Digital systems have such a prominent role in everyday life that we refer to the present technological period as

the DIGITAL AGE.

 Digital Systems Are Used In

1. Communication
2. Business Transactions
3. Traffic Control
4. Spacecraft Guidance
5. Medical Treatment
6. Weather Monitoring
7. Internet
8. Digital Telephones
9. Digital Televisions
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Logic Design
 One characteristic of digital systems is their ability to represent and manipulate discrete elements of

information.

 Any set that is restricted to a finite number of elements contains discrete information.

 Examples of discrete sets are the 10 decimal digits, the 26 letters of the alphabet, the 52 playing cards, and

the 64 squares of a chessboard.

 Early digital computers were used for numeric computations.

 In this case, the discrete elements were the DIGITS.

 From this application, the term Digital Computer emerged.

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Logic Design

Fig: A Digital System

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 Logic Design
Example 1:

A system has three inputs A, B, and C, and one output, Z, such that Z=1 if and
only if* two of the inputs are 1.
Table. A truth table

The physical manifestation of these binary

quantities may be one of two voltages, for
example,
0 volts (V) or ground for logic 0 and
5 V for logic 1

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 Logic Design
 Introduction to number systems

 Integers are normally written using a positional number system, in which each digit represents the
coefficient in a power series.

N = an-1r n-1 + an-2r n-2 + ...........+ a2r 2 + a1r + a0

 where ‘n’ is the number of digits, r is the radix or base, and the ai are the coefficients, where each is an

integer in the range 0 ≤ ai < r

 For decimal, r =10, and the a’s are in the range 0 to 9
 For binary, r = 2, and the a’s are all either 0 or 1
 hexadecimal, r =16 and the a’s are in the range 0 to 15 (10-A, 11-B, 12-C, 13-D, 14-E, 15-F)

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 Logic Design
 Introduction to number systems

(7642)10 = 7 * 103 + 6 * 102 +4 * 101 + 2 * 100

(101111)2 = 1 * 25 + 0 * 24 + 1 * 23 + 1 * 22 + 1 * 21 + 1*20
= 32 + 8 + 4 + 2 + 1
= (47)10

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 Logic Design
 Introduction to number systems

(4021.2)5 = (__________________) 10
= 4 * 53 + 0 * 52 +2 * 51 + 1 * 50 + 2 * 5-1
= (511.4)10

(B65F)H/16 = (__________________) 10
= 11 * 163 + 6 * 162 + 5 * 161 + 15 * 160
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 Logic Design
 Introduction to number systems
Table: Powers of 2 Table: First 32 binary integers

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 Logic Design
 Introduction to number systems
Decimal Binary Octal Hexadecimal
(Base 10) (Base 2) (Base 8) (Base 16)
00 0000 00 0
01 0001 01 1
02 0010 02 2
03 0011 03 3
04 0100 04 4
05 0101 05 5
06 0110 06 6
07 0111 07 7 Table: Numbers with different bases

08 1000 10 8
09 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15
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1111 17 F 07/03/2024 12
 Logic Design
 Introduction to number systems

Note:

The number one less than 2n consists of n 1’s

(for example, 24 - 1 = 1111 = 15 and 25 - 1 = 11111 = 31).
An n-bit number can represent the positive integers from 0 to 2n - 1
Thus, for example, 4-bit numbers have the range of 0 to 15,
8-bit numbers 0 to 255 and 16-bit numbers 0 to 65,535.

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 Logic Design
 Introduction to number systems: IPv4 & IPv6

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 Logic Design
 Introduction to number systems – Arithmetic Operations

Augend: 101101 Minuend: 101101 Multiplicand: 1011

Addend: + 100111 Subtrahend: - 100111 Multiplier: * 101
Sum: 1010100 Difference: 000110 1011
Rules of Binary Addition Rules of Binary Subtraction 0000
0+0=0 0-0=0 1011
1+0=1 1-0=1 Product: 110111
0+1=1 0-1=1 (With a borrow 1)
1+1= 10 1-1= 0
1+1+1 = 11

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 Logic Design
 Introduction to number systems – Number Base Conversions

1. (1010.011)2 = (___________)10

= (10.375)10

2. (630.4)8 = (___________)10

= (408.5)10

3. (41)10 = (___________)2

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= (101001)2 07/03/2024 16
 Logic Design
 Introduction to number systems – Number Base Conversions

4. (746)10 = (___________)2

= (1011101010)2

5. (153)10 = (___________)8

= (231)8

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 Logic Design
 Introduction to number systems – Number Base Conversions

6. Convert (0.6875)10 = (___________)2

Integer Fraction Coefficient
0.6875*2= 1 + 0.3750 1
0.3750*2= 0 + 0.7500 0
0.7500*2= 1 + 0.5000 1
0.5000*2= 1 + 0.0000 1

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 Logic Design
 Introduction to number systems – Number Base Conversions

6. Convert (0.513)10 = (___________)8

Integer Fraction Coefficient
0.513*8= 4 + 0.104 4
0.104*8= 0 + 0.832 0
0.832*8= 6 + 0.656 6
0.656*8= 5 + 0.248 5
0.248*8= 1 + 0.984 1
0.984*8= 7 + 0.872 7

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 Logic Design
 Introduction to number systems – Number Base Conversions

8. Convert (41.6875)10 = (___________)2

(41.6875)10 = (101001.1011)2

9. Convert (153.513)10 = (___________)8

(153.513)10 = (231.406517)8

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 Logic Design
 Introduction to number systems

 Octal & Hexadecimal

 Hexadecimal, often referred to as hex (r=16) and octal numbers as Oct (r=8) is another base that is
commonly used in computer documentation.
 In hexadecimal, binary digits are grouped in Fours (starting at the least significant). A-10, B-11, C-12, D-
13,E-14, F-15
 In Octal, binary digits are grouped in Threes (starting at the least significant).
(10110001101011.111100000110)2 = (_________________________)8
10 110 001 101 011 . 111 100 000 110
2 6 1 5 3 7 4 0 6

(10110001101011.111100000110)2 = (_________________________)16
10 1100 0110 1011 . 1111 0000 0110
2 C 6 B F 0 6
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 Logic Design
 Introduction to number systems

 Octal & Hexadecimal

(673.124)8 = (_________________________)2
110 111 011 . 001 010 100
6 7 3 1 2 4

(306.D)16 = (_________________________)2
0011 0000 0110 . 1101
3 0 6 D

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 Logic Design
 Introduction to number systems

 Octal & Hexadecimal

10. Convert (1011101010)2 = (_________________________)16

0010 1110 1010 = (2EA)16

11. Convert (2EA)16 = (_________________________)10

(2EA)16 = 2*162 + 14*161 + 10*160 = (746)10

12. Convert (746)10 = (_____________________________)16

746/16 = 46 remainder 10 produces A
46/16 = 2 remainder 14
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EA 07/03/2024 23
 Logic Design
 Introduction to number systems
Write an alp to perform addition on various types data
.model small ;model of type small, CS<=64K &DS<=64K
.data ;indicates start of data segment
n1 db 12h ;hexa decimal data
n2 db 16 ; decimal data, 10H in hexa decimal
sum db ? ; reserves 1byte mem location to store the result

.code ; start of code segment

mov ax,@data
mov ds,ax ; data segment initialization
mov al,n1 ; first data stored in mem moved to al
add al,n2 ; add the contents of al & n2 (10h) & store result in the al
mov sum, al ; store the result in mem as sum
mov ah,4ch ; to terminate the pgm
int 21h
end ; assembler directive, tells the assembler ,this is end of the pgm

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 Logic Design
 Introduction to number systems - COMPLEMENTS

 Complements are used in digital computers for simplifying the subtraction operation and for logical
manipulation.
 There are two types of complements for each base-r system:
i. The RADIX complement – referred to as r’s complement
ii. Diminished RADIX complement – referred to as (r-1)’s complement
 If base, r=2  RADIX complement – referred to as 2’s complement for binary
Diminished RADIX complement – referred to as 1’s complement for binary
 If base, r=10  RADIX complement – referred to as 10’s complement for decimal numbers
Diminished RADIX complement – referred to as 9’s complement decimal numbers

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 Logic Design
 Introduction to number systems – DIMINISHED RADIX COMPLEMENTS

 Diminished RADIX complement – referred to as (r-1)’s complement

 If base, r=10  Diminished RADIX complement – referred to as 9’s complement decimal numbers.
 9’s complement decimal number is obtained by SUBTRACTING each digit from 9.
 Example 1- 9 ‘s complement of 546700 is:
999999 - 546700 = 453299
 Example 2- 9 ‘s complement of 012398 is:
999999 - 012398 = 987601
 Exercise 1- 9 ‘s complement of 8976523
9999999 – 8976523 = 1023476
 Exercise 2- 9 ‘s complement of 521987634
999999999 – 521987634 = 478012365

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 Logic Design
 Introduction to number systems – DIMINISHED RADIX COMPLEMENTS

 If base, r=2  Diminished RADIX complement – referred to as 1’s complement binary.

 1’s complement of a binary number is obtained by SUBTRACTING each digit from 1.
 Example 1- 1 ‘s complement of 1011000 is: 1111111 - 1011000 = 0100111
 Example 2- 1 ‘s complement of 0101101 is: 1111111 - 0101101 = 1010010
 Exercise 1- 1 ‘s complement of 11001010
11111111 – 11001010 = 00110101
 Exercise 2- 1 ‘s complement of 011011
111111 – 011011 =100100
 11001010  00110101
 011011  100100
 Therefore, the 1’s complement of binary number is formed by changing 1’s to 0’s and 0’s to 1’s.

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 Logic Design
 Introduction to number systems – RADIX COMPLEMENTS

 RADIX complement – referred to as r’s complement

 If base, r=10  RADIX complement – referred to as 10’s complement decimal numbers.
 10’s complement of a decimal number is obtained by SUBTRACTING each digit from 9 and adding 1 to the
9’s complement value.
 Example 1- 10 ‘s complement of 546700 is:
999999 - 546700 = 453299 + 1 = 453300
 Example 2- 10 ‘s complement of 012398 is:
999999 - 012398 = 987601 + 1 = 987602
 Exercise 1- 10 ‘s complement of 8976523
9999999 – 8976523 = 1023476 + 1 = 1023477
 Exercise 2- 10 ‘s complement of 521987634
999999999 – 521987634 = 478012365 + 1 = 478012366
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 Logic Design
 Introduction to number systems – RADIX COMPLEMENTS

 If base, r=2  RADIX complement – referred to as 2’s complement decimal numbers.

 2’s complement of a binary number is obtained by SUBTRACTING each digit from 1 and adding 1 to the 1’s
complement value.
 Example 1- 2 ‘s complement of 1011000 is:
1111111 - 1011000 = 0100111 + 1 = 0101000
 Example 2- 2 ‘s complement of 0101101 is:
1111111 - 0101101 = 1010010 + 1 = 1010011
 Exercise 1- 2 ‘s complement of 11001010
11111111 – 11001010 = 00110101 + 1 = 00110110
 Exercise 2- 2 ‘s complement of 011011
111111 – 011011 =100100 + 1 = 100101

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 Logic Design
 PROBLEM 1:
 Using 10’s complement, subtract 72532 – 3250
M = 72532, N = 3250
10’s complement of subtrahend, N: 3250
First perform 9’s complement of subtrahend : 99999 – 03250 = 96749
Therefore, 10’s complement of subtrahend, N = 3250 is: 96749 + 1 = 96750
Then, M = 72532
10’s complement of N = + 96750
Sum = 169282
Discard the end carry 105 = - 100000
Answer = 69282

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 Logic Design
 PROBLEM 2:
 Using 10’s complement, subtract 82641 – 6370
M = 82641, N = 6370
10’s complement of subtrahend, N: 6370
First perform 9’s complement of subtrahend : 99999 – 06370 = 93629
Therefore, 10’s complement of subtrahend, N = 6370 is: 93629 + 1 = 93630
Then, M = 82641
10’s complement of N = + 93630
Sum = 176271
Discard the end carry 105 = - 100000
Answer = 76271

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 Logic Design
 PROBLEM 3:
 Using 10’s complement, subtract 882641 – 68370
M = 882641, N = 68370
10’s complement of subtrahend, N: 68370
First perform 9’s complement of subtrahend : 999999 – 068370 = 931629
Therefore, 10’s complement of subtrahend, N = 68370 is: 93629 + 1 = 931630
Then, M = 882641
10’s complement of N = + 931630
Sum = 1814271
Discard the end carry 106 = - 1000000
Answer = 814271

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 Logic Design
 PROBLEM 4:
 Using 10’s complement, subtract 3250 – 72532
M = 3250, N = 72532
10’s complement of subtrahend, N: 72532
First perform 9’s complement of subtrahend : 99999 – 72532 = 27467
Therefore, 10’s complement of subtrahend, N = 72532 is: 27467 + 1 = 27468
Then, M = 03250
10’s complement of N = + 27468
Sum = 30718
There is no end carry
Answer: -(10’s complement of 30718)
i.e, - (99999 – 30718 + 1)
Answer = -69282
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 Logic Design
 PROBLEM 5:
 Using 10’s complement, subtract 68370 - 882641
M = 68370, N = 882641
10’s complement of subtrahend, N: 882641
First perform 9’s complement of subtrahend : 999999 – 882641 = 117358
Therefore, 10’s complement of subtrahend, N = 882641 is: 117358 + 1 = 117359
Then, M = 68370
10’s complement of N = + 117359
Sum = 185729
There is no end carry
Answer: -(10’s complement of 185728)
i.e, - (999999 – 185729 + 1)
Answer = -814271
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 Logic Design
 PROBLEM 6:
 Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction:
i) X - Y ii) Y – X using 2’s complements.

i) X – Y
Step 1: Take 2’s complement of Y
Given Y= 1000011
2’s complement of Y = 0111100 + 1 = 0111101
X= 1010100
2’s complement of Y = + 0111101
Sum = 10010001
Discard end carry by 27 = -10000000
DEPT. OF ECE, NIE MYSURU
Answer: X – Y = 0010001 07/03/2024 35
 Logic Design
 PROBLEM 6:
 Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction:
i) X - Y ii) Y – X using 2’s complements.

ii) Y – X
Step 1: Take 2’s complement of X
Given X= 1010100
2’s complement of X = 0101011 + 1 = 0101100
Y= 1000011
2’s complement of X = + 0101100 ANSWER: Y - X = - (2’s complement of 1101111)
= - (0010000 + 1)
ANSWER: Y - X = - (0010001)
Sum = 1101111
There is no end carry
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 Logic Design
 PROBLEM 7:
 Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction:
i) X - Y ii) Y – X using 1’s complements.

i) X – Y
Step 1: Take 1’s complement of Y
Given Y= 1000011
1’s complement of Y = 0111100
X= 1010100
1’s complement of Y = + 0111100
Sum = 10010000
End around carry= + 1
DEPT. OF ECE, NIE MYSURU
Answer: X – Y = 0010001 07/03/2024 37
 Logic Design
 PROBLEM 7:
 Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction:
i) X - Y ii) Y – X using 1’s complements.

ii) Y – X
Step 1: Take 1’s complement of X
Given X= 1010100
1’s complement of X = 0101011
Y= 1000011
1’s complement of X = + 0101011 ANSWER: Y - X = - (1’s complement of 1101110)
ANSWER: Y - X = - (0010001)
Sum = 1101110
There is no end carry
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 Logic Design
 SELF LEARNING TOPIC
 SIGNED BINARY NUMBERS
 BINARY CODES

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 Boolean Algebra
 Boolean Algebra: Basic Definitions
 Boolean algebra , like any other deductive mathematical system, is defined by:
i. A set of elements
ii. A set of operators and
iii. A number of unproved axioms and postulates
 If ‘S’ is a set, and X and Y are certain objects, then X ⋲ S indicates X is a member of S and Y ∉ S indicates Y is
not an element of S.
 A set S = { 1, 2, 3, 4}
 The postulates of a mathematical system form the basic assumptions from which it is possible to deduce the
rules, theorems and properties of the system.
 The most common postulates used to formulate various algebraic structures are:
 Closure, Associative law, Commutative law, Identity element, Inverse and Distributive law

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 Boolean Algebra
 Boolean Algebra: Basic Definitions
 Closure:
 A set S is closed w.r.t a binary operator.
 Binary operator specifies a rule for obtaining a unique element.
 Example: N= {1,2,3,4………} is closed w.r.t the binary operator (+) by the rules of arithmetic addition.
 Because for any a, b ⋲ N we obtain a unique c ⋲ N i.e, a + b = c
 The set of natural numbers is not closed w.r.t the binary operator (-) by the rules of arithmetic subtraction.
 Because 2-3= -1 and 2,3 ⋲ N while (-1) ∉ N
 Associative law:
 A binary operator * on a set S is said to be associative if
(x * y) * z = x * (y * z) for all x, y, z ⋲ S

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 Boolean Algebra
 Boolean Algebra: Basic Definitions
 Commutative law:
 A binary operator * on a set S is said to be commutative if
x*y=y*x for all x, y ⋲ S
 Identity element:
 A set S is said to have an identity element w.r.t binary operator * on a set S if there exists an element e ⋲ S
with the property
e*x=x*e=x for all x ⋲ S
Example: the element 0 is an identity element w.r.t operation + on the set of integers
I = {…………-3, -2, -1, 0, 1, 2, 3 ……….} since x + 0 = 0 + x = x for all x ⋲ I

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 Boolean Algebra
 Boolean Algebra: Basic Definitions
 Inverse:
 A set S having the identity element e w.r.t a binary operator * is said to have an inverse whenever,
x*y=e
Example: in the set of integers I with e=0, the inverse of an element a is (-a) since a + (-a) = 0
 Distributive Law:
 If ⋆ and • are two binary operators on a set S, ⋆ is said to be distributive over •
x ⋆ ( y • z ) = (x ⋆ y) • (x ⋆ z)

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 Boolean Algebra
 Boolean Algebra: Axiomatic Definition of Boolean Algebra
 In 1854 George Boole introduced a systematic treatment of logic and developed an algebraic system which is
called as BOOLEAN ALGEBRA.
 In 1938, Claude. E. Shannon introduced a TWO VALUED Boolean algebra called a s SWITCHING ALGEBRA.
 Boolean algebra is an algebraic structure defined on a set of elements B together with two binary operators +
and • provided the following postulates are satisfied:
1. (a) closure w.r.t to the operator + and •
2. (a) An identity element w.r.t + , designated by 0: x+0=0+x=x
(b) An identity element w.r.t • , designated by 1: x • 1=1 • x=x
3. (a) commutative w.r.t +: x+y=y+x
(b) commutative w.r.t • : x • y=y • x

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 Boolean Algebra
 Boolean Algebra: Axiomatic Definition of Boolean Algebra
4. (a) • distributive over +: x •(y+z)= (x • y) + (x • z)
(b) + distributive over • : x +(y • z)= (x + y) • (x + z)
5. For every element x⋲ B, there exists an element x΄⋲B (Complement of x) such that:
x+x΄=1 and x • x΄ = 0
6. There exists atleast two elements x, y ⋲ B such that x≠y

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 Boolean Algebra
 Boolean Algebra: Axiomatic Definition of Boolean Algebra
 Two valued Boolean Algebra

x y x•y x y x+y x x΄
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1

 These rules are exactly the same as that of AND, OR and NOT operations
 Closure is obvious from the tables since the result of each operation is either 1 or 0 and 1, 0 ⋲ B
 From the table it can be seen that: a) 0 + 0 = 0 ; 0 + 1 = 1 + 0 = 1
b) 1 • 1 = 1 ; 1 • 0=0 • 1=0
 The commutative laws are obvious from the symmetry of the binary operator table.

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 Boolean Algebra
 Boolean Algebra: Axiomatic Definition of Boolean Algebra
 Two valued Boolean Algebra
 The distributive law: x •(y+z)= (x • y) + (x • z)

x y z y+z x • ( y+z ) x•y x•z ( x • y )+( x • z )

0 0 0 0 0 0 0 0

0 0 1 1 0 0 0 0

0 1 0 1 0 0 0 0

0 1 1 1 0 0 0 0

1 0 0 0 0 0 0 0

1 0 1 1 1 0 1 1

1 1 0 1 1 1 0 1

1 1 1 1 1 1 1 1

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 Boolean Algebra
 Boolean Algebra: Basic Theorems and Properties of Boolean Algebra

Postulates and Theorems of Boolean Algebra

Postulate 2 a) x + 0 = x b) x •1 = x
Postulate 5 a) x + x΄ = 1 b) x • x΄ = 0
Theorem 1 a) x + x = x b) x • x = x
Theorem 2 a) x + 1 = 1 b) x • 0 = 0
Theorem 3, Involution (x΄)΄ = x
Postulate 3, Commutative a) x + y = y + x b) x y = y x
Theorem 4, Associative a) x+(y+z) = (x+y)+z b) x(yz) = (xy)z
Postulate 4, Distributive a) x(y+z) = xy+xz b) x+yz = (x+y)(x+z)
Theorem 5, DeMorgan a) (x+y)΄ = x΄y΄ b) (xy)΄ = x΄+ y΄
Theorem 6, Absorption a) x+xy = x b) x(x+y)=x

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 Boolean Algebra
 Boolean Algebra: Basic Theorems and Properties of Boolean Algebra

 Theorems
1. x+x=x
2. x•x=x
3. x+1=1
4. x•0=0
5. (x΄)΄ = x
6. x + xy=x
7. x(x+y)=x

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 Half Adder
 Half Adder in Digital Logic

 Half adder is the simplest of all adder circuits.

 Half adder is a combinational arithmetic circuit that adds two numbers and produces a sum bit (s) and
carry bit (c) both as output.

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 Half Adder
 Half Adder in Digital Logic – K Map

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 Half Adder
 Half Adder in Digital Logic

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 Half Adder
 Half Adder in Digital Logic

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 Half Adder
 Half Adder in Digital Logic

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 Half Adder
 Half Adder in Digital Logic

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 Half Adder
 Half Adder in Digital Logic

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 Half Adder
 Half Adder in Digital Logic

Limitations: Adding of Carry is not possible in Half adder.

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 Full Adder
 Full Adder in Digital Logic

 To overcome the above limitation faced with Half adders, Full Adders are implemented.
 It is an arithmetic combinational logic circuit that performs addition of three single bits.
 It contains three inputs (A, B, Cin) and produces two outputs (Sum and Cout).

 Where, Cin -> Carry In and Cout -> Carry Out

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 Full Adder
 Full Adder in Digital Logic: K Map

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 Full Adder
 Full Adder in Digital Logic

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 Full Adder
 Full Adder in Digital Logic

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 Full Adder
 Full Adder in Digital Logic

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 Multiplexer
 Multiplexer

 A multiplexer or MUX, also called a data selector, is a combinational circuit with more than one input line,
one output line and more than one selection line.
 There are some multiplexer ICs that provide complementary outputs.
 Also, multiplexers in IC form almost invariably have an ENABLE or STROBE input, which needs to be active
for the multiplexer to be able to perform its intended function.
 A multiplexer selects binary information present on any one of the input lines, depending upon the logic
status of the selection inputs, and routes it to the output line.
 If there are n selection lines, then the number of maximum possible input lines is 2 n and the multiplexer is
referred to as a 2n-to-1 multiplexer or 2n × 1 multiplexer.

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 Multiplexer
 Multiplexer
 In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line, i.e., S0 and single outputs, i.e., Y.
 On the basis of the combination of inputs which are present at the selection line S 0, one of these 2 inputs will
be connected to the output.
 The block diagram and the truth table of the 2×1 multiplexer are given below

 For S = 0, the Boolean expression for the output becomes Y = I 0.

 For S = 1, the Boolean expression for the output becomes Y = I 1.

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 Multiplexer
 Multiplexer
 The logical expression of the term Y is as follows:
Y=S0'.A0+S0.A1

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 Multiplexer
 Multiplexer
 In the 4×1 multiplexer, there is a total of four inputs, i.e., A 0, A1, A2, and A3, 2 selection lines, i.e., S0 and S1 and
single output, i.e., Y.
 On the basis of the combination of inputs that are present at the selection lines S 0 and S1, one of these 4
inputs are connected to the output.
 The block diagram and the truth table of the 4×1 multiplexer are given below.

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 Multiplexer
 Multiplexer
 The logical expression of the term Y is as follows:
Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

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 Multiplexer
 Multiplexer

 In the 8 to 1 multiplexer, there are total eight inputs, i.e., A 0, A1, A2, A3, A4, A5, A6, and A7, 3 selection lines, i.e.,

S0, S1and S2 and single output, i.e., Y.

 On the basis of the combination of inputs that are present at the selection lines S 0, S1, and S2, one of these 8
inputs are connected to the output.
 The block diagram and the truth table of the 8×1 multiplexer are given below.

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 Multiplexer
 Multiplexer

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 Multiplexer
 Multiplexer
The logical expression of the term Y is as follows:
Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2 .A6+S0.S1.S3.A7

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 Multiplexer
 Demultiplexer

 A De-multiplexer is a combinational circuit that has only 1 input line and 2 N output lines.
 Simply, the multiplexer is a single-input and multi-output combinational circuit.
 The information is received from the single input lines and directed to the output line.
 On the basis of the values of the selection lines, the input will be connected to one of these outputs.
 De-multiplexer is opposite to the multiplexer.
 Unlike encoder and decoder, there are n selection lines and 2n outputs. So, there is a total of 2n possible
combinations of inputs. De-multiplexer is also treated as De-mux.

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 Multiplexer
 Demultiplexer

 In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y 0, and Y1, 1 selection lines, i.e., S0, and single
input, i.e., A.
 On the basis of the selection value, the input will be connected to one of the outputs.
 The block diagram and the truth table of the 1×2 multiplexer are given below.

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 Multiplexer
 Demultiplexer

The logical expression of the term Y is as follows:

Y0=S0'.A
Y1=S0.A

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 Multiplexer
 Demultiplexer
 In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y 0, Y1, Y2, and Y3, 2 selection lines, i.e., S0 and

S1 and single input, i.e., A.

 On the basis of the combination of inputs which are present at the selection lines S 0 and S1, the input be
connected to one of the outputs. T
 he block diagram and the truth table of the 1×4 multiplexer are given below.

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 Multiplexer
 Demultiplexer

The logical expression of the term Y is as follows:

Y0=S1'S0'A
y1=S1'S0A
y2=S1S0'A
y3=S1 S0 A

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 Multiplexer
 Demultiplexer

 In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7, 3 selection lines,

i.e., S0, S1and S2 and single input, i.e., A.

 On the basis of the combination of inputs which are present at the selection lines S 0, S1 and S2, the input will
be connected to one of these outputs.
 The block diagram and the truth table of the 1×8 de-multiplexer are given below.

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 Multiplexer
 Demultiplexer

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 Multiplexer
 Demultiplexer

The logical expression of the term Y is as follows:

Y0=S0'.S1'.S2’.A
Y1=S0.S1'.S2’.A
Y2=S0'.S1.S2’.A
Y3=S0.S1.S2'.A
Y4=S0'.S1’.SA
Y5=S0.S1'.S2A
Y6=S0'.S1.S2A
Y7=S0.S1.S3.A

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 Encoders
 Encoders
 An encoder is a multiplexer without its single output line.
 It is a combinational logic function that has 2 n (or fewer) input lines and n output lines, which correspond to
‘n’ selection lines in a multiplexer.
 The ‘n’ output lines generate the binary code for the possible 2n input lines.
 Let us take the case of an octal-to-binary encoder.
 Such an encoder would have eight input lines, each representing an octal digit, and three output lines
representing the three-bit binary equivalent.

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 Encoders
 Encoders
 In 4 to 2 line encoder, there are total of four inputs, i.e., Y 0, Y1, Y2, and Y3, and two outputs, i.e., A0 and A1.
 In 4-input lines, one input-line is set to true at a time to get the respective binary code in the output side.
 Below are the block diagram and the truth table of the 4 to 2 line encoder.

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 Encoders
 Encoders
The logical expression of the term A0 and A1 is as follows:
A1=Y3+Y2
A0=Y3+Y1

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 Encoders
 Encoders

 8 to 3 line Encoder:
 The 8 to 3 line Encoder is also known as Octal to Binary Encoder.
 In 8 to 3 line encoder, there is a total of eight inputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs,

i.e., A0, A1, and A2. In 8-input lines, one input-line is set to true at a time to get the respective binary code in
the output side.
 Below are the block diagram and the truth table of the 8 to 3 line encoder.

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 Encoders
 Encoders

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 Encoders
 Encoders
 The logical expression of the term A0, A1, and A2 are as follows:
A2=Y4+Y5+Y6+Y7
A1=Y2+Y3+Y6+Y7
A0=Y7+Y5+Y3+Y1

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 Encoders
 Priority Encoders
 A priority encoder is a practical form of an encoder.
 In this type of encoder, a priority is assigned to each input so that, when more than one input is simultaneously
active, the input with the highest priority is encoded.

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 Encoders
 Priority Encoders

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 Decoders
 Decoders

 The combinational circuit that change the binary information into 2 N output lines is known as Decoders.
 The binary information is passed in the form of N input lines.
 The output lines define the 2N-bit code for the binary information. In simple words, the Decoder performs the
reverse operation of the Encoder.
 At a time, only one input line is activated for simplicity. The produced 2 N-bit output code is equivalent to the
binary information.

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 Decoders
 Decoders

 In the 2 to 4 line decoder, there is a total of three inputs, i.e., A 0, and A1 and E and four outputs, i.e., Y0, Y1, Y2,

and Y3.
 For each combination of inputs, when the enable 'E' is set to 1, one of these four outputs will be 1.
 The block diagram and the truth table of the 2 to 4 line decoder are given below.

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 Decoders
 Decoders

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 Decoders
 Decoders
The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:
Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0’

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 Decoders
 Decoders

 The 3 to 8 line decoder is also known as Binary to Octal Decoder.

 In a 3 to 8 line decoder, there is a total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e.,

A0, A1, and A2.

 This circuit has an enable input 'E'. Just like 2 to 4 line decoder, when enable 'E' is set to 1, one of these four
outputs will be 1. The block diagram and the truth table of the 3 to 8 line encoder are given below.

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 Decoders
 Decoders

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 Decoders
 Decoders
 The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:

Y0=A0'.A1'.A2’ Y1=A0.A1'.A2’ Y2=A0'.A1.A2’ Y3=A0.A1.A2'

Y4=A0'.A1’.A2 Y5=A0.A1’.A2 Y6=A0'.A1.A2 Y7=A0.A1.A2

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 Sequential Circuits
 Sequential Circuits
 The sequential circuit is a special type of circuit that has a series of inputs and outputs.
 The outputs of the sequential circuits depend on both the combination of present inputs and previous
outputs.
 The previous output is treated as the present state. So, the sequential circuit contains the combinational
circuit and its memory storage elements.
 A sequential circuit doesn't need to always contain a combinational circuit. So, the sequential circuit can
contain only the memory element.

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 Sequential Circuits
 Types of Sequential Circuits:
 Asynchronous sequential circuits:
 The clock signals are not used by the Asynchronous sequential circuits.
 The asynchronous circuit is operated through the pulses.
 So, the changes in the input can change the state of the circuit.
 The asynchronous circuits do not use clock pulses.
 The internal state is changed when the input variable is changed.
 The un-clocked flip-flops or time-delayed are the memory elements of asynchronous sequential circuits.
 The asynchronous sequential circuit is similar to the combinational circuits with feedback.

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 Sequential Circuits
 Types of Sequential Circuits:
 Synchronous sequential circuits:
 In synchronous sequential circuits, synchronization of the memory element's state is done by the clock
signal.
 The output is stored in either flip-flops or latches(memory devices).
 The synchronization of the outputs is done with either only negative edges of the clock signal or only
positive edges.

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 Sequential Circuits
 Clock Signal and Trigerring
 Clock Signal
 A clock signal is a periodic signal in which ON time and OFF time need not be the same.
 When ON time and OFF time of the clock signal are the same, a square wave is used to represent the clock
signal. Below is a diagram which represents the clock signal:

 A clock signal is considered as the square wave. Sometimes, the signal stays at logic, either high 5V or low 0V,
to an equal amount of time.
 It repeats with a certain time period, which will be equal to twice the 'ON time' or 'OFF time'.

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 Sequential Circuits
 Clock Signal and Triggerring

 Types of Triggering
 These are two types of triggering in sequential circuits:
 Level triggering
 The logic High and logic Low are the two levels in the clock signal.
 In level triggering, when the clock pulse is at a particular level, only then the circuit is activated.
 There are the following types of level triggering:

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 Sequential Circuits

 Clock Signal and Triggerring

 Types of Triggering
 Positive level triggering
 In a positive level triggering, the signal with Logic High occurs.
 So, in this triggering, the circuit is operated with such type of clock signal. Below is the diagram of positive
level triggering:

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 Sequential Circuits
 Clock Signal and Triggerring

 Types of Triggering
 Negative level triggering
 In negative level triggering, the signal with Logic Low occurs.
 So, in this triggering, the circuit is operated with such type of clock signal.
 Below is the diagram of Negative level triggering:

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 Sequential Circuits
 Clock Signal and Triggerring

 Types of Triggering
 Edge triggering
 In clock signal of edge triggering, two types of transitions occur, i.e., transition either from Logic Low to Logic
High or Logic High to Logic Low.
 Based on the transitions of the clock signal, there are the following types of edge triggering
 Positive Edge Triggering
 Negative Edge Triggering

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 Sequential Circuits
 Clock Signal and Triggerring

 Types of Triggering
 Positive Edge triggering
 The transition from Logic Low to Logic High occurs in the clock signal of positive edge triggering.
 So, in positive edge triggering, the circuit is operated with such type of clock signal.
 The diagram of positive edge triggering is given below.

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 Sequential Circuits
 Clock Signal and Triggerring

 Types of Triggering
 Negative Edge triggering
 The transition from Logic High to Logic low occurs in the clock signal of negative edge triggering.
 So, in negative edge triggering, the circuit is operated with such type of clock signal.
 The diagram of negative edge triggering is given below.

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 Flip Flops
 Latches and Flip Flops

 Latches
 Latches are basic storage elements that operate with signal levels (rather than signal transitions).
 Latches controlled by a clock transition are flip-flops.
 Latches are level-sensitive devices.
 Latches are useful for the design of the asynchronous sequential circuit.
 Latches are sequential circuit with two stable states.
 These are sensitive to the input voltage applied and does not depend on the clock pulse.
 Flip flops that do not use clock pulse are referred to as latch.

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 Flip Flops
 Latches and Flip Flops

 SR Latches
 S-R latches i.e., Set-Reset latches are the simplest form of latches and are implemented using two inputs: S
(Set) and R (Reset).
 The S input sets the output to 1, while the R input resets the output to 0. When both S and R inputs are at 1,
the latch is said to be in an “undefined” state.
 They are also known as preset and clear states. The SR latch forms the basic building blocks of all other types
of flip-flops.
 SR Latch is a logic circuit with:
 2 cross-coupled NOR gate or 2 cross-coupled NAND gate.
 2 input S for SET and R for RESET
 2 output Q, Q’.

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 Flip Flops
 Latches and Flip Flops

 SR Latches

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 Flip Flops
 Latches and Flip Flops

 SR Latches using NAND gates

 In this circuit we are applying set to the upper NAND gate and reset to the lower NAND gate and Q and Q ̅
represents the output of the latch. The circuit will be set when the Q = 1 and the circuit will be reset when
the Q = 0.

S R Q Q ̅

0 0 Not used

0 1 1 0

1 0 0 1

Previous
1 1
state

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 Flip Flops
 Latches and Flip Flops

 SR Latches using NAND gates

1. SET = RESET = 0 is forbidden as such a condition tries to set (that is, Q = 1 ) and reset (that is, Q’ = 1) the
latch at the same time. To be more precise, SET and RESET inputs in the R-S flip-flop cannot be active at the same
time.
2. SET = 0 and RESET = 1 sets the latch. Q and Q’ respectively go to the ‘1’ and ‘0’ state.
3. SET = 1 and RESET = 0 resets or clears the latch. Q and Q’ respectively go to the ‘0’ and ‘1’ state.
4. SET = RESET = 1 is the normal resting condition of the latch. It has no effect on the output state of the
latch. both Q and Q’ outputs remain in the logic state they were in prior to this input condition.

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 Flip Flops
 Flip Flops
 Flip-Flop is a term that comes under digital electronics, and it is an electronic component that is used to store
one single bit of information.
 Since Flip Flop is a sequential circuit so its input is based upon two parameters, one is the current input and
other is the output from previous state. It has two outputs, both are complement of each other. It may be in
one of two stable states, either 0 or 1.

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 Flip Flops
 Flip Flops: SR
 The logical circuit ,truth table and function table of the SR flip flop is shown below:
 Here, S is the Set input, R is the reset input.

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 Flip Flops
 Flip Flops: SR
 This is the most common flip-flop among all.
 This simple flip-flop circuit has a set input (S) and a reset input (R).
 The basic block diagram contains S and R inputs, and between them is clock pulse, Q and Q’ is the
complemented outputs.

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 Flip Flops
 Flip Flops: SR
1. SET = RESET = 1 is the normal resting condition of the flip-flop. It has no effect on the output state of the flip-
flop. both Q and Q’ outputs remain in the logic state they were in prior to this input condition.
2. SET = 0 and RESET = 1 sets the flip-flop. Q and Q’ respectively go to the ‘1’ and ‘0’ state.
3. SET = 1 and RESET = 0 resets or clears the flip-flop. Q and Q’ respectively go to the ‘0’ and ‘1’ state.
4. SET = RESET = 0 is forbidden as such a condition tries to set (that is, Q = 1 ) and reset (that is, Q’ = 1) the flip-
flop at the same time. To be more precise, SET and RESET inputs in the R-S flip-flop cannot be active at the same
time.

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 Flip Flops
 Flip Flops: JK
 Due to the undefined state in the SR flip-flops, another flip-flop is required in electronics.
 The JK flip-flop is an improvement on the SR flip-flop where S=R=1 is not a problem.
 The JK flip flop is used to remove the drawback of the S-R flip flop, i.e., undefined states.
 The JK flip flop is formed by doing modification in the SR flip flop. The S-R flip flop is improved in order to
construct the J-K flip flop.
 When S and R input is set to true, the SR flip flop gives an inaccurate result. But in the case of JK flip flop, it
gives the correct output.

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 Flip Flops
 Flip Flops: D
 D flip flop is an electronic devices that is known as “delay flip flop” or “data flip flop” which is used to store
single bit of data
 The D flip flop has two inputs, data and clock input which controls the flip flop. when clock input is high, the
data is transferred to the output of the flip flop and when the clock input is low, the output of the flip flop is
held in its previous state.

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 Flip Flops
 Flip Flops: D
 A D flip-flop, also called a delay flip-flop, can be used to provide temporary storage of one bit of information.

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 Flip Flops
 Flip Flops: T
 The output of a toggle flip-flop, also called a T flip-flop, changes state every time it is triggered at
 its T input, called the toggle input. That is, the output becomes ‘1’ if it was ‘0’ and ‘0’ if it was ‘1’.

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 Counters
 Counters:

 A Counter is a device which stores (and sometimes displays) the number of times a particular event or
process has occurred, often in relationship to a clock signal.
 Counters are used in digital electronics for counting purpose, they can count specific event happening in the
circuit. For example, in UP counter a counter increases count for every rising edge of clock.
 Not only counting, a counter can follow the certain sequence based on our design like any random sequence
0,1,3,2… .
 They can also be designed with the help of flip flops.
 They are used as frequency dividers where the frequency of given pulse waveform is divided.
 Counters are sequential circuit that count the number of pulses can be either in binary code or BCD form.
 The main properties of a counter are timing , sequencing , and counting.

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 Asynchronous Binary Up Counter: Counters

 An ‘N’ bit Asynchronous binary up counter consists of ‘N’ T flip-flops. It counts from 0 to 2 𝑁 − 1. The block
diagram of 3-bit Asynchronous binary up counter is shown in the following figure.
 The 3-bit Asynchronous binary up counter contains three T flip-flops and the T-input of all the flip-flops
are connected to ‘1’.
 All these flip-flops are negative edge triggered but the outputs change asynchronously. The clock signal is
directly applied to the first T flip-flop. So, the output of first T flip-flop toggles for every negative edge of
clock signal.

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 Counters
 Counters:
 Counter works in two modes
 Up counter
 Down counter
 Counters are broadly divided into two categories
 Asynchronous counter
 Synchronous counter

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 Asynchronous Binary Up Counter: Counters

 The output of first T flip-flop is applied as clock signal for second T flip-flop. So, the output of second T flip-
flop toggles for every negative edge of output of first T flip-flop.
 Similarly, the output of third T flip-flop toggles for every negative edge of output of second T flip-flop, since
the output of second T flip-flop acts as the clock signal for third T flip-flop.
 Assume the initial status of T flip-flops from rightmost to leftmost is 𝑄2𝑄1𝑄0=000
 Here, 𝑄2 and𝑄1 are MSB & LSB respectively. We can understand the working of 3-bit asynchronous binary
counter from the following table.

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 Asynchronous Binary Up Counter: Counters

 Here Q0𝑄0 toggled for every negative edge of clock

signal.
 Q1𝑄1 toggled for every Q0𝑄0 that goes from 1 to 0,
otherwise remained in the previous state.
Similarly, Q2𝑄2 toggled for every Q1𝑄1 that goes
from 1 to 0, otherwise remained in the previous state.
 The initial status of the T flip-flops in the absence of
clock signal is Q2Q1Q0=000.
 This is incremented by one for every negative edge of
clock signal and reached to maximum value at
7th negative edge of clock signal.
 This pattern repeats when further negative edges of
clock signal are applied.
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 Asynchronous Binary Up Counter: Counters

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 Asynchronous Binary Down Counter: Counters

 An ‘N’ bit Asynchronous binary down counter consists of ‘N’ T flip-flops. It counts from 2 𝑁 − 1 to 0.
 The block diagram of 3-bit Asynchronous binary down counter is shown in the following figure.
 The block diagram of 3-bit Asynchronous binary down counter is similar to the block diagram of 3-bit
Asynchronous binary up counter.

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 Asynchronous Binary Down Counter: Counters

 But, the only difference is that instead of connecting the normal outputs of one stage flip-flop as clock signal for
next stage flip-flop, connect the complemented outputs of one stage flip-flop as clock signal for next stage flip-
flop.
 Complemented output goes from 1 to 0 is same as the normal output goes from 0 to 1.
 Assume the initial status of T flip-flops from rightmost to leftmost is Q2Q1Q0=000. Here, Q2 & Q0 are MSB & LSB
respectively.
 We can understand the working of 3-bit asynchronous binary down counter from the following table.

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 Asynchronous Binary Down Counter: Counters

 Here Q0 toggled for every negative edge of clock

signal. Q1 toggled for every Q0 that goes from 0 to 1,
otherwise remained in the previous state.
 Similarly, Q2 toggled for every 𝑄1 that goes from 0 to 1,
otherwise remained in the previous state.
 The initial status of the T flip-flops in the absence of clock
signal is Q2Q1Q0=000.
 This is decremented by one for every negative edge of
clock signal and reaches to the same value at 8th negative
edge of clock signal.
 This pattern repeats when further negative edges of clock
signal are applied.

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 Counters
 Asynchronous Binary Down Counter

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 Counters
 Counters: synchronous Binary Up & Down Counter - SLE

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 Thank You

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