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Boolean Algebra and Logic Circuits

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Boolean Algebra and Logic Circuits

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dc1901020
Copyright
© © All Rights Reserved
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Download as PPTX, PDF, TXT or read online on Scribd
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Logic Circuits

15.2 Boolean Algebra and


Logic Circuits
HALF ADDERS
• Half adders run on the basis of binary addition.
• 1+ 1 = 0 (carry 1)
• 1+ 0 = 1
• 0+ 1 = 1
• 0+ 0 = 0 Representation of a half adder circuit

• However the carry cannot be ignored hence the simplest circuit to


represent the addition is the half adder.
HALF ADDER
• The half adder has 2 inputs A and B and 2 outputs S(Sum) and
C(Carry)
• The truth table represents the basic Binary addition whereby A and B
with add each other to produce the output S and the carry is output C
Creating the half adder circuit with logic
gate
• The half adder circuit comprises of 2 main logic gates – AND and XOR
• The XOR gate takes the 2 inputs to create the SUM output as
illustrated in the previous truth table
• The AND gate takes the 2 inputs to create the CARRY output.

• For industrial use however manufacturers tend to use NAND or NOR


gates as these are considered universal gates(any circuit can be
created from purely from an AND gate or a NOR gate) and are easier
to manufacture.
HALF ADDER
LOGIC
CIRCUIT
• This circuit is purely
constructed from NAND
gates

Activity:
• Draw up the truth table
including the output at
each gate
HALF ADDER
LOGIC CIRCUI
• Based on the previous diagram now
construct the half adder circuit using only
NOR gates

• Using your logic circuit draw up the truth


table including the output at each gate
Hint: try to find the possible inputs
for S and C and work
backwards(creating the truth table
for the NOR can be helpful)
FULL ADDER
• The full adder is an extension of the half adder which includes any
carried value form a previous addition.
• The full adder takes in 3 inputs, A, B and Cin(Carry-In).
• The Cin value is normally the Carry value from the previous addition
of A and B.
• The full adder has 2 outputs, S(Sum) and Cout(Carry-Out)
• The Cout value is any remainder from the addition of the 3 inputs
• The S value is the total of the 3 inputs(A, B and Cin)
Full Adder
FULL ADDER
LOGIC
CIRCUIT
• Like before this circuit is
purely constructed from
NAND gates

Activity:
• Draw up the truth table
including the output at
each gate
Sequential Logic Circuits
Flip-Flops
Introduction
• So far the gate we have been using were combinational gate whereby
each gates output ddpende soley on the input
• Sequential gates are those which depend on an input value and the
value of a previous output
SR Flip-Flop
• The SR flip-flop aka latch is an example of a sequential circuit.
• It is constructed with either 2 NOR gate or 2 NAND gates
• The output of an SR circuit are always different from each other
• Meaning the second output is the complement of the first.
• S(set) and R(reset) can never be both 1 because this leads to an
invalid state with both Q and Q’ having value 0.
TRUTH TABLE
SR flip-flop

• This circuit is purely


constructed from NOR
gates

Activity:
• Draw the SR circuit using
the NAND Gate
• Draw up the truth table
including the output at
each gate
How an SR is used to store data
• SR flip-flop can be used as a storage device for 1 bit and therefore
could be used as a component in RAM because a value is stored but
can be altered. The truth table does
• not contain rows for R=1 and S=1 Because of this the circuit must be
protected from receiving an input signal on R and S
• simultaneously.
• The alternative NAND gate circuit for the SR flip-flop has a similar
structure but the labeling is different.
• The important difference is that setting is achieved with S=0 and R=1
and resetting with R=0 and S=1.
JK Flip-flop
• In addition to the possibility of entering an invalid state there is also
the potential for a circuit to arrive in an uncertain state if inputs do
not arrive at the same time.
• In order to prevent this, a circuit may include a clock pulse input to
increase synchronization of inputs.
• The JK flip-flop is an example of a synchronised circuit.

Circuit symbol
JK Flip-
Flop
• If the circuit is in the unset state with
Q = 0 and Q’ =1 this is stable and self-
consistent as shown by the following
argument:
a. the clock and R both input 0
b. the top-left NAND gate therefore
has output 1
c. this then leads to two 1 inputs to
the top-right NAND gate
d. ensuring that Q = 0.
JK Flip-
Flop

• If the input from J now becomes 1 and the


clock pulse switches to a 1 then:
• the top-left NAND gate has all 1 inputs
• so the output is 0
• this causes the top-right NAND gate to
output a 1 for Q there are now two 1 inputs
to the bottom-right NAND gate
• so the Q’ output becomes 0.
Truth table
How an JK is used to store data
• This shows how the J input is a set input. A similar argument shows
that the K is a clear input.
• In this respect the JK flip-flop behaves in a similar way to the SR flip-
flop as a storage device for one bit.
• However, there is an important difference in that if both J and K are
input as a 1 then the values for Q and Q’ are toggled (they switch
value).
• This makes the JK flip-flop a more reliable device because there is no
combination of input states that leave uncertainty as to which values
are stored
Avril Mukanyangi

Thank You!!!

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