Computer Organization

&
Architecture
1.1 Introduction

 Computer Organization, Computer Design, Computer Architecture

 Computer Organization :

 is concerned with the way the hardware computer operate and the way they are
connected together to form the computer system.
 The various components are assumed to be in place and the task is to investigate the
organizational structure to verify that the computer parts operate as intended.
 CONT’D…

 Computer Design:

 is concerned with the hardware design of the computer.

 Once the computer specification is formulated, it is the task of the designer to develop
hardware for the system.
 It is concerned with the determination of what hardware should be used and how the parts
should be connected.
 It is the aspect of computer hardware and sometimes referred to as computer
implementation.
 CONT’D…

 Computer Architecture:

 is concerned with the structure and behavior of the computer as seen by the user.

 It includes the information formats, the instruction set and techniques for addressing
memory.
1.2 Digital Logic Circuits

 This chapter introduces the fundamental knowledge needed for the design of digital systems
constructed with the individual gates and flip – flops.

 It covers Boolean algebra, combinational circuits and sequential circuits.

 This provides the necessary background for understanding the digital circuits to be presented.
1.3 Digital Computers

 Digital computers use the binary number system, which has two digits, 0 and 1

 A binary digit is called a bit.

 Bits are grouped together as bytes and words to form some type of representation within
the computer.

 A sequence of instructions for the computer is known as program.

 Block diagram of a digital computer as shown fig 1.1

CONT’D…

Fig 1.1
CONT’D…
 The hardware of the computer is usually divided into three major parts.

 The Central processing Unit (CPU): contains an arithmetic and logic unit for
manipulating data, a number of registers for storing data, and control circuits for fetching
and executing instructions.

 The memory of a computer; contains storage for instructions and data, it is called a
Random Access Memory (RAM) ,the CPU can access any location in memory at random
and retrieve the binary information within a fixed interval of time.
CONT’D…

 The input and output processor: contains electronic circuit for communication and
controlling the transfer of information between the computer and the outside world.

 The input and output device: connected to the computer include keyboards, printers,
terminals, magnetic disk drives and other communication devices.
 1.4 Logic Gates

 Gates are the fundamental building block of all digital logic circuits.

 Logical functions are implemented by the interconnection of gates.

 Binary information is represented in digital computers using electrical signals.

 These signals can be represented by voltage to specify one of two possible states.

 For example, if a wire contains a signal of 3 volts, it is considered to contain the digital value 1.
 CONT’D…

 Likewise, if the wire contains 1.5 volts, then it represents the digital value 0.

 The manipulation of binary information in a computer is done using logic circuits called
gates.

Examples: AND, OR, Inverter, Buffer, NAND, NOR, X-OR, X-NOR

 Each gate is defined in three ways: graphic symbol, algebraic notation/function, and truth
table
 Fig 1.2
A. AND Gate

The truth table of

AND gate

B. OR Gate
A
X=A+B
B

The truth table of OR

gate
C. Inverter

X = A’

D. Buffer

X=A

E. NAND
F. NOR
A

G. Exclusive-OR (XOR)

A x = A⊕ B
or
B x=A’B+AB’

H. Exclusive-NOR

X = (A⊕ B)’
1.5 Boolean Algebra

 Boolean algebra is an algebra that deals with binary variables and logic operations.

 Variables are designated by letters such as A, B, x, and y.

 A Boolean function can be expressed algebraically with binary variables, the logic
operation symbols, parentheses and equal sign, and it can represent by: truth table,
logic diagram & algebraic expression.
CONT’D…

 The result of a Boolean function is either 0 or 1.

 Example: Consider the following Boolean function: F = xy + z‘

 The function F is equal to 1 if either both x and y are 1 or z' is 1; F is equal to 0
otherwise.
 NB: z' = 1 is equivalent to saying z = 0 since z' is the complement of z.
 1.6 Basic Identities of Boolean algebra

(1) x+0=x (2) x * 0 = 0

(3) x+1=1 (4) x * 1 = x
(5) x+x=x (6) x * x = x
(7) x + x' = 1 (8) x * x' = 0
(9) x+y=y+x (10) xy = yx
(11) x + (y + z) = (x + y) + z (12) x(yz) = (xy)z
(13) x(y + z) = xy + xz (14) x + yz = (x + y)(x + z)
(15) (x + y)' = x'y' (16) (xy)' = x' + y‘
(17) (x')' = x
1.7 De-Morgan’s Theorem

 This theorem is very important in dealing with NOR and NAND gates.

 It states that a NOR gate that performs the (x+y)’ function is equivalent to the function

x’y’.

 Similarly a NAND function (xy)’ can be expressed by (x’+y’).

 For this reason the NOR and NAND gates have two distinct graphic symbols.
 OR invert invert AND

 The invert AND symbol for the NOR gate follows from the De-Morgan’s thermo and from the convention that
small circles denote complementation.
 Similarly the NAND gates have two distinct symbols as shown below.

AND-invert
x
y
z

Invert OR
x
Y
z
 1.8 Complement of a function

 The complement of a function F when expressed in a truth table is obtained by interchanging 1’s

and 0’s in the values of F in the truth table.

 When the function is expressed in algebraic form the complement of the function can be derived

by means of De-Morgan’s Theorem.

 The general form of DE Morgan's theorem can be expressed as follows:

(x1+x2+x3+….Xn) = x1’x2’x3’…xn’

(x1x2x3…xn)’ =x1’+x2’+x3’+…+xn’
 CONT’D…

 By changing all OR operation to AND operation and all OR operations and then complementing

each individual letter variable we can derive a simple procedure for obtaining the complement of

an algebraic expression.

Example: F = AB+C’D’+B’D F’=(A’+B’)(C+D)(B+D’)

 NB: The complement expression is obtained by interchanging AND and OR operations and

complementing each individual.

1.9 Map Simplification

 In addition to using Boolean algebra to simplify a Boolean function, we use map

simplification techniques/methods.

 The map method is also known as the Karnaugh map or K-map.

 Each combination of the variables in a truth table is called a min-term.

 There are 2n min-terms for a function of n variables.

 The Boolean algebra can be simplified using the following two methods:

1. Sum-of- Products simplifications (SOP)

2. Product-of-sum simplifications (POS)

1.10 Variable Maps

fig 1.3
 CONT’D…

 The variable names are listed across both the sides of the diagonal line into the corner of the map.

 The 0’s and the 1’s marked along each row and each column designate the value of the variables.

 Each variable under the brackets contain half of the squares in the map where that variable

appears unprimed.
CONT’D…

 The min-term represented by a square is determined from the binary assignment of the

variable along the left top edges in the map.

 Here the min-term 5 in the three variable maps are 101 of the second column.

 This min-term represents a value for the binary variables A, B and C with A and C being

unprimed and B being primed.

 Sum-of-Products Simplification (SOP)

 A Boolean function represented by a truth table is plotted into the map by inserting 1's into those
squares where the function is 1.

 Boolean functions can then be simplified by identifying adjacent squares in the Karnaugh map that
contain a 1.

 A square is considered adjacent to another square if it is next to, above, or below it.

 In addition, squares at the extreme ends of the same horizontal row are also considered adjacent.

 The same applies to the top and bottom squares of a column.

 CONT’D…
 The objective is to identify adjacent squares containing 1's and group them together.

 Groups must contain a number of squares that is an integral power of 2.

 Groups of combined adjacent squares may share one or more squares with one or more groups.

 Each group of squares represents an algebraic term, and the OR of those terms gives the
simplified algebraic expression for the function.

 To find the most simplified algebraic expression, the goal of map simplification is to identify the least
number of groups with the largest number of members.
CONT’D…

Example: We will simplify the Boolean function. F (A,B,C) = Σ(3,4,6,7)

 There are four squares marked with 1’s, one for each min-term that produces 1 for the function.

 These squares belong to min-term 3,4,6,7 and are recognized from the figure b.

 Two adjacent squares are combined in the third column.

 This column belongs to both B and C produces the term BC.

 The remaining two squares with 1’s in the two corner of the second row are adjacent and belong to row

columns of C’, so they produce the term AC’.

CONT’D…
 The simplified expression for the function is the or of the two terms:

F = BC + AC’

 The second example simplifies the following Boolean function:

F(A,B,C) = Σ(0,2,4,5,6)

 The five min-terms are marked with 1’s in the corresponding squares of the three variable maps.

 The four squares in the first and the fourth columns are adjacent and represent the term C’.

 The remaining square marked with a 1 belongs to min-term 5 and can be combined with the

square of min-term 4 to produce the term AB’.

 The simplified function is :

 CONT’D…

Map for F(A,B,C) = Σ(0,2, 4, 5, 6)

The simplified expressions of the function is :

F = C’+AB’
Maps for F(A,B,C,D)=Σ(0,1,2,6,8,9,10)

Fig 1.4
 CONT’D…

 The area in the map covered by this four variable consists of the squares marked with 1’s in fig 1.4.

 The function contains 1’s in the four corners that when taken as groups give the term B’D’.

 This is possible because these four squares are adjacent when the map is considered with the top

and bottom or left and right edges touching.

CONT’D…

 The two 1’s on the bottom row are combined with the two 1’s on the left of the bottom row

to give the term B’C’.

 The remaining 1 in the square of min-term 6 is combined with the min-term 2 to give the

term A’CD’.

 So the simplified function is:

F = B’D’ + B’C’ + A’CD’

Product-of-Sums Simplification (POS)

 This approach is similar to the Sum-of-Products simplification, but identifying adjacent squares

containing 0’s instead of 1’s forms the groups of adjacent squares.

 Then, instead of representing the function as a sum of products, the function is represented as a

product of sums.

Examples: F(A,B,C,D) = Σ(0,1,2,5,8,9,10)

 The 1’s marked in the map of fig 1.5 represents the min-terms that produces a 1 for the function,
CONT’D…

 The squares marked with 0’s represent the min-term not included in F and therefore denote the complement

of F.

 Combining the squares with 1’s gives the simplified function in sum-of-products form:

F = B’D’ +B’C’+A’C’D

 If the squares marked with 0’s are combined as shown in the diagram, we obtain the simplified complement

function:
F’=(A’+B’)(C’+D’)(B’+D)

Fig 1.5
Fig 1.6
Fig 1.7
1.11 Don't Care Conditions

 It doesn't matter whether a function produces a 0 or 1 for a given min-term.

 When this condition occurs, an X is used in the map to represent the don't care condition.

 Then, when performing map simplification, a square containing an X can be used in both the

Sum-of-Products approach and the Product-of-Sums approach.

 When choosing adjacent squares for the function in the map, the x’s may be assumed to be

either 0 or 1, whichever gives the simplest expression

CONT’D…

 In addition an x need not to be used at all if it does not contribute to the simplification of
the function.

 In each case the choice depends only on the simplification that can be achieved.

 As example consider the following Boolean function together with the don’t care min-terms:

 F(A,B,C) = Σ0,2,6)

 d(A,B,C) = Σ(1,3,5)
CONT’D…

 The min-term listed with F produce a 1 for the function.

 The don’t care min-terms listed with d may produce either a 0 or 1 for the function.

 The remaining min-terms 4,7 produce a 0 for the function.

 The 1’s and x’s are combined in any convenient manner so as to enclose the maximum

number of adjacent squares.

CONT’D…

 It is not necessary to include the don’t care min-terms 1 and 3 with the 1’s in the first row
we obtain the term, BC’.

The simplified expression is:

F = A’ + BC’

But if we don’t use the X’s the simplified expression would be:

F=A’C’+BC’ it needs two ANDs gate and one OR gates.

 Combinational Circuits

 A combinational circuit is a connected arrangement of logic gates with a set of inputs and outputs.

 At any given time, the binary values of the outputs are a function of the binary values of the inputs.

 The design of a combinational circuit starts from a verbal outline of the problem and ends in a logic

circuit diagram.
CONT’D…

 The procedure involves the following steps:

 The problem is stated.

 The input and output variables are assigned letter symbols.

 The truth table that defines the relationship between inputs and outputs is derived.

 The logic diagram is drawn

 Half-Adder
 The most basic digital arithmetic circuit.
 Performs the addition of two binary digits.
 The input variables of a half-adder are called the augends and the addend.
 The output variables of a half-adder are called the sum and the carry.

Fig 1.8 half adder

S = x’y+xy’=x ⊕ y
C=xy
Full-Adder
 A full-adder performs the addition of three binary digits.
 Two half-adders can be combined to form a full-adder.
 Full adder has three inputs and two outputs
 The full adder circuit contains two half adders and an OR gate.
CONT’D…

NB: Additional examples of combinational circuits:

 Decoders
 Encoders
 multiplexers(MUL)
 Demultiplexers
 Decoders

 A binary code of n bits is capable of representing up to 2 n distinct elements of the coded information

 A decoder is a combinational circuit that converts binary information from the n coded inputs to a

maximum of 2n unique outputs

 A decoder has n inputs and m outputs, where m ≤ 2n, and are called n-to-m-line decoders

 Each output represents one of the combinations of the input variables

 An enable input controls operation of the decoder

Fig 1.20 3-to- 8 line Decoder
 Truth table for 3-to- 8 line Decoder

Some decoders use NAND gates rather than AND gates causing the outputs to be in their
complemented form
 The circuit would then be enabled when E = 0
 Fig 1.21 2-to-4 line decoder with NAND gates

NB:
 It is possible to combine two or more decoders with enable inputs to form a larger decoder
 The enable inputs are a convenient feature for decoder expansion
Fig 1.22 A 3X8 Decoder constructed with 2 X 4 Decoders

You can check the relationship by using the truth tables.

Encoders
An encoder is a digital circuit that performs the inverse of a decoder
 An encoder has 2n (or less) input lines and n output lines
The output lines generate the binary code corresponding to the input value
Truth tables for Octal to Binary Encoder
 Cont…
An encoder can be implemented with OR gates
A0 = D 1 + D 3 + D 5 + D 7

A1 = D 2 + D 3 + D 6 + D 7

A2 = D 4 + D 5 + D 6 + D 7

Multiplexers

 A multiplexer (MUX) is a combinational circuit with 2n input data lines, n input select lines,
and one output line
 The input selection lines determine which input data line is selected for the output
Fig 1.23 4-to-1 line Multiplexers
 Rather than using a truth table to describe the circuit, we use function table with 2n rows is used ,
example for the 4-to-1 line multiplexer above we needs 64 rows, if we use truth table , then instead we
use function tables.
 One row for each combination of the selection inputs
 The MUX is also called a data selector
Function table for 4-to- 1 line Multiplexers

You can check from fig 1.23

Sequential circuits

 The current output of a sequential circuit depends on the current input and the current
state of that circuit.
Flip-flops
 Is the simplest form of sequential circuit.

 There are a variety of flip flops, all of which share two properties:

1. The flip-flop is a bi-stable device, it exists in one of two stable states

2. The flip-flop has two outputs, which are always the complements of each other.
These are generally labeled Q and Q’ (Q complement).
CONT’D…

 A Flip-flop is a binary cell capable of storing one bit of information.

 It has two outputs, one for the normal value and one for the complement value of the bit

stored in it.

 Flip-flops are storage elements utilized in synchronous sequential circuits.

CONT’D…

 Synchronous sequential circuits employ signals that effect storage elements only at discrete

instances of time.

 A timing device called a clock pulse generator that produces a periodic train of clock pulses

achieves synchronization.

 Values maintained in the storage elements can only change when the clock pulses.

 Hence, a flip-flop maintains a binary state until directed by a clock pulse to switch states.
CONT’D…

 The difference in the types of flip flops is in the number of inputs and the manner in which

the inputs affect the binary state.

 Flip-flops can be described by a characteristic table which permutated all possible inputs

(just like a truth table).

 The characteristic table of a flip-flop describes all possible outputs (called the next state)

at time Q(t+1) over all possible inputs and the present state at time Q(t).
 The most common types of flip flops are:
 SR Flip-Flop
 D Flip-Flop
 JK Flip-Flop
 T Flip-Flop

SR Flip-Flop or S-R Latch

Has 3 Inputs: Graphic symbol Truth table

 S (for set)
 R (for reset)
 C(for Clock)
Has 2 Outputs:
 Q
 Q'
 CONT’D…

 The operation of the SR flip-flop is as follow.

 If there is no signal at the clock input C, the output of the circuit cannot change irrespective of the

values at inputs S and R.

 Only when the clock signals changes from 0 to 1 can the output be affected according to the values

in inputs S and R

 If S =1 and R = 0 when C changes when C changes from 0 to 1 output Q is set to 1.

CONT’D…

 If S = 0 and R =1 when C changes from 0 to 1output Q is cleared to 0.

 If both S and R are 0 during the clock transition, output does not change.

 When both S and R are equal to 1, the output is unpredictable and may go to either 0 or

1, depending on internal timing that occur within the circuit.

 D Flip-Flop:
= slight modifications of SR flip-flops

Inputs: Graphics Symbol

D (for data)
C (for clock)
Outputs:
Q
Q'
JK Flip-Flop : is the refinements of the SR flip-flops in that indeterminate conditions of the SR type
and is defined in the JK types.
-if inputs J& K are both equal to 1 a clock transition switches the outputs of the flip-flops to their
complement state.
Inputs: Graphics Symbol
J
K
C
Outputs:
Q &Q'
T Flip-Flop : is obtained from a JK types when inputs J& K are connected to provide single
inputs designed by T.

 the T flip flops has only two conditions

I. When T=0(J=K=0) a clock transition does not change the state of the flip-flops
II. When T=1(J=K=1) a clock transition complements the state of the flip-flops

Inputs:
T (for toggle)
C (for clock)
Outputs:
Q &Q‘
The T flip flops can be expressed by this equation: Q(t+1)=Q(t) XOR T

Edge – Triggered Flip-flops

 Most common types of flip flops used synchronize the state change during a clock
transition is the edge-triggered flip- flops.
CONT’D…

 Most flip-flops are edge-triggered flip-flops (i.e. the transition occurs at a specific level of

the clock pulse) .

 A positive-edge transition occurs on the rising edge of the clock signal.

 A negative-edge transition occurs on the falling edge of the clock signal.

 CONT’D…

Master Slave flip-flops

 Consists of two flip-flop

 The 1st is the Master, w/h responds to the positive level of the clock and

 The 2nd is the Slave, w/h responds to the negative level of the clock.

• E.g. The result changes from 0 to 1 transitions of the clock signals.

 Flip-flops can also include special input terminals for setting or clearing the flip-flop asynchronously.

 These inputs are usually called preset and clear and are useful for initialing the flip-flops before clocked

operations are initiated.

CONT’D…

Registers
 A register is a group of flip-flops with each flip-flop capable of storing one bit of information.

 An n-bit register has a group of n flip-flops.

 A register may also have combinational gates that perform certain data-processing tasks.

 The flip-flops hold the data and the gates control when and how new data is transferred
into the register.

 The flip-flops have a common clock input.

 A common clear input is available to reset all the flip-flops asynchronously.

CONT’D…

Fig 1.24 4 bit Registers

CONT’D…

 The transfer of new data into a register is called loading the register

 If all bits are loaded simultaneously with a common clock pulse transition, then the

loading is done in parallel

 The load input determines the action to be taken with each clock pulse

 If the load input is 1, then the data in the four inputs are transferred at the next positive

clock transition.
CONT’D…

 If the load input is 0, the data inputs are inhibited and the output is fed back to simulate a

no change condition

 Two basic types of registers are commonly used:

1. parallel registers and

2. shift registers.
CONT’D…
 NB: Figure 1.25 illustrates the operation of a parallel register using D flip-flops.

Fig 1.25 8 bit parallel register

 CONT’D…
SHIFT REGISTER:

 A shift register accepts and/or transfers information serially.

 A shift register is capable of shifting its binary information in one or both directions

 The logical configuration is a chain of flip-flops, with the output of one connected to the input of the next

 The serial input determines what goes into the leftmost position during the shift

 The serial output is taken from the output of the rightmost flip-flop

Fig 1.26 :5-bit shift register

CONT’D…

 A bi-directional shift register can shift in both directions

 The most general shift register has all the following capabilities:

 An input for clock pulses to synchronize all operations

 A shift-right operation and a serial input line associated with the shift-right

 A shift-left operation and a serial input line associated with the shift-left

 A parallel load operation and n input lines associated with the parallel transfer

 n parallel output lines.

 Binary Counters

 A register that goes through a predetermined sequence of states upon the application of input pulses is

called a counter

 The input pulses may be a clock or an external input

 The input may occur at uniform intervals of time or randomly

 Used to count the number of occurrences of an event and for generating timing signals to control the

sequence of operations

 A counter that follows the binary number sequence is a binary counter.

CONT’D…

 An n-bit binary counter is a register of n flip-flops and gates that follow a sequence of states

 Consider the sequence 0000, 0001, 0010, 0011, 1000, …

 The lsb is complemented on each count

 Every other bit is complemented iff all its lower-order bits are equal to 1.

 Natural to use either T or JK flip-flops since they both have a complement state

 The counter has an enable input

 Synchronous counters have a regular pattern with a common clock

 The chain of AND gates generate the logic for the flip-flop inputs.
CONT’D…

Fig 1.27 4 bit synchronous binary counter

Memory Unit

 A memory unit is a collection of storage cells together with associated circuits to transfer
information in and out of storage

 The memory stores binary data in groups of bits called words

 A word can represent an instruction code or alphanumeric characters

 Each word in memory is assigned an address from 0 to 2 k –1, where k is the number of
address lines.
CONT’D…

 A decoder inside the memory accepts an address opens the paths needed to select the bits of the

specified word

 The memory capacity is stated as the total number of bytes that can be stored

 Refer to the number of bytes using one of the following

 K (kilo) = 210 M (mega) = 220

 G (giga) = 230 64K = 216, 2M = 221, and 4G = 232

CONT’D…

 In random-access memory (RAM) the memory cells can be accessed for information from

any desired random location.

 The process of locating a word in memory is the same and requires an equal amount of

time no matter where the cells are located physically in memory.

 Communication between memory and its environment is achieved via data input and

output lines, address selections lines, and control lines.

CONT’D…

 The n data input lines provide the information to be stored in memory

 The n data output lines supply the information coming out of memory

 The k address lines provide a binary number of k bits that specify a specific word or location

 The two control lines specify the direction of transfer – either read or write.
CONT’D…

Steps to write to memory:

 Apply the binary address of the desired word into the address lines
 Apply the data bits that are to be stored in memory on the data lines
 Activate the write input
CONT’D…

 Steps to read from memory:

 Apply the binary address of the desired word into the address lines

 Activate the read input

 A read-only memory (ROM) is a memory unit that performs the read operation only; there is
no write capability

 The binary information stored in a ROM is permanent during the hardware production.
CONT’D…

 RAM is a general-purpose device whose contents can be altered

 The information in ROM forms the required interconnection pattern

 ROMs come with special internal electronic fuses that can be programmed for a specific

configuration

 An m x n ROM is an array of binary cells organized into m words of n bits each.

CONT’D…
 A ROM has k address lines to select one of m words in memory and n output lines, one for each bit
of the word.

 May have one or more enable inputs for expansion.

 The outputs are a function of only the present input (the address), so it is a combinational circuit
constructed of decoders and OR gates.
CONT’D…

 When used as a memory unit, it stores fixed programs that are not to be altered and for tables

of constants that will not change

 When used in the design of control units for digital computers, it stores coded information

that represents the sequence of internal control variables to enable the various operations

 A control unit that utilizes a ROM is called a micro programmed control unit.

 The required paths may be programmed in three different ways.

CONT’D…

 Mask programming is done by the semiconductor company based upon a truth table

provided by the manufacturer.

 Programmable read-only memory (PROM) is more economical.

 PROM units contain all fuses intact and are blown by users.

 Erasable PROM (EPROM) can be altered using a special ultraviolet light.

 Electrical Erasable PROM (EEPROM) can be erased with electrical signals.

END of CHAPTER ONE AND THREE