COMPUTER

ARCHITECTURE
Chapter 3
A Top-Level View Of Computer
Function and Interconnection
Overview
Part One
3.1 Components of a computer
3.2 Functions of a computer
Part Two
3.3 Interrupts
3.4. Buses
Part One
3.1 Components of a
Computer
Program Concept

Types of Connecting Various Components

• General purpose (Programming in

Software) hardware can do different
tasks, given correct control signals
• Instead of rewiring, supply a new set
of control signals
Hardware and Software Approaches

• How to implement this arithmetic operation using hardwire

and software
— X=pow(2,3); //
Hardware and Software Approaches
Hardwired Program Software Program
What is a program?
• A sequence of steps
• For each step, an arithmetic or logical
operation is done
• For each operation, a different set of
control signals is needed
Example
3.2 Functions of a
Computer
Function of Control Unit
• For each operation, a unique code is
provided
—e.g. ADD, MOVE
• A hardware segment accepts the code and
issues the control signals
Components
• The Control Unit and the Arithmetic and
Logic Unit constitute the Central
Processing Unit
• Data and instructions need to get into the
system and results out
—Input/output
• Temporary storage of code and results is
needed
—Main memory
Components
Computer Components:
Top Level View
How is Instruction Executed?
• What is instruction?
— Instruction specify the action that the processor is supposed
to take.
• The processing required for a single instruction is called an
instruction cycle.
• Instruction cycle are made of these two steps:
— Fetch (processor reads from memory and also referred to as
fetch cycle)
— Execute (Also referred to as execute cycle)
Fetch Cycle
• Program Counter (PC) holds address of
next instruction to fetch
• Processor fetches instruction from
memory location pointed to by PC
• Increment PC
—Unless told otherwise
• Instruction loaded into Instruction
Register (IR)
• Processor interprets instruction and
performs required actions
Execute Cycle
• An instruction’s execution (execute cycle)
may involve one or a combination of these
actions
—Processor-memory
– data transfer between CPU and main memory
—Processor I/O
– Data transfer between CPU and I/O module
—Data processing
– Some arithmetic or logical operation on data
—Control
– Alteration of sequence of operations
Instruction Format
• Assume both instructions and data are 16 bits long.
• The instruction format provides
— 4 bits for the opcode, so that there can be as many as 24 = 16
different opcodes and
— 12 bits for the address , so that up to 212 words of memory can be
directly addressed.

Instruction format

Integer format
Figure 3.4 Characteristics of a Hypothetical Machine
 Example of Program Execution
Internal CPU Registers
PC (Program Counter)
AC (Accumulator)
– a data register
IR (Instruction Register)
Program to be executed:
Adds the content of the
memory word at address
940 to the content of the
memory word address
941 and stores the result
in latter location.

Figure 3.5 Example of

Program Execution
(cont.) Example of Program
Execution
Requires 3 fetch and 3 execute
cycles.
1. {1st Fetch cycle} The PC contains 300,
the address of the first instruction. This
instruction (the value 1940 in
hexadecimal) is loaded into the
instruction register IR and the PC is
incremented. Note that this process
involves the use of a memory address
register (MAR) and a memory buffer
register (MBR). For simplicity these
intermediate registers are ignored.
(cont.) Example of Program
Execution
2. {1st Execute cycle} The first
4 bits (first hexadecimal digit) in the IR
indicate that the AC is to be loaded. The
remaining 12 bits (3 hexadecimal digits)
specify the address (940) from which
data are to be loaded.
(cont.) Example of Program
Execution

3. {2nd Fetch cycle} The next instruction

(5941) is fetched from location 301 and
the PC is incremented.
(cont.) Example of Program
Execution

4. {2nd Execute cycle} The old content of

the AC and the content of location 941
are added and the result is stored in the
AC.
(cont.) Example of Program
Execution

5. {3rd Fetch cycle} The next instruction

(2941) is fetched from location 302 and
the PC is incremented.
(cont.) Example of Program
Execution

6. {3rd Execute cycle} The content of AC is

stored in location 941.
(cont.) Example of Program
Execution

Operand (Data) can be in:

i.Register (file register is the 32 register reach one 32-
bit).
ii.Memory (byte, wordline).
iii.Immediate value.
 (cont.) Example of Program
Execution
Arithmetic operations: (Add)
Add x , z

Destination
Source

Mov x, z

Destination
Source

Str x, z

Source
Destination
(cont.) Example of Program
Execution
300 301

CPU

PC
Opcode Address 200
0100 300
200
IR
0110 301 Empty
201
0101 302
202 AC
Empty

4
300
8
301
302
(cont.) Example of Program
Execution
300 301

Opcode Address

200 0100 300

CPU
201 0110 301

202 0101 302 PC

200

Fetch
IR
300 4 0100 300

301 8
AC
302 Empty
(cont.) Example of Program
Execution

300 301

Opcode Address

200 0100 300

CPU
201 0110 301
PC
202 0101 302 201

Execute
IR

300 4 0100 300

301 8 AC
302 4
(cont.) Example of Program
Execution
300 301 Opcode Address

200 0100 300

CPU
201 0110 301

0101 302 PC
202
201

Fetch
IR
300 4 0110 301
301 8
AC
302 4
(cont.) Example of Program
Execution

300 301

Opcode Address

200 0100 300 CPU

201 0110 301

PC
0101 302 202
202

IR
300 4
0100 301
301 8
302 AC
8
Execute
(cont.) Example of Program
Execution
300 301

Opcode Address

200 0100 300

CPU
201 0110 301

0101 302 PC
202 203

IR
300 4 0100 302
301 8
AC
302 12

Store
(cont.) Example of Program
Execution

Memory
Memory of Address

0 15
PC = No. of Instruction = 12 bits.
IR = Instruction Register = 16 bits.
AC = 16 bits.
MAR = 12 bits.
4095
MBR = 16 bits.
Input Register = 8 bits.
Output Register = 8 bits.
(cont.) Example of Program
Execution
1bits 12 bits

sign Opcode Address

0 1 4 16

PC
0 12 bits 12

IR Memory 4096 words

16 bits per each word
0 16 bits 15

MBR
0 16 bits 15 Input
0 8 bits 7
MAR
0 12 bits 11 Output
0 8 bits 7
AC
0 16 bits 15
(cont.) Example of Program
Execution

A MANO Computer uses a memory unit with 256k words of 32

bits each. A binary instruction code is stored in one word of
memory. The code part to specify one 64 regists, and an address
part.
a)How any bits are there in the operation code, register code part,
and the address part?
b)Draw the instruction word format and indicate the number of
bits in each part.
c)How many bits are there in data and address inputs of the
memory?
 (cont.) Example of Program
Execution
32 bits

0 31

Memory of Address
PC
0 18 bits 17

IR
0 32 bits 31 256k

MBR 32 bits
0 32 bits 31 Input
0 8 bits 7
MAR
0 18 bits 17 Output
0 8 bits 7
AC
0 32 bits 31
(cont.) Example of Program
Execution
1bits 6 bits 18 bits

sign Opcode Register Address

00 01 07 13 31
 Instruction Cycle State
Diagram
• The upper part involve an exchange between the processor and
memory or between processor and I/O module.
• States in the lower part of the diagram only internal processor
operations.
Instruction Cycle State
Operation

Instruction Fetch (IF): Read instruction from its memory

location into the processor.
Instruction Operation Decoding (IOD): Analyze
instruction to determine type of operation to be performed
and operand(s) to be used.
Operand Address Calculation (OAC): If the operation
involves reference to an operand in memory or available
via I/O, then determine the address of the operand.
Operand Fetch (OF): Fetch the operand from memory or
read it in from I/O.
Data Operation (DO): Perform the operation indicated in
the instruction.
Operand Store (OS): Write the result into memory or out
to I/O.
Part Two
2.3 Interrupts
Why Use Interrupts?
• Other modules (e.g. I/O, memory) may
interrupt the processor’s normal
sequence of processing.
• Interrupts are provided primarily as way
to improve processing efficiency.
—The processor can be used for processing
something else (e.g. open and edit a Word
document) while I/O operation (e.g. printing)
is in progress.
Classes of Interrupts
• Program
—e.g. due to overflow, division by zero
• Timer
—Generated by internal processor timer
—Used in pre-emptive multi-tasking (do certain
function in regular basis e.g. data backup)
• I/O
—from I/O controller to signal normal
completion or error conditions.
• Hardware failure
—e.g. power failure, memory parity error
Program Flow Control

X – interrupt occurs during course of execution of user program

(cont.) Program Flow Control
• The user program perform a series of
WRITE calls interleaved (berselang-seli)
with processing.
• Code segment 1, 2 and 3 refer to
sequences of instructions that do not
involve I/O.
• The WRITE calls are to an I/O program
that is a system utility and that will
perform the actual I/O operation.
• The I/O program consists of 3 sections:
— Label 4: sequence of instructions to
prepare for actual I/O.
— The actual I/O (Processor WAIT for this
to finish).
— Label 5: sequence of instructions to
complete the I/O operation. May include
setting flag indicating success or fail.
 Interrupt Cycle
• Added to instruction cycle
— (NOW Instruction Cycle = Fetch Cycle + Execute Cycle +
Interrupt Cycle)
• Processor checks for interrupt
— Indicated by an interrupt signal
— User program does not have to contain special code for handling interrupt
— The processor and operating system are responsible for suspending user
program
• If no interrupt, fetch next instruction
• If interrupt pending:
— Suspend execution of current program
— Save context (save next instruction address and other data relevant to
processor’s current activity)
— Set program counter (PC) to start address of interrupt handler routine
— Process interrupt
— Restore context and continue interrupted program
 Transfer of Control via Interrupts
• When the interrupt handler routine is completed, the
processor can resume execution of the user program at the
point of interruption.
 Instruction Cycle with Interrupts
• If no interrupts are pending, processor proceeds with the fetch cycle and fetches
the next instruction of the current program.
• If interrupt is pending, the processor will do the followings:
— It suspends execution of the current program and saves its context (save next
instruction address and other data relevant to processor’s current activity).
— Sets the program counter to the starting address of an interrupt handler routine.
Interrupt handler program is generally part of operating system.
 Program Timing: Short I/O Wait
• For the system using interrupts, the Program Timing with Short I/O Wait
time required for the I/O operation is
relatively short: less than the time to
complete the execution of instructions
between 2 WRITE operations in the
user program.
• Thus, with interrupt (Figure b) no
waiting time by the processor.
 Program Timing: Long I/O Wait
• For WRITE I/O operation taking longer Program Timing with Long I/O Wait
wait time, longer than the time to
complete the execution of instructions
between 2 WRITE operations in the
user program.
• The first WRITE I/O need to be
completed first before the second
WRITE can be processed.
 Instruction Cycle (with Interrupts) -
State Diagram

(Compare with “Instruction Cycle State Diagram” in slide 26)

Multiple Interrupts
Approaches to Deal with Multiple Interrupts
1. Disable interrupts
— Processor will ignore further interrupts whilst processing
one interrupt
— Interrupts remain pending and are checked after first
interrupt has been processed
— Interrupts handled in sequence as they occur
— Used in Multiple Interrupt - Sequential
2. Define priorities
— Low priority interrupts can be interrupted by higher
priority interrupts
— When higher priority interrupt has been processed,
processor returns to previous interrupt
— Used in Multiple Interrupt - Nested
Multiple Interrupts - Sequential

Disable Interrupt Approach

Disable Interrupt Approach
• Advantage
—Nice and simple
• Disadvantage
—Does not take into account relative priority
and time-critical needs.
Multiple Interrupts – Nested

Define Priorities Approach

Time Sequence of Multiple Interrupts
(cont.) Time Sequence of
Multiple Interrupts
Interrupt - Exception

• No interrupt is required for operation

not involving processor e.g. DMA
(Direct Memory Access).
— In some cases, I/O devices can operate
directly with memory without depending
on processor.
— When processor is bypassed (not using
processor), then interrupt is not needed.
— Direct memory access (DMA) can be used
for data exchanges between I/O device
and memory (not controlled by processor).
Exercise 1

Due date: Next week

THANK YOU