VERILOG – Behavioral Modeling

Anand S Moghe

* ANAND S MOGHE 1
 Behavioral Modeling
• Behavioral modeling enables you to describe a system at a
high level of abstraction. (At this level of abstraction, implementation is
not as important as the high-level description of a functional block or of the
system.)

• Behavioral modeling in Verilog is described by specifying a set

of concurrently active procedural blocks in a high level
programming language that together describe the operation
of the system.
• High level programming language constructs are available in
Verilog for behavioral modeling. Some of these are:
– Assignment statements
– Looping statements
– Conditional statements

* ANAND S MOGHE 2
 Continuous assignments
• Continuous assignments drive values on to a net (wire).

• Any changes in the RHS of the continuous assignment are evaluated and
the LHS is updated.

• You can model combinational logic with continuous assignment

statements.
• Continuous assignments drive a wire that has been previously declared.
• example:
wire out;
assign out = a & b;

wire #10 inv = ~in; // evaluated and assigned at 10 units

wire eq;
assign eq = (a == b); // assigns ‘1‘ only if a equals b; else assigns ‘0’

* ANAND S MOGHE 3
 Conditional operator
• Conditional operator is similar to a case statement (seen later). The value
assigned to the LHS is the one that results true from the expression
evaluation.

assign out = ((a+b)? in : 1‘bz);

in out

enable

* ANAND S MOGHE 4
 Conditional operator .. cont
module mux_1 (out, in1, in2, in3, in4, sel);
parameter WIDTH = 8
output [WIDTH-1:0] out;
input [WIDTH-1:0] in1, in2, in3, in4;
input [1:0] sel;

//wire [3:0] out;

assign out = (sel == 2’b00)? in1:

(sel == 2’b01)? in2:
(sel == 2’b10)? in3:
(sel == 2’b11)? in4:
4’bx;
endmodule

• The default value is specified to ensure proper behavior for any case that
is not encountered. In the above example, it would be when one of the
bits of sel[1:0] is unknown.

* ANAND S MOGHE 5
 Concatenation and replication operators
• For swapping the bytes in a word, the following statement can be used:
wire [15:0] word, swapped_word;
swapped_word = {word[7:0], word[15:8]};

• For usage of concatenation operator on the LHS, the following can be an example:
module add_32 (c0, sum, a, b, ci);
output c0;
output [31:0] sum;
input [31:0] a, b;
input ci;
assign #10 {c0, sum} = a + b + ci;
endmodule

• Bit replication example to generate 8’b0101_0101

byte = {4{2’b01}};

• Sign extension:
word = {{8{byte[7]}},byte};

* ANAND S MOGHE 6
 Timing control in procedural blocks
• Procedural blocks are the basis for behavioral modeling.
• Procedural blocks are of two types:
– initial procedural block that executes only once
– always procedural blocks that execute in a continuous loop which has timing control
• Procedural blocks have the following components:
– Procedural assignment statements to describe the data flow within the block
– Timing controls to control the triggering of the block and the execution of the
statements in the block.
– High-level programming language constructs that describe the functional operation of
the block.

initial always
c c
c c
c c
c c
c c
c c
c c
c c

* ANAND S MOGHE 7
 Timing control in procedural blocks
• Procedural blocks’ timing is specified using 3 types of timing controls:
– Simple delay.
#10 regA = regB;
#(cycle/2) clk = ~clk; // cycle is declared as a parameter
This delays the execution for a specific number of simulation time steps.

– Edge triggered timing control:

@(posedge clk) regA = regB; // controlled by positive edge
@(negedge clk) rega = regb; // controlled by negative edge
@(x or y) rega = regb; // controlled by both edges (basically change in x or y)
This delays the execution until an edge occurs on the <signal>. Several <signal>
arguments can be specified using the ‘or’ keyword.

– Level triggered timing control

wait (set); // controlled by a logic high on set signal.

* ANAND S MOGHE 8
 Timing control in procedural blocks
10 30 50 70 90 110 130 150

clk

set
15 48 71

q
33 43 93 103

always wait(set)
begin
@(posedge clk) always #5
#3 q = 1; clk = ~clk;
#10 q = 0;
wait(!set);
end
• Posedge at 10 is ignored since it is waiting for set = 1; Posedge at 30 is caught and
q = 1 at 33 followed by q=0 at 43.
• Set goes low at 48; caught by wait(!set)
• Now waiting for set = 1 which happens at 71; posedge at 90 is caught. q=1 at 93
*
and q=0 at 103. Loop repeats. ANAND S MOGHE 9
 Timing control in procedural blocks
• Assignments made in procedural blocks are known as procedural assignments.
module dff (q, qb, d, clk);
output q, qb;
input d, clk;
reg q, qb;
always @(posedge clk) begin
#5 q <= d;
#1 qb <= ~d;
end
endmodule

• The LHS of a procedural assignment must be a data type of register class.

• The RHS of a procedural assignment can be any valid expression. The data types
used in the right-hand side expression are not restricted.
• If you forget to declare a signal, it defaults to a wire and so when it is used on the
left hand side of the assignment in a procedural block, it gives an error message:
“illegal left hand side assignment”.

* ANAND S MOGHE 10
 Block statements
• Block statements are used to group two or more statements together, so they act
as one statement syntactically.
• Sequential block statements are enclosed between the keywords begin and end.
The statements in this block are executed in sequential manner.
• Parallel block statements are grouped together between the keywords fork and
join. The statements in this block are executed concurrently (concurrent with
respect to simulation time).

always c always c initial c initial c

begin fork begin fork
c c c c
c c c c
c c c c
c c c c
c c c c
c c c c
end join end join

* ANAND S MOGHE 11
 Nonblocking procedural statements
• Non-blocking assignments in Verilog are meant for modeling sequential elements
like flip flops.
module swap_values;
reg a, b, c;
initial begin // executes in simulation time step 0
a = 0;
b = 1;
c = 0;
end
b tn e
always @(posedge c)
begin
b <= a; // read a, write into a_temp=0;
a <= b; // read b, write into b_temp=1; nonblocking assignment swaps the values
of a and b; a=1; b=0
end
endmodule
• A nonblocking statement allows the assignments without blocking the procedural
flow
• The assignment happens in two steps:
– The simulator evaluates all the RHS expressions and schedules the assignments to take
place at the time specified by the timing control.
– At the end of the time step in which the delay has expired, the simulator executes the
assignment by assigning the value to the LHS expression
* ANAND S MOGHE 12
Stratified Event Queue

ANAND S MOGHE
 Nonblocking procedural assignments
// non-block1.v
module non_block1;

reg a, b, c, d, e, f;
// blocking assignments
initial begin
The simulator assigns 1 to register a
a = #10 1;
b = #2 0;
at simulation time 10, assigns 0 to register
c = #4 1; b at simultation time 12, and assigns 1
end to register c at simulation time 16
// nonblocking assignments
initial begin
d <= #10 1;
The simulator assigns 1 to register d
e <= #2 0;
at simulation time 10, assigns 0 to register
f <= #4 1;
end e at simulation time 2, and assigns 1
initial begin to register f at simulation time 4
$monitor($time, “a=%3d b=%3d c=%3d
d=%3d e=%3d f=%3d”, a, b, c, d, e,
f);
end
endmodule

* ANAND S MOGHE 14
 Conditional statements – if / if-else
• if and if-else statements

if (index > 0) // beginning of outer if

if (regA > regB) // beginning of the 1st inner if
result = regA;
else
result = 0; // end of the 1st inner if
else
if (index == 0) // 2nd inner if
$display(“note: index is zero”);
else
$display(“note: index is negative”);

• In nested if sequences, the else is associated with the closest previous if.
• To ensure proper readability and proper association, use begin-end block
statements.

* ANAND S MOGHE 15
 Conditional statements – if / if-else
if (sel == 0)
out = a;
a
else out
out = b;
b
sel

* ANAND S MOGHE 16
 Conditional statements.. cont
• case statement: example case expression
case (opcode)
3’b000: result = regA + regB;
3’b001: result = regA - regB;
3’b010, controlling expression
3’b100: result = ‘bx;
default: begin
result = ‘bx;
$display(“no match”);
end
endcase
• The case statement is a multiway conditional statement that tests whether the
expression matches one of a number of other expressions, and branches
accordingly.
• The case statement does a bit-by-bit comparison for an exact match; the default
statement is optional; It is executed when none of the previous statements match
the case expression.
• Use of multiple default statements is illegal.
• It is always good practice to use the default statement especially to check for x
(unknown) values.
* ANAND S MOGHE 17
 Conditional statements.. cont
• case / casex / casez matching
case casex casez
0 = 0 0 = 0 0 = 0
1 = 1 1 = 1 1 = 1
x = x x = 0,1,x,z x = x
Z = z z = 0,1,x,z z = 0,1,x,z

The ? (question mark) character is a verilog alternative for the z character.

• It is good programming practice to use casez instead of casex when dealing with
RTL code.

* ANAND S MOGHE 18
 Case and if-else statements.. comparison
• Comparison of case and if-else statements
– case is more compact than if-else statement
– Any set of general expression can be used with if-else statement
– With the case statement, the case expression are all evaluated against a common
expression
– case comparison is done using a 4-value logic – 0, 1, x, z
– case expression and controlling expression width should match. In contrast, the if-else
expression involving x or z bits may result in an x or z value which might be interpreted
as FALSE.
casez and casex :
– casez and casex are two variants of the basic case statement
– casez allows for ‘z’ to be treated as don’t-care.
– casex allows for both ‘z’ and ‘x’ to be treated as don’t care

• casez and casex are similar in syntax to case , except that the casez or casex
keyword is substituted for case .

* ANAND S MOGHE 19
 Case and if-else statements.. comparison
• Example
module decode
sensitivity list
reg [7:0] r;
reg [7:0] mask;

always @(r or mask) begin

// other statements go here…..
mask = 8’bx0x0x0x0; // every other bit is masked
casex (r ^ mask) // XOR
8’b001100xx : statement1;
8’b1100xx00 : statement2;
8’b00xx0011 : statement3;
8’bxx001100 : statement4;
endcase
end
endmodule
• In this example we have loaded the mask with the 8-bit value x0x0x0x0, indicating
that every other bit is ‘x’. If r = 8’b01100110, then the statement2 will be executed,
since: (x0x0x0x0) ^ (01100110) = x1x0x1x0.
• Since the unknown ‘x’ is treated as a don’t care, then only statement2 will be
executed. Although the expression for statement4 also matches, it will not be
executed because the condition on statement2 was found first.

* ANAND S MOGHE 20
 Looping statements..
• Repeat Loop
module multiplier (result, op_a, op_b);
parameter size = 8;
input [size-1:0] op_a, op_b;
output [2*size:0] result;

reg [2*size:0] shift_opa, shift_opb;

always @(op_a or op_b) begin

result = 0;
shift_opa = op_a; // zero extend left
shift_opb = op_b;
repeat (size) begin
#10 if (shift_opb[1]) result = result + shift_opa;
shift_opa = shift_opa << 1; // logical left shift
shift_opb = shift_opb >> 1; // logical right shift
end
end
endmodule
• A repeat loop executes a block of statements a fixed number of times.
• The code above implements a shift-and-add multiplier.

* ANAND S MOGHE 21
 Looping statements..
• while Loop
...
...
reg [7:0] tempreg;
. . .
. . .
while (tempreg) begin
if (tempreg[0]) count = count + 1;
tempreg = tempreg >> 1; // right shift
end
endmodule

• A while loop executes a block of statements as long as its expression is true (or
nonzero)
• If the expression starts out false, the statements are not executed.

* ANAND S MOGHE 22
 Looping statements..
• for Loop
...

for (index=0; index<size; index=index+1)

if (val[index] == 1’bx)
$display (“found an X”);

for (i=10; i>index; i=i-1)

memory[i] = 1’b0;

• The for loop executes as long as the condition evaluates to TRUE.

• The for loop functionality can be implemented with a while loop, but this
requires separate initialization and counter incrementing assignments, that are
now included as a part of the for loop.

* ANAND S MOGHE 23