Field-Effect Transistors

Topic 6 (Chapter 6)
 Basic Difference Between BJT and
FET
• The BJT is a current-controlled device
• The FET is a voltage-controlled device.
 FETs vs. BJTs
Similarities: 1. Both are Transistors
2. Amplifiers
3. Switching devices
4. 3 terminal devices

Differences: 1. BJTs are bipolar. FETs are unipolar.

2. FETs are voltage controlled devices. BJTs
are current controlled devices.
3. FETs have higher input impedance. BJTs
have higher gain.
4. FETs are less sensitive to temperature
variations and are better suited for integrated
circuits.
5. FETs are smaller than BJTs.
6. FET have faster switching speed than BJT.
 FET Types

JFET: Junction FET (Not in our syllabus. Not used NOW)

MOSFET: Metal–Oxide–Semiconductor FET

D-MOSFET: Depletion MOSFET

E-MOSFET: Enhancement MOSFET

 MOSFET TYPES
• Two types:
1. Depletion type
2. Enhancement type

• Both of the above types have two sub-types:

1. N-channel or simply n-type (also called NMOS in short)
2. P-channel or simply p-type (also called PMOS in short)
 Some Facts..

• The name MOSFET is derived from its

physical structure.
– Metal Oxide Semiconductor Field Effect
Transistor
• However, MOSFET’s gates do not actually
use any “metal”, polysilicon is used instead.
• Another name for MOSFET is insulated
gate FET, or IGFET.
ENHANCEMENT-TYPE MOSFET

E-MOSFET
 E-Type MOSFET Construction
The Drain (D) and Source (S) connect to the to n-type regions.

The Gate (G) connects to the p-type

substrate via a thin insulating layer of
silicon dioxide (SiO2)

There is no channel!
The n-type material lies on a p-type
substrate that may have an additional
terminal connection called the
Substrate (SS) or Body (B)
Channel formation in the n-channel
enhancement-type MOSFET
 minimum
• 𝑽 𝑮𝑺
 Field-Effect
• The gate and the channel region of the MOSFET
form a parallel-plate capacitor
– The oxide layer acts as the capacitor dielectric
• The channel conductivity and the current that flows
through the channel is determined by the electric
field in the channel
– Caused by an applied gate voltage, vGS
– This is the origin of the name “field-effect transistor” (FET)
• A current flows when a voltage vDS is applied
• Potential difference created by vDS
• Channel created by vGS
•
 Change in channel and depletion
region with VDS increasing and
a fixed value of VGS

fixed
increases
decreases
Channel width
decreases at
drain
 E-Type MOSFET Operation
The enhancement-type MOSFET (E-MOSFET) operates only
in the enhancement mode.
 E-Type MOSFET Transfer Curve

ID  k (VGS  VT )2 Where, VT = the E-MOSFET threshold voltage

k, a constant, can be determined by using ID(ON)

k
values at a specific point and the formula: (VGS(ON)  VT)2
 EMOSFET Current Equation
• Off Region ( < ) OR ( = )

• Linear/Triode/Ohmic Region ( < ) & (>)

• Saturation Region ( ) & ( > )

= Transconductance parameter (A/V2)

Overdrive or Effective voltage
 EMOSFET Current Problem
• For an enhancement NMOS, = 1 mA/V2, = 3 V.
(a) = 2 V, = 10 V; (b) = 5 V, = 0 V
(c) = 5 V, = 1 V; (d) = 5 V, = 6 V
• The NMOS is in which region? Why? Find , and .
Write unit.
(a) = 2 V = 3 V. OFF Region.
• . Always
(b) = 5 V = 3 V, BUT: = 0 V.OFF Region.
• . Always
 EMOSFET Current Problem
(c) = 5 V = 3 V. 0 V.
• Linear/Ohmic/Triode Region ( )

. Always
(d) = 5 V = 3 V. 0 V.
• Saturation Region ( )
. Always
PMOS transistors Enhancement Type

• Similar to the NMOS

transistor
– except that all
semiconductor
regions are reversed
in polarity
MOSFET Symbols
• The symbols try to reflect the
actual construction of the device.
• The dashed line between drain
and source is chosen to reflect the
fact that a channel does not exist
between the two under no-bias
conditions.
• It is, in fact, the only difference
between the symbols for the
depletion-type and enhancement-
type MOSFETs.
• NMOS: source current leaves the
NMOS.
• PMOS: source current enters the
PMOS.
6.7 Depletion-Type MOSFET Construction
• The Drain (D) and
Source (S) connect to the
to n-type regions.
– The n-typed regions are
connected via an n-channel.
– The n-channel is connected
to the Gate (G) via a thin
insulating layer of silicon
dioxide (SiO2).
• The n-type material lies on
a p-type substrate or body
that may have an additional
terminal connection called
the Substrate (SS).
 D-Type MOSFET Structures

P-channel DMOS N-channel DMOS

Same as Enhancement EMOS.
Only difference: N/P channel exists between drain and source before
applying any voltage
D-Type MOSFET Symbols
• The symbols try to reflect the actual
construction of the device.
• The lack of a direct connection (due to
the gate insulation) between the gate
and the channel is represented by a
space between the gate and the other
terminals of the symbol.
• The vertical line representing the
channel is connected between the drain
and the source and is “supported” by the
substrate.
• Two symbols are provided for each type
of channel to reflect the fact that in
some cases the substrate is externally
available, whereas in others it is not.
• For most of our analysis, the substrate
and the source will be connected and
the lower symbols will be employed.
 Complementary MOS or CMOS
• Most widely used of all the IC technologies
– Applies to both analog and digital circuits
• CMOS is preferred over BJT in digital applications:
– Less power.
– Higher input impedance.
– Scaling is easier
 CMOS Devices
CMOS (complementary MOSFET) uses a p-channel and
n-channel MOSFET; often on the same substrate.

• Another arrangement is also possible in which an n-

type body is used and the n device is formed in a p
well
 Digital Logic Inverters
• Most basic element in design of digital circuits.

Figure: A logic inverter operating from a dc supply VDD.

CMOS Logic Design: CMOS Inverter

Input 1, Output 0

Input 0, Output 1
 FET Biasing

(We will limit our discussion to only E-MOSFET.)

 Mathematical Vs. Graphical
Approach
• The relationship between input VGS and output ID is
nonlinear, which complicates the mathematical approach to the dc
analysis.
• We want to design Amplifier with MOSFET
• MOSFET will be in Saturation Region
• Current is constant in Saturation region

• A graphical approach is less accurate but quicker

• We will use graphical solutions rather than mathematical
solutions.
FET General Relationships for
DC Analysis
Plotting The E-MOSFET Transfer Curve

• Once k is defined, other levels of ID can be determined for the

chosen values of VGS
• Determining about 3 to 4 points enables drawing the device
transfer characteristics.
 Voltage-Divider Biasing

Plot the line and the transfer

curve to find the Q-point using
these equations:

= 0; =

R2VDD
VG 
R1  R2
VGS  VG  ID RS
VDS  VDD  ID (RS  RD )
 Voltage-Divider Bias Q-Point
(E-MOSFET)
Network: Plot the line using
VGS = VG , ID = 0 A
ID = VG / RS , VGS = 0 V

Device: Using the following values

from the spec sheet, plot the
transfer curve:
VGSTh, ID = 0 A
VGS(on) , ID(on)

The point where the line and the

transfer curve intersect is the Q-
point.

Using the value of ID at the Q-point,

solve for the other circuit values.
For the NMOS below, and
Draw the device/characteristics curve and load line of the NMOS.
Show the Q-point in the graph. Step 0: Give appropriate current
Find , , , and . directions for the 3 terminals.
+20V

+40V
Step 1: Drawing Load Line from
KVL at Gate-Source.
4 kΩ
Step 2: Draw device/
4 MΩ
characteristics curve from
MOSFET current equation.

Step 3: Get -point from the

5 MΩ intercept of Load Line and
device/characteristics curve.
2 kΩ
Step 4: Find from KVL at Drain-
-3V Source
For the NMOS below, and
Draw the device/characteristics curve and load line of the NMOS.
Show the Q-point in the graph.
Find , , , and .
+20V

+40V
4 kΩ

4 MΩ

5 MΩ

2 kΩ

-3V
For the NMOS below, and
Draw the device/characteristics curve and load line of the NMOS.
Show the Q-point in the graph.
Find , , , and .
+20V

+40V
4 kΩ

4 MΩ

5 MΩ

2 kΩ

-3V
 Step 1: Drawing Load Line
from KVL at Gate-Source:
+20V

+40V
4 kΩ

4 MΩ

𝑰𝑫
G

𝑰 𝑮=𝟎 5 MΩ
𝑰𝑺
2 kΩ

-3V
Step 2: Drawing device/characteristics curve from MOSFET
current equation:
;

, Always
Step 4: Find from KVL at
Drain-Source

We know:
Special Case: If is not given. But is given
Given, at
 FET Amplifiers

(We will limit our discussion to only E-MOSFET.)

 E-Type MOSFET AC Equivalent
An open-circuit between gate
and drain–source channel

gm and rd can be
found in the
specification sheet
for the FET.
 Determining gm

The constant k can be determined from a given typical

operating point on a specification sheet
Common-Source Voltage-Divider Bias

The input is applied to the gate and

the output is taken from the drain.

There is a 180º voltage phase

shift between input and output.
 Calculations

Input impedance:
Z i R 1||R2

Output impedance:
Zo  rd ||RD
Z o  RD rd 10

Voltage gain: Av  g m (rd ||R D ) Av  g m RD rd 10 RD

 Thank You!

It was great having you in the class!

Best of luck!