Central Processing Unit

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 CENTRAL PROCESSING
UNIT

• Introduction
• General Register Organization
• Stack Organization
• Instruction Formats
• Addressing Modes

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 Central Processing Unit

• The CPU is made up of 3 major Components.

• The CPU performs a variety of functions dictated by the
type of instructions that are incorporated in the computer
• In programming, memory locations are needed for
storing pointers, counters, return addresses, temporary
result , etc. Memory access is most time consuming
operation in a computer.
• It is then more convenient and more efficient to store
these intermediate values in processor registers, which
are connected through common bus system.

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 MAJOR COMPONENTS OF CPU
Storage Components:
Registers
Flip-flops

Execution (Processing) Components:

Arithmetic Logic Unit (ALU):
Arithmetic calculations, Logical computations, Shifts/Rotates

Transfer Components:
Bus

Control Components:
Control Unit
Register
File ALU

Control Unit
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 Chapter 7

Instruction
• CPU components

– Register Set : stores immediate data used during the execution

of the instructions

– Arithmetic Logic Unit (ALU) : performs the required µoperations

for executing the instructions

– Control Unit : supervises the transfer of information among the

registers and instructs the ALU as to which operation to perform

Register set

Control

Arithmetic
Logic unit
Fig. 8-1 Major component of CPU (ALU)
 Central Processing
General Register Organization

• The design of a CPU is a task that

involves choosing the hardware for
implementing the machine instructions.
• Lets describe how the registers
communicate with the ALU through buses
and explain the operation of the memory
stack.

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 General Registers
Chapter 8

Organization
• Register set with common ALU
Clock Input

R1
R2
R3
R4
R5
R6
R7

Load SELA MUX MUX SELB

(7 lines)

3×8 A Bus B Bus

decoder

Arithmetic logic unit

OPR
SELD (ALU) 3 3 3 5
SELA SELB SELD OPR

(a) Block diagram Output (b) Control word

Fig. 8-2 Register set with common ALU

 General Registers
Chapter 8

Organization
• Control Word
Tab. 8-1 Example of µoperations for the CPU Tab. 8-2 Encoding of ALU operations

Binary OPR
Code SELA SELB SELD Select Operation Symbol
000 Input Input None 00000 Transfer A TSFA
001 R1 R1 R1 00001 Increment A INCA
010 R2 R2 R2 00010 Add A + B ADD
011 R3 R3 R3 00101 Subtract A – B SUB
100 R4 R4 R4 00110 Decrement A DECA
101 R5 R5 R5 01000 AND A and B AND
110 R6 R6 R6 01010 OR A and B OR
111 R7 R7 R7 01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA

3 3 3 5
SELA SELB SELD OPR

(b) Control word

 Example of Microoperations:

R1 ←R2+R3

• To Perform this operation, the control must provide binary selection

variables to the following selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A.
2. MUX B selector (SELB): to place the content of R3 into bus B.
3. ALU operation selector (OPR): to provide the arithmetic addition
A+B.
Decoder destination selector (SELD): to transfer the content of the
output bus into R1.
There are therefore 14 binary selection inputs , and their combination
value specifies a control word) See Tables 8-1, 8-2 & 8-3 (Morris
Mano))
A control Word (CW) is a word whose individual bits represent a
various control signals.

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 STACK ORGANIZATION
• A useful feature that is included in the CPU of most
computers is a stackor LIFO(Last in First Out).
• Stack is a storage structure that stores information in
such a way that the last item stored is the first item
retrieved.
• It is based on the principle of LIFO (Last-in-first-out).
• The stack in digital computers is a group of memory
locations with a register that holds the address of top of
element
• This register that holds the address of top of element of
the stack is called Stack Pointer.
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• Stack Operations
The two operations of a stack are:
• Push: Inserts an item on top of stack.
• Pop: Deletes an item from top of stack.
• Implementation of Stack
In digital computers, stack can be implemented
in two ways:
• Register Stack
• Memory Stack
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 Register Stack

• A stack can be organized as a collection of finite number of registers

that are used to store temporary information during the execution of
a program. The stack pointer (SP) is a register that holds the
address of top of element of the stack.
• A stack can be placed in a portion of a large memory or it can be
organized as a collection of a finite number of memory words or
registers. Figure 3 shows the organization of a 64-word register
stack.
• The stack pointer register SP contains a binary number whose value
is equal to the address of the word that is currently on top of the
stack. Three items are placed in the stack: A, B, and C, in that
order. Item C is on top of the stack so that the content of SP is now
3.

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13
To remove the top item, the stack is popped by reading the memory word at
address 3 and decrementing the content of SP.
Item B is now on top of the stack since SP holds address 2. To insert a new
item, the stack is pushed by incrementing SP and writing a word in the next-higher
location in the stack. Note that item C has been read out but not physically removed.
This does not matter because when the stack is pushed, a new item is written in
its place. In a 64-word stack, the stack pointer contains 6 bits because 26 = 64.
Since SP has only six bits, it cannot exceed a number greater than 63 (111111 in
binary). When63 is incrementedby 1, the resultis 0 since 111111 + 1 = 1000000 in
binary, but SP can accommodate only the six least significant bits.
Similarly, when 000000 is decremented by 1, the result is 111111. The one-bit
register FULL is set to 1 when the stack is full, and the one-bit register EMTY is set
to 1 when the stack is empty of items. DR is the data register that holds the binary
data to be written into or read out of the stack.
Initially, SP is cleared to 0, EMTY is set to 1, and FULL is cleared to 0, so that SP
points to the word at address 0 and the stack is marked empty and not full. If the
stack is not full (if FULL = 0), a new item is inserted with a push operation.
The push operation is implemented with the following sequence of microoperations;

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• SP ← SP + 1 Increment stack pointer M[SP] ← DR Write item on top of the stack
If (SP = 0) then (FULL ←1) Check if stack is full
• EMTY ← 0 Mark the stack not empty
• The stack pointer is incremented so that it points to the address of the next-
higher word. A memory write operation inserts the word from DR into the top of
the stack. Note that SP holds the address of the top of the stack and that M[SP]
denotes the memory word specified by the address presently available in SP.
The first item stored in the stack is at address L The last item is stored at
address 0.
If SP reaches 0, the stack is full of items, so FULL is set to L This condition is
reached if the top item prior to the last push was in location 63 and, after
incrementing SP, the last item is stored in location 0.
Once an item is stored in location 0, there are no more empty registers in the
stack. If an item is written in the stack, obviously the stack cannot be empty, so
EMTY is cleared to 0.
A new item is deleted from the stack if the stack is not empty (if EMTY = 0). The
pop operation consists of the following sequence of microoperations
• DR ← M[SP] Read item from the top of stack SP ← SP - 1 Decrement
stack pointer If (SP = 0) then (EMTY ← 1) Check if stack is empty
FULL ← 0 Mark the stack not full
• The top item is read from the stack into DR . The stack pointer is
then decremented. If its value reaches zero, the stack is empty, so
EMTY is set to 1.
This condition is reached if the item read was in location 1. Once
this item is read out, SP is decremented and reaches the value 0,
which is the initial value of SP. Note that if a pop operation reads the
item from location 0 and then SP is decremented, SP changes to
111111, which is equivalent to decimal 63.
In this configuration, the word in address 0 receives the last item in
the stack. Note also that an erroneous operation will result if the stack
is pushed when FULL = 1 or popped when EMTY = 1

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 Memory Stack

• A stack can also be implemented in a random-access

memory attached to a CPU. The implementation of a
stack in the CPU is done by assigning a portion of
memory to a stack operation and using a processor
register as a stack pointer.
• Figure 4 shows a portion of computer memory
partitioned into three segments: program, data, and
stack. The program counter PC points at the address of
the next instruction in the program. The address register
AR points at an array of data.
•

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18
• The stack pointer SP points at the top of the stack. The three registers
are connected to a common address bus, and either one can provide an
address for memory.
PC is used during the fetch phase to read an instruction. AR is used
during the execute phase to read an operand.
SP is used to push or pop items into or the stack. If the initial value of SP
is 4001 and the stack grows with decreasing addresses.
Thus the first item stored in the stack is at address 4000, the second item
is stored at address 3999, and the last address that can be used for the
stack Is 3000.
No provisions are available for stack limit checks.
We assume that the items in the stack communicate with a data register
DR . A new item is inserted with the push operation as follows:

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• SP ← SP - 1 M[SP] ← DR
• The stack pointer is decremented so that
it points at the address of the next word. A
memory write operation inserts the word
from DR into the top of the stack. A new
item is deleted with a pop operation as
follows:
• DR ← M[SP] SP ← SP + 1

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• The top item is read from the stack into DR. The stack pointer is
then incremented to point at the next item in the stack.
Most computers do not provide hardware to check for stack
overflow (full stack) or underflow (empty stack).
The stack limits can be checked by using two processor registers:
one to hold the upper limit (3000 in this case), and the other to hold
the lower limit (4001 in this case).
After a push operation, SP is compared with the upper-limit
register and after a pop operation, SP is compared with the lower-
limit register.
The two microoperations needed for either the push or pop are (1)
an access to memory through SP, and (2) updating SP. Which of
the two microoperations is done first and whether SP is updated by
incrementing or decrementing depends on the organization of the
stack.

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• In Fig. 4 the stack grows by decreasing the memory address. The
stack may be constructed to grow by increasing the memory
address as in Fig. 3.
In such a case, SP is incremented for the push operation and
decremented for the pop operation. A stack may be constructed so
that SP points at the next empty location above the top of the stack.
In this case the sequence of microoperations must be
interchanged. A stack pointer is loaded with an initial value. This
initial value must be the bottom address of an assigned stack in
memory. Henceforth, SP is automatically decremented or
incremented with every push or pop operation.
The advantage of a memory stack is that the CPU can refer to it
without having to specify an address, since the address is always
available and automatically updated in the stack pointer.

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 INSTRUCTION FORMAT
• A computer will usually have a variety of instruction
code formats. It is the function of the control unit within the
CPU to interpret each instruction code and provide the
necessary control functions needed to process the
instruction.
The format of an instruction is usually depicted in a
rectangular box symbolizing the bits of the instruction as
they appear in memory words or in a control register. The
bits of the instruction are divided into groups called fields.
The most common fields found in instruction formats are:

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 Instruction Format

INSTRUCTION FORMAT
Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(s) or a processor register(s)
Mode field - specifies the way the operand or the
effective address is determined
The number of address fields in the instruction format
depends on the internal organization of CPU

- The three most common CPU organizations:

Single accumulator organization:

ADD X /* AC  AC + M[X] */
General register organization:
ADD R1, R2, R3 /* R1  R2 + R3 */
ADD R1, R2 /* R1  R1 + R2 */
MOV R1, R2 /* R1  R2 */
ADD R1, X /* R1  R1 + M[X] */
Stack organization:
PUSH X /* TOS  M[X] */
ADD
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• Other special fields are sometimes employed under
certain circumstances, as for example a field that gives
the number of shifts in a shift-type instruction. The
operation code field of an instruction is a group of bits
that define various processor operations, such as add,
subtract, complement, and shift.
The bits that define the mode field of an instruction
code specify a variety of alternatives for choosing the
operands from the given address.

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• Operations specified by computer instructions are executed on
some data stored in memory or processor registers. Operands
residing in memory are specified by their memory address.
Operands residing in processor registers are specified with a
register address.
A register address is a binary number of k bits that defines one of
'2k' registers in the CPU. Thus a CPU with 16 processor registers R0
through R15 will have a register address field of four bits.
The binary number 0101, for example, will designate register RS.
Computers may have instructions of several different lengths
containing varying number of addresses. The number of address
fields in the instruction format of a computer depends on the internal
organization of its registers. Most computers fall into one of three
types of CPU organizations:

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 Three-address instruction
• Computers with three-address instruction
formats can use each address field to specify
either a processor register or a memory
operand. The program in assembly language
that evaluates X = (A + B) * (C + D) is shown
below, together with comments that explain
the register transfer operation of each
instruction.
•

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 Two-address instructions
• Two-address instructions are the most
common in commercial computers. Here
again each address field can specify either
a processor register or a memory word.
The program to evaluate X = (A + B) * (C
+ D) is as follows:

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 One-Address Instructions

• One-address instructions use an implied

accumulator (AC) register for all data
manipulation. For multiplication and division there
is a need for a second register. However, here
we will neglect the second register and assume
that the AC contains the result of all operations.
The program to evaluate X = (A + B) * (C + D) is
•

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 Zero-Address Instructions

• A stack-organized computer does not

use an address field for the instructions
ADD and MUL. The PUSH and POP
instructions, however, need an address
field to specify the operand that
communicates with the stack. The following
program shows how X = (A + B) * (C + D)
will be written for a stack organized
computer. (TOS stands for top of stack.)
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 THREE, and TWO-ADDRESS
INSTRUCTIONS
Three-Address Instructions:

Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B /* R1  M[A] + M[B] */
ADD R2, C, D /* R2  M[C] + M[D] */
MUL X, R1, R2 /* M[X]  R1 * R2 */

- Results in short programs

- Instruction becomes long (many bits)

Two-Address Instructions:
Program to evaluate X = (A + B) * (C + D) :

MOV R1, A /* R1  M[A] */

ADD R1, B /* R1  R1 + M[B] */
MOV R2, C /* R2  M[C] */
ADD R2, D /* R2  R2 + M[D] */
MUL R1, R2 /* R1  R1 * R2 */
MOV X, R1 /* M[X]  R1 */
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ONE, and ZERO-ADDRESS INSTRUCTIONS
One-Address Instructions:
- Use an implied AC register for all data manipulation
- Program to evaluate X = (A + B) * (C + D) :
LOAD A /* AC  M[A] */
ADD B /* AC  AC + M[B] */
STORE T /* M[T]  AC */
LOAD C /* AC  M[C] */
ADD D /* AC  AC + M[D] */
MUL T /* AC  AC * M[T] */
STORE X /* M[X]  AC */
Zero-Address Instructions:
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A /* TOS  A */
PUSH B /* TOS  B */
ADD /* TOS  (A + B) */
PUSH C /* TOS  C */
PUSH D /* TOS  D */
ADD /* TOS  (C + D) */
MUL /* TOS  (C + D) * (A + B) */
POP X /* M[X]  TOS */
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 ADDRESSING MODES
• The addressing mode specifies a rule for interpreting or
modifying the address field of the instruction before the
operand is actually executed.
• Computers use addressing mode techniques for the
purpose of accommodating one of the following provisions:
• 1. To give programming versatilities to the user to be more
flexible.
• 2. To reduce the number of bits in the addressing field of
the instruction.
• In some some computers, the addressing mode of the
instruction is specified with distinct binary code.

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• Instruction format with mode field

• Other computers use a single binary for operation &

address mode.
• The mode field is used to locate the operand.
• Address field may designate a memory address or a
processor register.
• There are 2 modes that need no address field at all
(Implied & immediate modes).
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 TYPES OF ADDRESSING MODES

The most well known addressing mode then are:

• Implied mode.
• Immediate mode
• Register mode
• Register Indirect mode
• Auto-increment or Auto-decrement mode
• Direct Mode
• Indirect Mode
• Relative Address Mode
• Index Addressing Mode
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 TYPES OF ADDRESSING MODES
Implied Mode
Address of the operands are specified implicitly
in the definition of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP], EA: Effective Address.

Immediate Mode
Instead of specifying the address of the operand,
operand itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand

Register Mode
Address specified in the instruction is the register address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory addressing
- EA = IR(R) (IR(R): Register field of IR)
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 TYPES OF ADDRESSING MODES
Register Indirect Mode
Instruction specifies a register which contains
the memory address of the operand
- Saving instruction bits since register address
is shorter than the memory address
- Slower to acquire an operand than both the
register addressing or memory addressing
- EA = [IR(R)] ([x]: Content of x)

Auto-increment or Auto-decrement features:

Same as the Register Indirect, but:
- When the address in the register is used to access memory, the
value in the register is incremented or decremented by 1 (after or
before the execution of the instruction)

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 TYPES OF ADDRESSING
MODES
Direct Address Mode
Instruction specifies the memory address which
can be used directly to the physical memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address
for a large physical memory space
- EA = IR(address), (IR(address): address field of IR)

Indirect Addressing Mode

The address field of an instruction specifies the address of a memory
location that contains the address of the operand
- When the abbreviated address is used, large physical memory can
be addressed with a relatively small number of bits
- Slow to acquire an operand because of an additional memory
access
- EA = M[IR(address)]

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 TYPES OF ADDRESSING
MODES
Relative Addressing Modes
The Address fields of an instruction specifies the part of the address
(abbreviated address) which can be used along with a
designated register to calculate the address of the operand

PC Relative Addressing Mode(R = PC)

- EA = PC + IR(address)

- Address field of the instruction is short

- Large physical memory can be accessed with a small number of
address bits

Indexed Addressing Mode

XR: Index Register:
- EA = XR + IR(address)
Base Register Addressing Mode
BAR: Base Address Register:
- EA = BAR + IR(address)
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Applications of Addressing
Modes

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41
 Example
• The two-word instruction at address 200 and 201 is a
"load to AC" instruction with an address field equal to
500.
• The first word of the instruction specifies the operation
code and mode, and the second word specifies the
address part.
• PC has the value 200 for fetching this instruction. The
content of processor register R1 is 400, and the content
of an index register XR is 100.
• AC receives the operand after the instruction is
executed.
• Find the Effective Address and operand that must be
loaded into AC for each possible mode.
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 ADDRESSING MODES - EXAMPLES
Address Memory
200 Load to AC Mode
PC = 200 201 Address = 500
202 Next instruction
R1 = 400

399 450
XR = 100
400 700

AC
500 800

600 900
Addressing Effective Content
Mode Address of AC
Direct address 500 /* AC  (500) */ 800 702 325
Immediate operand 201 /* AC  500 */ 500
Indirect address 800 /* AC  ((500)) */ 300
Relative address 702 /* AC  (PC+500) */ 325 800 300
Indexed address 600 /* AC  (XR+500) */ 900
Register - /* AC  R1 */ 400
Register indirect 400 /* AC  (R1) */ 700
Autoincrement 400 /* AC  (R1)+ */ 700
Autodecrement 399 /* AC  -(R) */ 450

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