Unit II

16-bit Microprocessors
Why Transition :- Transition
S.No. 8085 Microprocessor 8086 Microprocessor
1. 8085 has 16 address line with 8 to 20 address with 16 to these lines also
these line also being used for data being used for data
2. 8 bit accumulator & six 8 bit All register 16 bit wide
general purpose register which
can be combined to form 16 bit
register for addressing
3. A program counter & stack 5 pointer register
pointer
4. Address 64 KB of memory 16 segments each with a length of 64 K
these memory segments are addressed
through four segment register
- Code Segment
- Stack Segment
- Data Segment
- Extra Segment
5. Single processing capability Multiprocessing capability
6. Only 256 instructions 64 K or 65536 instructions more than one
opcode can be used for the same
instruction
 8086 Registers and Internal Architecture
• There are two main functional logic
blocks in the 8086/88 processors:
– EU Execution Unit - execution of program
instructions
– BIU Bus Interface Unit - provides interface
to memory and I/O
1. controls the address, data, and control busses.
2. handles instruction fetch and data read/write
functions
 Bus Interface Unit
• BIU is the 8086’s interface to the outside world.
• It is responsible for performing all external bus
operations.
• BIU contains the segment registers, Instruction
pointer and bus control logic
• BIU has a mechanism called Instruction Stream
Queue to implement a Pipeline Architecture that
permits pre-fetch of up to 6 bytes of code.
 Control Unit
• Responsible for decoding and executing all
instructions
• Generates operand addresses
• Requests BIU to perform RD or WR cycles
to Memory or I/O
• After execution the EU tests and updates
the status flags
• Handles Jumps
 Execution Unit – Multipurpose Registers
• EAX Accumulator: AX is good at collecting the results of arithmetic and logic
operations. It is very strongly tied to the ALU (arithmetic and logic unit) and
can serve as the source and destination of instructions that use the ALU Thus when
you operate on a program variable over and over,AX can be used to hold the variable
during the long chain of instructions being executed and accumulate the end
result. So AX is called the accumulator.

• EBX Base Index: BX is a specialist of memory address arithmetic. Scalingof

offsets and indexing into a block of memory is better done using BX to hold the base
address. Some programmers call it the base register.
• ECX Count: CX is good at keeping count of operations. Loop instructions are designed by
the CPU architect to use CX as the count register. CL counts the number of shifts and rotate
operations done on other registers.
• EDX Data:DX points at addresses of Input/Output ports, peripheral controller devices & get
data in or out through Input/Output devices.
 Execution Unit – Multipurpose Registers
• ESP Stack Pointer: Used to offset into the stack segment to
address the stack. PUSH/POP, JSR
• EBP Base Pointer: Used to store a base memory location for data
transfers.
• EDI Destination Index: Typically used as an offset for the
destination memory location for string/byte transfers.
• ESI Source Index: Typically used as an offset for the source
memory location for string/byte transfers.
• The use of the base and offset registers EBX, ESP, EFP, EDI and
ESI will become clearer when addressing modes are covered.
 Execution Unit – Flag Register

C-Carry Flag This flag is set, when there is a carry out of MSB in case of
addition or a borrow in case of subtraction. For example, when two
numbers are added, a carry may be generated out of the most significant bit
position. The carry flag, in this case, will be set to ‘1’, In case, no carry is
generated, it will be ‘0’.
• Parity Flag (PF) - this flag is set to 1 when there is even number of one bits in
result, and to 0 when there is odd number of one bits.

• AC-Auxiliary Carry Flag This is set, if there is a carry from the lowest
nibble, i.e. bit three, during addition or borrow for the lowest nibble, i.e. bit
three, during subtraction.
 Execution Unit – Flag Register
• Z Zero: Zero Flag (ZF) - set to 1 when result is zero. For non-zero result this
flag is set to 0.

• Sign Flag (SF) - set to 1 when result is negative. When result is positive
it is set to 0. (This flag takes the value of the most significant bit.)

• T Trap: If this flag is set, the processor enters the single step
execution mode. In other words, a trap interrupt is generated
after execution of each instruction. The processor executes the
current instruction and the control is transferred to the Trap
interrupt service routine.
• Interrupt enable Flag (IF) - when this flag is set to 1 CPU reacts to
interrupts from external devices.
•D-Direction Flag This is used by string manipulation instructions. If this
flag bit is ‘0’, the string is processed beginning from the lowest address to
the highest address, i.e. auto incrementing mode. Otherwise, the string is
processed from the highest address towards the lowest address, i.e. auto
decrementing mode.

O-Overflow Flag
This flag is set, if an overflow occurs, i.e. if the result of a signed operation is large
enough to be accommodated in a destination register. For example, in case of the
addition of two signed numbers, if the result overflows into the sign bit, i.e. the
result is of more than 7 -bits in size in case of 8-bit signed operations and more
than I5-bits in size in case of I6-bit signed operations, then the overflow flag will
be set.
 BIS – Segment Registers
• CS Code Segment: Used to compute the starting address of the
section of memory holding code (restricted to 64K in REAL mode).
• DS Data Segment: Used to compute the starting address of the
section of memory holding data (restricted to 64K in REAL mode).
• SS Stack Segment: Used to compute the starting address of the
section of memory holding the stack (restricted to 64K in REAL
mode).
• ES Extra Segment: Additional data segment used by some string
instructions.
• FS&GS Additional segment registers in the 80386 (and up) for
program use.
Segmented Memory:-
Two types of memory organization are in popular use.
These are linear addressing & segmented addressing.

With linear addressing the entire memory space is

available to processor in one linear array. Segmented
memory divides the available memory space into
“ chunks” called segments. The processor is then limited
to accessing program instructions & data from the active
segments only.
As already stated, the 8086 addresses a segmented
memory. The complete physical address which is 20-
bits long is generated using segment and offset
registers, each 16-bits long.For generating a physical
address from contents of these two registers, the
content of a segment register also called as segment
address is shifted left bit-wise four times and to this
result, content of an offset register also called as offset
address is added, to produce a 20-bit physical address
For example, if
the segment address is 1005H and the offset is 5555H, then the
physical address is calculated as below
Segment address----- 1005H
Offset address------5555H
Segment address --------1005H--- 0001000000000101
Shifted by 4 bit positions---- 00010000000001010000
+
offset address-------0101 0101 0101 0101
Physical address------ 0001 0101 01011010 0101
155A5
Thus the segment addressed by the segment value 1005H can have offset
values from 0000H to FFFFH within it, i.e. maximum 64K locations may b
accommodated in the segment. Thus the segment register indicates the
base address of a particular segment, while the offset indicates the
distance of the required memory location in the segment from the base
address. Since the offset is a 16-bit number, each segment can have a
maximum of 64K locations. The bus interface unit has a separate adder to
perform this procedure for obtaining a physical address while addressing
memory. The segment address value is to be taken from an appropriate
segment register depending upon whether code, data or stack are to be
accessed, while the offset may be the content of IP, BX, SI, DI,SP or an
immediate 16-bit value, depending upon the addressing mode.
 Segmented addressing uses two components to specify a memory location: a segment
value and an offset within that segment. Ideally, the segment and offset values are
independent of one another. The best way to describe segmented addressing is with a
two-dimensional array. The segment provides one of the indices into the array, the offset
provides the other:
 (11MB)
MB

EA (Effective Address)

20-bit (5-byte) 64 KB +
Physical Segment
16-bit
Memory address

Appended byte 0H
Warning: A very common mistake people make when performing this computation is to
forget they are working in hexadecimal, not decimal. It is surprising to see how many
people add 9+1 and get 10h rather than the correct answer 0Ah.
 8086 Generating Physical
Addresses
CS
Memory System ES
Address Lines
SS
DS
19 0
Physical Address Dedicated Segment Registers

ADD BP
15 0 15 0
DI
Index Reg. Segment Reg. 0000
SI
SP
IP
Portion of BIU Circuitry
Dedicated Index Registers
In the 8086 chip architecture, the addressable memory space is divided into segments,
each of which can contain up to 64K of memory. Segments can only start on a
paragraph address. A paragraph address is a byte location that is evenly divisible by
16 bytes. Every 16th byte in memory contains segment number n. To access specific
bytes or words in memory, you must use an offset relative to the beginning of a
specified segment.
Together, a segment and an offset provide a segmented address that can locate any
byte in the 1 megabyte of address space in the 8086 processor.
CS
ES
physical address memory
SS
00000h
DS
paragraph 1
00010h
paragraph 2

00020h
paragraph 3 BP
DI
SI
SP
IP

•Each paragraph has phys. address that is multiple of 10h

• BIU is responsible for appending 0000 to Segment

– only need 16-bit segment registers
 Segmented Memory (x86
Style)FFFFFh
• Segment Registers:
Code
Segment
– Point to Base Address
Segment
Registers
Extra
CS Segment • Index Registers:
ES fragmentation
SS
DS
Stack
Segment
– Contain Offset Value

• Notation (Segmented Address):

Data
Segment
– CS:IP
– DS:SI
– ES:DI
00000h – SS:BP
System – SS:SP
Memory
 Memory Data Organization
• 1 Word = 16 bits
• Byte Addressable
• Little Endian Arrangement
– MSB (Most Significant Byte) at Higher Address

offset
072CH 18H AD5FCH
or • Segment Address = ACEDH
072BH A3H AD5FBH
logical • Logical Address = 0724H
072AH 7EH AD5FAH
address 0729H 69H AD5F9H • Physical Address
0728H AAH AD5F8H = ACED0H + 0724H
0727H 2EH AD5F7H = AD5F4H
0726H 00H AD5F6H • M[ACED:0724]
0725H 55H AD5F5H = M[AD5F4] (word read)
0724H 02H AD5F4H = 5502H
0723H 72H AD5F3H
increasing 0722H 11H AD5F2H

0724H 0725H
0H 2H 5H 5H hex
0000 0010 0101 0101 binary
 Register Transfer Language

• When describing memory/register operations,

will use Register Transfer Language (RTL)
rega  regb transfer regb to rega (ax  cx)
rega  reg a op reg b rega gets result of rega op regb
rega  M[location N] transfer contents of memory location N
to reg a (mem read operation)
M[location N]  rega transfer reg a to memory location N
(write operation)

Size of memory operand (byte, word, dword) depends on size of

register or is indicated by instruction opcode.
 Memory Read Operations

Byte Read:
offset al  M[0724h]
072CH 18H AD5FCH
or after: al = 02h
072BH A3H AD5FBH
logical
072AH 7EH AD5FAH
address 0729H 69H AD5F9H Word Read:
0728H AAH AD5F8H ax  M[0724h]
0727H 2EH AD5F7H
after: ax = 5502h
0726H 00H AD5F6H

0725H 55H AD5F5H

0724H 02H AD5F4H Dword Read

0723H 72H AD5F3H eax  M[0724h]
increasing 0722H 11H AD5F2H after: eax = 2E005502h
 Memory Write Operations
Assume EAX = FAC4237B h
Byte Write: M[0724h]  al

before: after:
072CH 18H AD5FCH
072CH 18H AD5FCH
072BH A3H AD5FBH 072BH A3H AD5FBH
072AH 7EH AD5FAH
072AH 7EH AD5FAH
0729H 69H AD5F9H
0729H 69H AD5F9H
0728H AAH AD5F8H 0728H AAH AD5F8H
0727H 2EH AD5F7H
0727H 2EH AD5F7H
0726H 00H AD5F6H
0726H 00H AD5F6H
0725H 55H AD5F5H 0725H 55H AD5F5H
0724H 7BH AD5F4H
0724H 02H AD5F4H
0723H 72H AD5F3H
0723H 72H AD5F3H
0722H 11H AD5F2H 0722H 11H AD5F2H
 Memory Write Operations
(cont.)
Assume EAX = FAC4237B h
Word Write: M[0724h]  ax

before: after:
072CH 18H AD5FCH
072CH 18H AD5FCH
072BH A3H AD5FBH 072BH A3H AD5FBH
072AH 7EH AD5FAH
072AH 7EH AD5FAH
0729H 69H AD5F9H
0729H 69H AD5F9H
0728H AAH AD5F8H 0728H AAH AD5F8H
0727H 2EH AD5F7H
0727H 2EH AD5F7H
0726H 00H AD5F6H
0726H 00H AD5F6H
0725H 55H AD5F5H 0725H 23H AD5F5H
0724H 7BH AD5F4H
0724H 02H AD5F4H
0723H 72H AD5F3H
0723H 72H AD5F3H
0722H 11H AD5F2H 0722H 11H AD5F2H
 Memory Write Operations
(cont.)
Assume EAX = FAC4237B h
DWord Write: M[0724h]  eax

before: after:
072CH 18H AD5FCH
072CH 18H AD5FCH
072BH A3H AD5FBH 072BH A3H AD5FBH
072AH 7EH AD5FAH
072AH 7EH AD5FAH
0729H 69H AD5F9H
0729H 69H AD5F9H
0728H AAH AD5F8H 0728H AAH AD5F8H
0727H FAH AD5F7H
0727H 2EH AD5F7H
0726H C4H AD5F6H
0726H 00H AD5F6H
0725H 55H AD5F5H 0725H 23H AD5F5H
0724H 7BH AD5F4H
0724H 02H AD5F4H
0723H 72H AD5F3H
0723H 72H AD5F3H
0722H 11H AD5F2H 0722H 11H AD5F2H
 Default Segment/Index Pairs

Type of Memory Reference Default Segment Base Alternate Segment Base Offset

Instruction Fetch CS None IP

Stack Operation SS None SP
Variable (except following) DS CS, ES, SS Effective Address
- String Source DS CS, ES, SS SI
- String Destination ES None DI
- BP used as Base Register SS CS, DS, ES Effective Address
- BX Used as Base Register DS CS, ES, SS Effective Address
Advantage of Segmented Memory
Having separate data and code segments is that one program can work on
several different set of data . This is done by reloading register DS to point to the
new data.

A multitasking environment in which the 8086 is running several different

programs. An inactive program can be temporarily saved on magnetic disc and a
new program brought in to take its place-without concern for the physical
location of this new program. Such program are said to be relocatable meaning
they will run at any location in memory. The requirements for writing relocatable
programs are that no reference be made to physical addresses and no changes to
the segments registers are allowed.

Disadvantages of Segmented Memory

Segmented memory introduces extra complexity in both hardware (memory
addresses require two register-an offset register and a segment register) and
software(programs are limited to the segment size 64K bytes).
Signal Descriptions Of 8086
The Microprocessor 8086
is a 16-bit CPU available
in three clock rates, i.e.
5,8 and 10MHz,packaged
in a 40 pin .The 8086
operates in single
processor or
multiprocessor
configurations to achieve
high performance.Pins
serve a particular
function in minimum
mode(single processor
mode)and other function
in maximum
mode(multiprocessor
mode) configuration
8086 Pin Assignment
AD15-ADo -These are the time multiplexed memory I/O
address and data lines. Address remains on the lines during
TI state, while the data is available on the data bus during
T2,T3,Tw and T4. Here T1,T2,T3,T4 and Tw are the clock states of
a machine cycle. Tw is a wait state .

A19/S6,A18/S5,A17/S4, A16/S3 These are the time multiplexed

address and status lines. During Tl these are the most
significant address lines for memory operations. During
memory or I/O operations, status information is available on
those lines for T2, T3 and T4. The S4 and S3 combinedly
indicate which segment register is presently being used for
memory accesses.
BHE/S7-Bus High Enable/Status The bus high enable signal is
used to indicate the transfer of data over the higher order
(D15-D8) data bus as shown in Table . It goes low for the data
transfers over D15-D8 and is used to derive chip selects of odd
address memory bank or peripherals. BHE is low during T1
for read, write and interrupt acknowledge cycles, when ever a
byte is to be transferred on the higher byte of the data bus.
The status information is available during T2,T3 and T4.

RD-Read Read signal, when low indicates the peripherals

that the processor is performing a memory or I/O read
operation. RD is active low and shows the state for T2, T3,
Tw of any read cycle.
READY This is the acknowledgement from the slow devices
or memory that they have completed the data transfer. The
signal made available by the devices is synchronized by the
8284A clock generator to provide ready input to the 8086. The
signal is active high.

INTR-Interrupt Request -This is a level triggered input. This is

sampled during the last clock cycle of each instruction to
determine the availability of the request. If any interrupt
request is pending, the processor enters the interrupt
acknowledge cycle. This can be internally masked by
resetting the interrupt enable flag. This signal is active high
and internally synchronized.

TEST This input is examined by a 'WAIT' instruction. If the

TEST input goes low, execution will continue, otherwise the
processor remains in an idle state. The input is synchronized
internally during each clock cycle on leading edge of clock.
NMI-Non-maskable Interrupt This is an edge-triggered input
which causes a Type2 interrupt. The NMI is not maskable
internally by software. A transition from low to high initiates
the interrupt response at the end of the current instruction.
This input is internally synchronized .
RESET This input causes the processor to terminate the
current activity and start execution from FFFF0H. The signal
is active high and must be active for at least four clock
cycles. It restarts execution when the RESET returns low.
RESET is also internally synchronized .
CLK-Clock Input The clock input provides the basic timing
for processor operation and bus control activity. Its an
asymmetric square wave with 33% duty cycle. The range of
frequency for different 8086 versions is from 5MHz to
10MHz.
Vcc +5V power supply for the operation of the internal
circuit.
ALE-Address Latch Enable This output signal indicates the
availability of the valid address on the address/data lines, and is
connected to latch enable input of latches. It is a HIGH pulse active
during T1 of any bus cycle.
DT /R -Data Transmit/Receive This output is used to decide the
direction of data flow through the transreceivers (bi-directional
buffers). When the processor sends out data, this signal is high
and when the processor is receiving data, this signal is low.
Logically, this is equivalent to S 1 in maximum mode. Its timing is
the same as M/I/O.
HLDA-Hold/Hold Acknowledge When the HOLD line goes high,
it indicates to the processor that another master is requesting
the bus access. The processor, after receiving HOLD request,
issues the hold acknowledge signal on HLDA pin, in the middle
of the next clock cycle after completing the current bus
(instruction) cycle. At the same time,the processor floats the
local bus and control lines. When the processor detects the
HOLD line, it lowers the HLDA signal. HOLD is an asynchronous
GND ground for the internal circuit.
MN/MX The logic level at this pin decides whether the
processor-is to operate in either minimum (single processor)
or maximum (multiprocessor) mode.
The following pin functions are for the minimum mode
operation of 8086
M/I/O -Memory/lO This is a status line logically equivalent to
S2 in maximum mode. When it is low, it indicates the CPU is
having an I/O operation, and when it is high, it indicates that
the CPU is having a memory operation. This line becomes
active in the previous T4 and remains active till final T4 of the
current cycle.
INTA -Interrupt Acknowledge This signal is used as a read
strobe for interrupt acknowledge cycles. In other words,
when it goes low, it means that the processor has accepted
the interrupt. It is active low duringT2, T3 and Tw of each
interrupt acknowledge cycle.
DEN DATA ENABLE: provided as an output enable for the 8286/8287
in a minimum system which uses the transceiver. DEN is active LOW
during each memory and I/O access and for INTA cycles. For a read or
INTA cycle it is active from the middle of T2 until the middle of T4,
while for a write cycle it is active from the beginning of T2 until the
middle of T4.
S2, S1, S0-Status Lines These are the status lines which
reflect the type of operation,these being carried out by the
processor. These become active during T4 of the previous
cycle and remain active during T1 and T2 of the current bus
cycle. The status lines return to passive state during T3 of
the current bus cycle so that they may again become active
for the next bus cycle during T4. Any change in these lines
during T3 indicates the starting of a new cycle, and return to
passive state indicates end of the bus cycle. These status
lines are encoded in table
LOCK This output pin indicates that other system bus
masters will be prevented from gaining the system bus, while
the LOCK signal is low. The LOCK signal is activated by the
'LOCK' prefix instruction and remains active until the
completion of the next instruction. This floats to tri-state off
during "hold acknowledge" .When the CPU is executing a
critical instruction which requires the system bus, the LOCK
prefix instruction ensures that other processor connected in
the system will not gain the control the bus. The 8086, while
executing the prefixed instruction, asserts the bus lock signal
output, which may be connected to an external bus
controller.
QS1, QS0-Queue Status These lines give information about the
status of the code- prefetch queue. These are active during the
CLK cycle after which the queue operation is performed. These
are encoded as shown in table

This modification in a simple fetch and execute architecture of

a conventional microprocessor offers an added advantage of
pipelined processing of the instructions. The 8086 architecture
has a 6-byte instruction prefetch queue. Thus even the largest
(6-bytes) instruction can be prefetched from the memory and
stored in the prefetch queue. This results in a faster execution
of the instructions.
In 8085, an instruction (opcode and operand) is fetched, de-
coded and executed and only after the execution of this
instruction, the next one is fetched. By prefetching the
instruction, there is a considerable speeding up in
instruction execution in 8086. This scheme is known as
instruction pipelining.
The first byte is a complete opcode in case of some instructions (one
byte opcode instruction) and it is a part of opcode, in case of other
instructions (two byte long opcode instructions), the remaining part of
opcode may lie in the second byte. But invariably the first byte of an
instruction is an opcode. These opcodes along with data are fetched
and arranged in the queue. When the first byte from the queue goes for
decoding and interpretation, one byte in the queue becomes empty and
subsequently the queue is updated. The microprocessor does not
perform the next fetch operation till at least two bytes of the instruction
queue are emptied. The instruction execution cycle is never broken for
fetch operation. After decoding the first byte, the decoding circuit
decides whether the instruction is of single opcode byte or double
opcode byte. If it is single opcode byte, the next bytes are treated as
data bytes depending upon the decoded instruction length, otherwise,
the next byte in the queue is treated as the second byte of the
instruction opcode. The second byte is then decoded in continuation
with the first byte to decide the instruction length and the number of
subsequent bytes to be treated as instruction data. The queue is
updated after every byte is read from the queue but the fetch cycle is
initiated by BIU only if at least two bytes of the queue are empty and the
EU may be concurrently executing the fetched instructions.
The next byte after the instruction is completed is again the
first opcode byte of the next instruction. A similar procedure
is repeated till the complete execution of the program. The
main point to be noted here is, that the fetch operation of the
next instruction is overlapped with the execution of the
current instruction. As shown in the architecture, there are
two separate units, namely, execution unit and bus interface
unit. while the execution unit is busy in executing an
instruction, after it is completely decoded, the bus interface
unit may be fetching the bytes of the next instruction from
memory, depending upon the queue status .
RQ/GT0, RQ/GT1-Request/Grant These pins are used by other local
bus masters, in maximum mode, to force the processor to
release the local bus at the end of the processor's current bus
cycle. Each of the pins is bi-directional with RQ/GT 0 having
higher priority than RQ/ GT1. RQ/GT pins have internal pull-up
resistors and may be left unconnected. The request/ grant
sequence is as follows:

1. A pulse one clock wide from another bus master requests the
bus access to 8086.
2. During T4 (current) or T 1 (next) clock cycle, a pulse one clock
wide from 8086 to the requesting master, indicates that the
8086 has allowed the local bus to float and that it will enter the
"hold acknowledge" state at next clock cycle. The CPU's bus
interface unit is likely to be disconnected from the local bus of
the system.
3. A one clock wide pulse from the another master indicates to
8086 that the 'hold' request is about to end and the 8086 may
regain control of the local bus at the next clock cycle.
Thus each master to master exchange of the local bus is a
sequence of 3 pulses. There must be at least one dead
clock cycle after each bus exchange. The request and grant
pulses are active low. For the bus requests those are
received while 8086 is performing memory or I/O cycle, the
granting of the bus is governed by the rules as discussed in
case of HOLD, and HLDA in minimum mode.
 8086 Addressing Modes

• Microprocessor needs
memory address to
access data from the
memory.
• Assembly language
may use several
addressing modes to
accomplish this task.
 8086 Register Addressing Modes
Most 8086 instructions can operate on the 8086's general
purpose register set. By specifying the name of the register as
an operand to the instruction, you may access the contents of
that register. Consider the 8086 mov (move) instruction:
mov destination, source
This instruction copies the data from the source operand to the
destination operand. The eight and 16 bit registers are
certainly valid operands for this instruction. The only restriction
is that both operands must be the same size. Now let's look at
some actual 8086 mov instructions:
mov ax, bx ;Copies the value from BX into AX
mov dl, al ;Copies the value from AL into DL
Remember, the registers are the best place to keep often used
variables.
Mov makes a copy of Source and stores this value into Dest.
This instruction does not affect the original contents of Source.
It overwrites the previous value in Dest.
• The P has a set of rules that apply whenever memory is addressed,
which define the segment and offset register combination used by
certain addressing modes[By Default].
 Addressing Modes
1 Direct (absolute) memory addressing
– Instruction specifies the address of the data
– The data address (in the instruction) can be the full
physical address on the memory architecture in use
 Addressing Modes
2 Register addressing
– When operands are held in the registers, e.g. MOV A, B
– Register addressing instructions are the fastest and use
the fewest bits compared to others
– Some call it inherent addressing also
3 Immediate addressing
– Used for constant values know when the program is written
– Data (i.e. constant values) can immediately follow the instruction
 4.The Register Indirect Addressing Modes
• Register indirect addressing– Also called pointer register addressing
– Instruction contains address of the register that contains the address of the
needed data
– A 2-level addressing mode
There are four forms of this addressing mode on the 8086, best demonstrated
by the following instructions:
mov al, [bx]
mov al, [bp]
mov al, [si]
mov al, [di]

You can use the segment override prefix symbols if you wish to access data in
different segments. The following instructions demonstrate the use of these
overrides:
mov al, cs:[bx]
mov al, ds:[bp]
mov al, ss:[si]
mov al, es:[di]
 5 Indexed addressing
– Finds a memory location based on an index
– Instruction contains the starting address of the array,the index
register contains the offset to reach the data being addressed
The indexed addressing modes use the following syntax:
mov al,disp[bx]
mov al,disp[bp]
mov al,disp[si]
mov al,disp[di]
The offsets generated by these addressing modes are the sum of the constant and the
specified register. The addressing modes involving bx, si, and di all use the data
segment, the disp[bp] addressing mode uses the stack segment by default. As with the
register indirect addressing modes, you can use the segment override prefixes to specify
a different segment

mov al, ss:disp[bx]

mov al, es:disp[bp]
mov al, cs:disp[si]
mov al, ss:disp[di]
 6.Based Indexed Addressing Modes

– Index register has the starting address of the data table

– Instruction specifies the index register (ID) and offset, not the full
starting address of data table; useful for transferring data

mov al,[bx][si]
mov al,[bx][di]
mov al,[bp][si]
mov al,[bp][di]
 7.Based Indexed Plus Displacement Addressing Mode

These addressing modes are a slight modification of the base/indexed addressing modes with the
addition of an eight bit or sixteen bit constant. The following are some examples of these
addressing modes:

mov al, disp[bx][si]

mov al, disp[bx+di]
mov al, [bp+si+disp]
mov al, [bp][di][disp]
 8 Relative addressing
– Effective address = (PC) + offset
– Used for branching short distances in well-written programs
 9 • Relative addressing with index plus displacement

Effective address = (PC) + (index register) + displacement

10 • Stack addressing
– Saves the return address when the program calls a subroutine
– After fetching the jump op code and subroutine address, the PC is
made to point to the next op code (the return address)
– This return address is pushed onto the stack by the program
– The “return” instruction at the end of the subroutine pops the
return address from the stack, incrementing the stack pointer