CS305 : MICROPROCESSORS & MICROCONTROLLERS

MODULE -3 : 8086 MICROPROCESSOR

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 **What is an Interrupt?**

 An interrupt is a signal that indicates an event has occurred and requires

immediate attention from the processor.
 These events can be generated by external devices such as keyboard, mouse,
or timer, or they can be software-generated interrupts.
 When an interrupt occurs, the processor temporarily suspends the execution
of the current program and transfers control to a specific interrupt handler
routine to handle the event.

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 8086 Microprocessor - Interrupts

 The process of interrupting the normal program execution

to carry out a specific task is referred to as interrupt

 The meaning of ‘Interrupts’ is to break the sequence of

operation

 While the microprocessor is executing a program, an ‘

interrupt’ breaks the normal sequence of execution of
instructions, diverts its execution to some other program
called Interrupt Service Routine (ISR)

 After executing ISR, IRET returns the control back again

to the main program

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 Interrupt processing flow chart

Main program

Interrupt N
Req

Accept N
Interrupt

Get interrupt
vector

Jump to ISR
Save PC

Load PC

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Interrupt Cycle of 8086 Microprocessor

The interrupt cycle of the 8086 processor allows it to handle interrupts from external
devices or software in a systematic manner

The interrupt cycle of the 8086 processor consists of several phases:

1) Interrupt Request (IRQ)

2) Interrupt Acknowledge (INTA)
3) Interrupt Vector Fetch
4) Interrupt Service Routine (ISR)
5) Interrupt Return

1) Interrupt Request (IRQ)

 An interrupt request is generated by an external device or software

 The interrupt request is sent to the Interrupt Controller, which prioritizes and manages
interrupts.
 The Interrupt Controller sends an interrupt signal to the 8086 processor.

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 2) Interrupt Acknowledge (INTA)
 The 8086 processor receives the interrupt signal and sends an acknowledgement signal (INTA) to the
Interrupt Controller
 The INTA signal informs the Interrupt Controller that the processor is ready to receive interrupt data

3) Interrupt Vector Fetch

 The Interrupt Controller sends the interrupt vector number to the processor
 The interrupt vector number corresponds to a specific interrupt service routine

4) Interrupt Service Routine (ISR)

 The current state of the processor, including the contents of registers, is saved on the stack to ensure
a smooth transition to the interrupt service routine
 The processor starts executing the interrupt service routine

5) Interrupt Return

 Once the interrupt handler routine is executed, the processor restores the saved state from the stack.
 The program execution continues from the point where it was interrupted.

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Classification of Interrupts

I. Hardware and software Interrupts

 The interrupts initiated by external hardware by sending an appropriate signal to the interrupt pin
of the processor is called hardware interrupt
 The software interrupts are program instructions

II. Vectored and Non vectored Interrupts

 Vectored Interrupts are those which have fixed vector address (starting address of sub-routine-
Vector Address) and after executing these, program control is transferred to that address
 Non-Vectored Interrupts are those in which vector address is not predefined. The interrupting
device should supply the address of the ISR to be executed in response to the interrupt

III. Maskable and Non maskable Interrupts

 The interrupts whose request can be either accepted or rejected by the processor are called
Maskable interrupts.
 The interrupts whose request has to be definitely accepted (cannot be rejected) by the processor
are called non-maskable interrupts

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Interrupt Vector Table (IVT)
IVT is a structured list containing the addresses of ISR for various interrupts.

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 8086 Microprocessor - Interrupts

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 Hardware Interrupts

Hardware interrupt is caused by any peripheral device by sending a signal through a

specified pin to the microprocessor.

The 8086 has two hardware interrupt pins- NMI and INTR

1. NMI is a non-maskable interrupt

2. INTR is a maskable interrupt

One more interrupt pin associated is INTA called interrupt acknowledge.

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 Software Interrupts

 These are instructions that are inserted within the program to generate
interrupts
 There are 256 software interrupts in 8086 microprocessor
 The instructions are of the format INT type
INT n ; where type n ranges from 00 to FF
(0 to 255)

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 8086 µP - Interrupt Types

256 interrupts are divided into groups

Predefined (Reserved) Interrupts

1. Type 0 Interrupt – Divide by zero

2. Type 1 Interrupt – Single step mode

3. Type 2 Interrupt - Non maskable Interrupt

4. Type 3 Interrupt – Breakpoint interrupt

5. Type 4 Interrupt – Interrupt on Overflow

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 Predefined (Reserved) Interrupts
1. Type 0 Interrupt – Divide by zero (Divide error interrupt)
 Interrupt represents division by zero situation (K/0 = ∞ )

2. Type 1 Interrupt – Single step mode

 Interrupt represents single-step execution during the
debugging of a program
 Used for executing the program in single step mode by
setting TRAP flag ( TF = 1)
3. Type 2 Interrupt - Non maskable Interrupt
 Interrupt represents non-maskable NMI interrupt

4. Type 3 Interrupt – Breakpoint interrupt

 Used for providing breakpoints in the program –
INT 03 ; Stop the program
5. Type 4 Interrupt – Interrupt on Overflow
 Used to handle any overflow error
INTO ; Interrupt Overflow 06/09/2024
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Difference Between Interrupt and Polling

I. Interrupt

 Interrupt is a hardware mechanism in which, the device notices the CPU that it requires its
attention. So when CPU gets an interrupt signal through the interrupt-request line, CPU stops the
current process and respond to the interrupt by passing the control to interrupt handler which
services device

II. Polling

 The process in which the CPU constantly checks the status of the device- to see if it needs the
CPU's attention is called polling. It is basically a protocol in which the CPU services the I/O
devices.
 It is an inefficient method because most of the time much of the CPU’s time is wasted on
unnecessary polls

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Difference between Interrupt and Polling

Sl Interrupt Polling
No.
1 In interrupt, the device notices the Whereas, in polling, CPU steadily
CPU that it requires its attention. checks whether the device needs
attention.
2 its a hardware mechanism. n this protocol, the CPU services the
device.
3 An interrupt handler services/works While in polling, the device is serviced
with the device. by CPU.
4 Interrupt-request line indicates that The command-ready bit indicates that
the device needs to be serviced. the device needs to be serviced.
5 Interrupts save the CPU cycles. Polling wastes many of the CPU
cycles.
6 Interrupts can occur at any point in CPU polls the devices at regular
time. intervals of time.
7 It becomes inefficient if devices Polling becomes inefficient when the
frequently interrupt the CPU. CPU rarely finds a device that is ready
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 Peripheral Devices
1) 8259 – Programmable Interrupt Controller
2) 8255 – Programmable Peripheral Interface
3) 8279 – Keyboard/Display Controller
4) 8257 – DMA Controller

Programmable Interrupt Controller 8259

 It is used to expand the interrupts of the processor

 8259 can accept 8 interrupt requests and allow one by one to the processor through INTR pin
 The 8059s can be cascaded to accept a maximum of 64 interrupts

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Pin Details of 8259

 28 pin IC packed in DIP

 Pins – Address/Data/Interrupt request/Read/Write/Cascade/Supply

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 Functional Block diagram (Architecture) of 8259

8 Functional Units
1) IRR - IR0-IR7
2) PR –
IR0 – highest priority
IR7 – lowest priority
3) IMR
4) ISR – Keep track of current
ISR
5) Control Logic – INT & INTA’
6) Data bus buffer – D0-D7
7) Read/Write Logic –
RD’, WR’,A0, CS’
8) Cascade Buffer-
CAS0-CAS2, SP’/EN’

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Interfacing of 8259 with 8086 Microprocessor
 Type of interrupt signal
(Level/Edge triggered)
 Type of processor
 Type number
 Masking of interrupts
 Priority of interrupts

Steps:
 Receive the interrupt IR0-IR7
 Check for its priority and masking
 8259 will send INT signal to INTR pin of 8086
 8086 send acknowledge signal to 8259 through INTA’ pin
 Receive the type number from 8259
 Generate 20 bit vector table address
 Start servicing the interrupt by executing the ISR stored in the vector address
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