Scribd
Upload
138 views14 pages

Ocv-On Chip Variation: Presented by Sriram Srinath Mentor Mubeena Banu

OCV (On Chip Variation), AOCV (Advance On Chip Variation) and POCV (Parametric On Chip Variation) have been done. Why and how a new variation model has evolved over the previous one and how it is better in terms of timing pessimism have also been discussed.

Uploaded by

Sriram Srinath
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
138 views14 pages

Ocv-On Chip Variation: Presented by Sriram Srinath Mentor Mubeena Banu

OCV (On Chip Variation), AOCV (Advance On Chip Variation) and POCV (Parametric On Chip Variation) have been done. Why and how a new variation model has evolved over the previous one and how it is better in terms of timing pessimism have also been discussed.

Uploaded by

Sriram Srinath
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 14

OCV-ON CHIP

VARIATION
MENTOR PRESENTED BY
MUBEENA BANU SRIRAM SRINATH
WHAT IS OCV?
•In VLSI, OCV stands for On-Chip Variation. It is a method
used to model the impact of process variations on the timing
characteristics of an Integrated Circuit (IC).
•The final output which goes to the fabrication team after
physical design and signoff in the ASIC design flow is
the .gds (Graphical Design System) file.
•Using this file fabrication team will do the IC packaging.
•We have the same gds data for all the ICs in all die but the
location of dia is different on the wafer. If the gds is same
for all the die then ideally electrical characteristics of all the
ICs should have the same.
WHAT IS OCV?
• But practically it is not. The IC manufactured in
different die has variation in their electrical
characteristics.
• For example, let us consider three dies at different
locations on the wafer as shown in the figure. Die-1 is
situated at the centre of the wafer, die-3 at the edge of
wafer and die-2 in between the centre and outer edge.
• So now the question is different IC’s have different
locations then from where these varaitions occurs?

ALL THESE VARAITIONS COME FROM


FABRICATION PROCESS
SOURCES OF VARIATIONS
VARIATION IN PROCESS
•Drain current of Nmos transistor in linear region.

•Parameters which depend on fabrication process are:


1. Gate Oxide Thickness (tox)
2. With of transistor (W)
3. Length of the transistor (L)
4. and Threshold voltage of Transistor
VARIATION IN PROCESS

•Photolithography
• OPC
•RDF
•Etching
• CMP
• OTV
VARIATION IN PROCESS
•CONCLUSION
•There are chances of process parameters in many ways while the chip is being
fabricated.
•These process variation cause will cause the drain current (Id) of transistors and
ultimately the variation in the delay of standard cells
•Delay of standard cells = f(R) = f(Id) = f(W,L,Tox)
VARIATION IN VOLTAGE
•Standard cells get power from the power pads through power rails and strips.
•It is possible that the effective interconnect length (Rails + Stripe ) for two
standard cells placed in different locations could be different.
•As every interconnect has a finite IR drop, so if the interconnect length is
different, There will be variation in power supply of standard cells placed at
different location
•So these will cause a variation in supply voltage of standard cells inside the
chip and standard cell will offer different delay based on location/supply
voltage.
VARIATION IN TEMPERATURE
•Transistors characteristic is very strongly dependent on
the temperature.
• One factor in ambient temperature on which chip is
being operated. But transistor's characteristics mainly
depends on Junction temperature.
•Junction temperature is sum of ambient temperature and
temperature raised due to power dissipation of transistors.
•Based on placement density and power requirements,
There are formation of local hotspot on a
particular area of core.
EFFECTS OF ON-CHIP
VARIATION
• On-chip variations are very unpredictable and non-systematic in
nature.it causes variations in the delay and transition of the standard
cells.

• On-chip variations cause some additional change in delay of standard


cells. If we don’t take care of these variations while time closer, This
effect may cause post silicon failure.
HOW TO TAKE CARE OF OCV
•To take care of On-chip variation we add some pessimism in timing of standard cells

•Basically we apply _+x% additional delay over the standard cells, which is called derete to model
the On-chip variations

•Derate factor is the extra timing pessimism applied to the delay of standard cells to do STA.

•In case of setup analysis, data path and launch clock path positive derate will be applied and in
capture clock path negative derate will be applied. And vice-versa for Hold analysis.
SETUP AND HOLD ANALYSIS
HOW TO TAKE CARE OF OCV?
•In OCV we apply a fixed derete to all the standard cells which is highly pessimistic. To overcome the
timing pessimism later industry moved to AOCV and then POCV
OCV AOCV POCV
On-chip Variation Advanced On-chip Variation Parametric On-chip Variation
Fixed derete Distance and Logic Depth based derete Staticial based POCV Coefficient

reduced pessimism
THANK YOU

You might also like