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Introduction To VHDL

The document provides an introduction to VHDL including details about case sensitivity, white space, comments, parentheses, statements, identifiers, reserved words, entities, architectures, concurrent statements, and the signal assignment operator. It also includes an example problem and solution for implementing a logic equation in VHDL.

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Nandhini G
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© © All Rights Reserved
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Download as PPTX, PDF, TXT or read online on Scribd
20 views

Introduction To VHDL

The document provides an introduction to VHDL including details about case sensitivity, white space, comments, parentheses, statements, identifiers, reserved words, entities, architectures, concurrent statements, and the signal assignment operator. It also includes an example problem and solution for implementing a logic equation in VHDL.

Uploaded by

Nandhini G
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Introduction to VHDL

Case Sensitivity
VHDL is not case sensitive. This means that the two statements shown below have the exact
same meaning (don’t worry about what the statement actually means though).

Dout <= A and B;

doUt <= a AnD b;


White Space
VHDL is not sensitive to white space (spaces and tabs) in the source document. The two
statements have the exact same meaning.

nQ <= In_a or In_b ;


nQ<=in_a OR in_b;
Comments
Comments in VHDL begin with the symbol “--” (two consecutive dashes). The VHDL synthesizer
ignores anything after the two dashes and up to the end of the line in which the dashes appear.
The below picture shows two types of commenting styles. Unfortunately, there are no block-style
comments (comments that span multiple lines but do not require comment marks on every line)
available in VHDL.
Parentheses
VHDL is relatively lax on its requirement for using parentheses. Like other computer languages,
there are a few precedence rules associated with the various operators in the VHDL language.
Though it is possible to learn all these rules and write clever VHDL source code that will ensure
the readers of your code are left scratching their heads, a better idea is to practice liberal use of
parentheses to ensure the human reader of your source code understands the purpose of the
code
VHDL Statements
Similar to other algorithmic computer languages, every VHDL statement is terminated with a
semicolon. This fact helps when attempting to remove compiling errors from your code since
semicolons are often omitted during initial coding.

Identifiers

An identifier refers to the name given to various items in VHDL. Examples of identifiers in
higher-level languages include variable names and function names. Examples of identifiers in
VHDL include variable names, signal names and port names (all of which will be discussed
soon). Listed below are the hard and soft rules (i.e. you must follow them or you should follow
them), regarding VHDL identifiers.
ˆ Identifiers should be self-describing. In other words,
the text you apply to identifiers should provide
information as to the use and purpose of the item the
identifier represents. ˆ Identifiers can be as long as you
want (contain many characters).

ˆ Identifiers can only contain a combination of letters


(A-Z and a-z), digits (0-9) and the underscore
character (“ ”).

ˆ Identifiers must start with an alphabetic character.

Identifiers must not end with an underscore and must


never have two consecutive underscores.
Reserved Words
There is a list of words that have been assigned special meaning by the VHDL language. These
special words, usually referred to as reserved words, cannot be used as identifiers when writing
VHDL code. A partial list of reserved words that you may be inclined to use appears below.
Entity
The VHDL entity construct provides a method to abstract the functionality of a circuit description
to a higher level. It provides a simple wrapper for the lower-level circuitry. This wrapper
effectively describes how the black box interfaces with the outside world. Since VHDL describes
digital circuits, the entity simply lists the various inputs and outputs of the underlying circuitry. In
VHDL terms, the black box is described by an entity declaration. The syntax of the entity
declaration is shown below.
The above picture shows an example of a black box and the VHDL code used to describe it.
Listed below are a few points to note about the code.

Most of the points deal with the readability and understandability of the VHDL code. ˆ Each port
name is unique and has an associated mode and data type. This is a requirement. ˆ The VHDL
compiler allows several port names to be included on a single line. Port names are separated by
commas. Always strive for readability.
VHDL Standard Libraries
The VHDL language as many other computer languages, has gone through a long and intense
evolution. Among the most important standardization steps we can mention are the release of
the IEEE Standard 1164 package as well as some child standards that further extended the
functionality of the language.
Architecture
The VHDL entity declaration, introduced before, describes the interface or the external
representation of the circuit. The architecture describes what the circuit actually does. In other
words, the VHDL architecture describes the internal implementation of the associated entity. As you
can probably imagine, describing the external interface to a circuit is generally much easier than
describing how the circuit is intended to operate. This statement becomes even more important as
the circuits you are describing become more complex.
Concurrent Statements
At the heart of most programming languages are the statements that form a majority of the
associated source code. These statements represent finite quantities of actions to be taken. A
statement in an algorithmic programming language such as C or Java represents an action to be
taken by the processor. Once the processor finishes one action, it moves onto the next action
specified somewhere in the associated source code.

VHDL programming is significantly different. Whereas a processor steps one by one through a set of
statements, VHDL has the ability to execute a virtually unlimited number of statements at the same
time and in a concurrent manner (in other words, in parallel). Once again, the key thing to remember
here is that we are designing hardware. Parallelism, or things happening concurrently, in the context
of hardware is a much more straightforward concept than it is in the world of software.
As a consequence of the concurrent nature of VHDL statements, the three chunks of
code appearing below are 100% equivalent to the code shown
Signal Assignment Operator “<=”
Algorithmic programming languages always have some type of assignment operator. In C or Java, this
is the well-known “=” sign. In these languages, the assignment operator signifies a transfer of data
from the right-hand side of the operator to the left-hand side. VHDL uses two consecutive characters
to represent the assignment operator: “<=”. This combination was chosen because it is different from
the assignment operators in most other common algorithmic programming languages. The operator is
officially known as a signal assignment operator to highlight its true purpose. The signal assignment
operator specifies a relationship between signals. In other words, the signal on the left-hand side of
the signal assignment operator is dependent upon the signals on the right-hand side of the operator.

Syntax:

<target> <= <expression> ;


Problem:

Write the VHDL code to implement the function expressed by the


following logic equation:
F3 = L’ · M’ · N + L · M
Solution:
Thank You!
Have a nice day 

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